JP3238529B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an element array in which semiconductor elements are arranged in a matrix, wherein a plurality of semiconductor elements are arranged in a column direction in the element array. And a method for forming the same.

[0002]

2. Description of the Related Art As a semiconductor device having an element array in which semiconductor elements are arranged in a matrix, there is, for example, a DRAM (dynamic semiconductor memory). Conventional DR
In an AM cell array, elements are separated by a field insulating film between rows in the array, and elements are separated by a field insulating film for each of a plurality of semiconductor elements in a column direction in the array.

Here, a conventional method of forming an element isolation structure in a DRAM cell array will be described in detail with reference to the drawings. FIGS. 6A to 6C show plan patterns on a semiconductor substrate on which a DRAM cell array is formed, and FIGS. 7A to 7C and FIGS. 8A to 8C.
FIGS. 9A to 9C show cross-sectional structures of the substrate along the line XX in FIGS. 6A to 6C.

First, as shown in FIGS. 6A and 7A, N-type semiconductor substrate 1 is doped with boron.
The P-type well layer 2 is formed to a depth of about 4 μm by thermal diffusion. Thereafter, a first oxide film 3 is deposited on the P-type well layer 2, and subsequently, a first silicon nitride film 4 is deposited.

After that, a resist film is applied and patterned to form an element isolation pattern resist 5 composed of a number of strip-shaped island-shaped patterns. Next, the first silicon nitride film 4 is anisotropically etched by RIE (reactive ion etching) using the element isolation pattern resist 5 as a mask.
Is removed. As a result, the first silicon nitride film 4 has an element isolation pattern similar to that of the element isolation pattern resist 5.

Next, as shown in FIGS. 6 (b) and 7 (b), a field oxide film 6 is formed in a portion not covered with the first silicon nitride film 4 by using a thermal oxidation technique. Thereafter, the first is performed by CDE (chemical dry etching).
Is etched to expose the first oxide film 3.

Next, as shown in FIG. 7 (c), after depositing a second silicon nitride film 7 on the entire surface, a resist film is applied and patterned to form a trench opening pattern resist 8. . FIG. 6C shows the positional relationship between the trench opening pattern resist 8 and the element isolation pattern 4 a formed by the silicon nitride film 4.

Thereafter, anisotropic etching is performed by RIE in the order of the second silicon nitride film 7, the first oxide film 3, and the P-type well layer 2 to form a trench (groove) 8a.
At this time, the depth of the trench 8a is set to 4 μm or more so as to reach the N-type semiconductor substrate 1 slightly.

Next, the trench opening pattern resist 8 is removed, and a second oxide film 9 is deposited on the entire surface as shown in FIG. The second oxide film 9 remains on the inner side wall. In other words, the second oxide film 9 is formed in a shape that leaves the trench sidewalls.

Similarly, the first N-type polysilicon film 1
By performing anisotropic etching by RIE after depositing 0 on the entire surface, the first N-type polysilicon electrode 10 remains on the side wall in the trench.

At this time, it is important to take care that the total thickness of the second oxide film 9 and the first N-type polysilicon electrode 10 does not completely fill the trench. And the processed first N-type polysilicon electrode 1
Etching is performed so that 0 is lower than the interface between the P-type well layer 2 and the first oxide film 3 (for example, about 300 nm).

Next, as shown in FIG. 8B, the first N
Forming a capacitor gate insulating film 11 on the type polysilicon electrode 10 and the N type semiconductor substrate 1 by a thermal oxidation technique,
Further, a second N-type polysilicon electrode 12 is deposited.

Next, as shown in FIG. 8C, after the second N-type polysilicon electrode 12 is etched back by CDE so as to be embedded in the trench, a sidewall etching pattern resist 13 is formed. Then, using the side wall etching pattern resist 13 as a mask, a part of the second oxide film 9 is etched with an NH ₄ F etching solution.

Next, the side wall etching pattern resist 1
3 is removed, and a third N-type polysilicon electrode 14 is deposited so as to be in contact with the P-type well layer 2 as shown in FIG.

Next, a third oxide film 15 is formed on the third N-type polysilicon electrode 14 by a thermal oxidation technique. Subsequently, the second silicon nitride film 7 is removed by CDE, and the first oxide film 3 and the third oxide film 15 are removed by an NH ₄ F etching solution.

Next, as shown in FIG. 9B, a gate insulating film 16 of the MOS transistor is formed by a thermal oxidation technique. Further, after depositing a fourth N-type polysilicon film 17, a transistor electrode pattern resist 18 is formed.

Then, the fourth N-type polysilicon film 17 is anisotropically etched by RIE to form a fourth N-type polysilicon electrode 17, and arsenic is ion-implanted by an ion implantation technique. Here, the arsenic ion implantation region is indicated by 19 in FIG. 9B.

Next, by removing the transistor electrode pattern resist 18 and activating the ion-implanted arsenic by thermal diffusion, as shown in FIG.
The source / drain region 20 of the MOS transistor is formed.

In the structure shown in FIG. 9C formed by the above-described manufacturing method, the first N-type polysilicon electrode 10 is a plate electrode and the second N-type polysilicon electrode 12 has a capacitor element having a storage electrode.

The storage electrode 12 of this capacitor element
Is the source / drain region 20 of the NMOS transistor
Is electrically connected to one of them. Further, the plate electrode 10 of the capacitor element is connected to the N-type semiconductor substrate 1.
And the plate electrodes 10 of two or more capacitor elements have a common potential.

A DRAM cell having a one-transistor / one-capacitor structure is formed by each one of the capacitor element and the NMOS transistor. By the way, D
2. Description of the Related Art Integrated circuits represented by RAMs and the like have been increasingly integrated. For this reason, application of a resist film by lithography, which is essential for fine processing, has become a problem. That is, the resist film cannot be processed as designed. This is particularly serious when the resist film is processed into an island shape.

That is, as shown in FIG. 6A, an element isolation pattern resist 5 for determining the shape of the element isolation pattern is formed.
Is very important, but even if it is planned to form an ideal rectangular pattern, due to the limitation of the resolution in the current lithography technology, it is actually a pattern resist 5 ′ shown in FIG. In this case, the end of the resist film in the pattern length direction becomes round.

When an element isolation pattern is formed based on the actual pattern resist 5 ', an element formation region surrounded by the element isolation region formed based on the element isolation pattern as shown in FIG. In addition, the channel width W0 on the drain region side of the channel region below the gate electrode 17 of the NMOS transistor adjacent to the trench capacitor region 21 is different from the channel width W1 on the source region side.

In other words, with respect to the channel width W0 corresponding to the center portion (sharply formed pattern portion) of the actual pattern resist 5 'in the pattern length direction, the front end portion in the pattern length direction (rounded pattern). The channel width W1 corresponding to (portion) becomes narrow.

This has a problem that the electrical characteristics of the transistor are greatly affected, and the characteristics as designed cannot be obtained. Further, the actual pattern resist 5 '
Among them, the degree of the phenomenon that the leading end in the pattern length direction is rounded is not always constant, so that there is also a problem that the electrical characteristics are different for each transistor.

[0026]

As described above, conventionally, a plurality of element units are arranged in a column direction of an array of a DRAM cell having a one-transistor / one-capacitor structure including a trench capacitor region and an adjacent MOS transistor. When forming an element isolation structure, it is necessary to divide and form a pattern resist for forming a field insulating film in units of a plurality of elements in a column direction, and the pattern length of the pattern resist is limited due to the limitation of resolution in current lithography technology. The tip of the MOS transistor in the direction becomes rounded, and the channel width of the channel region below the gate electrode of the MOS transistor on the drain region side and the channel width on the source region side are different, so that the electrical characteristics of the MOS transistor can be obtained as designed. If the electrical characteristics are different for each MOS transistor There was a cormorant problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. A plurality of semiconductor elements are arranged in a matrix and a plurality of elements are arranged in a column direction in an element array in which rows are separated by a field insulating film. When forming an element isolation structure in units, a semiconductor device capable of continuously forming a pattern resist for forming a field insulating film without dividing it in a column direction and obtaining electrical characteristics of an element as designed. It is an object of the present invention to provide a manufacturing method thereof.

[0028]

According to the present invention, there is provided a semiconductor device comprising:
An element array in which semiconductor elements are arranged in rows and columns is provided between rows in the element array, and a space between the rows of the element array is supplied.
It is located between a field insulating film of a straight pattern to be gaseously separated and an element block area in units of a plurality of element formation areas in the column direction in the element array .
At least one trench and said mutual element block.
Side of the trench except for a part of the region in contact with one of the
It is provided on the wall and electrically separates the columns of the element block region.
An insulating film to be separated;
In the region where the edge film has been removed, the one element block region
And polysilicon electrically connected only to the

[0029]

The element block region is electrically isolated by surrounding the element block region with a field insulating film and a trench whose inner wall is covered with an insulating film. Accordingly, for example, in an array of DRAM cells having a one-transistor / one-capacitor structure including a trench capacitor region and a MOS transistor adjacent thereto, when forming an element isolation structure in a unit of a plurality of cells in a column direction in the array, a field isolation is required. It can be continuously formed without dividing the pattern resist film for forming the column direction, 且
The element block in the column direction is
The isolation region can be electrically separated. Therefore, the drain region side and the source region side of the channel region below the gate electrode region of the MOS transistor can be formed to have the same channel width, and the electrical characteristics of the MOS transistor can be obtained as designed, and for each MOS transistor A semiconductor device with no different electrical characteristics can be realized.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming an element isolation structure in a column direction in a DRAM cell array according to an embodiment of the present invention will be described in detail with reference to the drawings.
1A to 1C show plan patterns on a semiconductor substrate on which a DRAM cell array is formed.
1A shows a cross section along the line XX in FIG. 1A, FIG. 2B shows a cross section along the line YY in FIG.
FIG. 2C shows a cross section taken along line YY in FIG. 1B, and FIGS. 2D, 3A to 3C, and 4.
(A) to (c) show cross sections along line XX in FIG. 1 (c).

First, as shown in FIGS. 1A and 2A, N-type semiconductor substrate 1 is doped with boron.
The P-type well layer 2 is formed to a depth of about 4 μm by thermal diffusion. Thereafter, a first oxide film 3 is deposited on the P-type well layer 2 to a thickness of 50 nm, and then a first silicon nitride film 4 is deposited to a thickness of 100 nm.

Thereafter, as shown in FIGS. 1B and 2B, a resist film is applied and patterned to form an element isolation pattern resist 5 composed of a striped straight pattern. In this case, the width of the pattern resist 5 is 0.8 μm, and the width of the space between the patterns is 0.8 μm.

Next, the first silicon nitride film 4 is anisotropically etched by RIE using the element isolation pattern resist 5 as a mask, and thereafter, the element isolation pattern resist 5 is removed. As a result, the first silicon nitride film 4 has an element isolation pattern similar to that of the element isolation pattern resist 5.

Next, as shown in FIG. 2C, a field oxide film 6a is formed in a portion not covered with the first silicon nitride film 4 by using a thermal oxidation technique, and thereafter, a field oxide film 6a is formed by CDE. The first silicon nitride film 4 is etched to expose the first oxide film 3.

Next, as shown in FIG. 2D, a 100 nm thick second silicon nitride film 7 is deposited on the entire surface, and then a resist film is applied and patterned to form a trench opening pattern resist 8. .

FIG. 1C shows the positional relationship between the trench opening pattern resist 8 and the element isolation pattern 4 a formed by the silicon nitride film 4. In this case, the trench opening pattern resist 8 is, for example, rectangular, and one side of the trench opening pattern is, for example, 0.8 μm.
Then, two sides of the trench opening pattern resist 8 parallel to the column direction of the trench opening pattern are located on the field oxide film 6a.

Thereafter, anisotropic etching is performed by RIE in the order of the second silicon nitride film 7, the first oxide film 3, and the P-type well layer 2 to form a trench 8a. At this time, the depth of the trench 8a is set to, for example, 4.4 μm so as to reach the N-type semiconductor substrate 1 slightly.

Next, the trench opening pattern resist 8 is removed by an ashing method, and as shown in FIG.
After depositing the second oxide film 9 on the entire surface to a thickness of 50 nm, anisotropic etching is performed by RIE to form the second oxide film 9 in a shape left on the side wall in the trench.

Similarly, the first N-type polysilicon film 1
After depositing 200 nm on the entire surface of the trench, anisotropic etching is performed by RIE, thereby forming the first N-type polysilicon electrode 10 in a shape left on the side wall in the trench.

At this time, it is important to take care that the total thickness of the second oxide film 9 and the first N-type polysilicon electrode 10 does not completely fill the trench. And the processed first N-type polysilicon electrode 1
Etching is performed so that 0 is lower than the interface between the P-type well layer 2 and the first oxide film 3 (for example, about 300 nm).

Next, as shown in FIG. 3B, the first N
A gate insulating film 11 of 10 nm is formed on the polysilicon electrode 10 and the N-type semiconductor substrate 1 by a thermal oxidation technique.
Then, the second N-type polysilicon electrode 12 is
Deposit 00 nm.

Next, as shown in FIG. 3C, after the second N-type polysilicon electrode 12 is etched back by CDE so as to be embedded in the trench, a sidewall etching pattern resist 13 is formed. Then, using the side wall etching pattern resist 13 as a mask, a part of the second N-type polysilicon electrode 12 and a part of the second oxide film 9 are etched with an NH ₄ F etching solution.

Next, the side wall etching pattern resist 1
3 is removed, and a third N-type polysilicon electrode 14 is deposited to a thickness of 600 nm so as to be in contact with the P-type well layer 2 as shown in FIG.

Next, a third oxide film 15 having a thickness of 30 nm is formed on the third N-type polysilicon electrode 14 by a thermal oxidation technique. Subsequently, the second silicon nitride film 7 is removed by CDE, and the first oxide film 3 and the third oxide film 15 are removed by an NH ₄ F etching solution.

Next, as shown in FIG. 4B, the gate insulating film 16 of the MOS transistor is
nm. Further, a fourth N-type polysilicon film 17 is formed.
Is deposited to a thickness of 300 nm, a transistor electrode pattern resist 18 is formed.

Then, the fourth N-type polysilicon film 17 is anisotropically etched by RIE to form a fourth N-type polysilicon electrode 17, and arsenic is ion-implanted by an ion implantation technique. Here, the arsenic ion implantation region is indicated by 19 in FIG.

Next, the transistor electrode pattern resist 18 is peeled off, and the ion-implanted arsenic is activated by thermal diffusion, as shown in FIG.
The source / drain region 20 of the MOS transistor is formed.

That is, the manufacturing method of the above embodiment uses a lithography technique for forming an element isolation pattern resist 5 consisting of a striped straight pattern on a semiconductor substrate, and forms a striped straight pattern on the surface layer of the semiconductor substrate. Forming a field oxide film 6a composed of a pattern, opening a plurality of trenches 8a at intervals in the length direction of the element formation region between the field oxide films 6a, The method includes a step of forming an insulating film 9 on a side wall and a step of forming a plurality of semiconductor elements in each of the element forming regions whose length direction is divided by the trench.

The step of forming the semiconductor element includes the step of forming a capacitor in the trench and the step of forming a charge storage node (storage electrode 12) of the capacitor.
Forming a MOS transistor so that one of the source / drain regions 20 continues.

In the structure shown in FIG. 4C formed by the manufacturing method described above, the first N-type polysilicon electrode 10 is a plate electrode, and the second N-type polysilicon electrode 12 is a storage electrode. Trench region 21 having the formed capacitor element in the trench is formed. The storage electrode 12 of the capacitor element is electrically connected to one of the source / drain regions 20 of the NMOS transistor. Further, the plate electrode 10 of the capacitor element is electrically connected to the N-type semiconductor substrate 1, and the plate electrodes of two or more capacitor elements have a common potential.

A DRAM cell having a one-transistor / one-capacitor structure is formed by each one of the capacitor element and the NMOS transistor. In addition, in the structure of the above embodiment, two-bit DRAM cells (element block regions) adjacent in the cell column direction are used.
Each element block region is electrically isolated by having a structure surrounded by a field insulating film 6a formed in parallel with the cell column direction and a trench 8a whose inner wall is covered with an insulating film 9.

Since the region 2a of the P-type well layer 2 existing between the element block regions is in an electrically floating state, it is thermally diffused by arsenic ion-implanted into the surface layer of this region. There is no problem even if the impurity region 20a is formed.

In order to prevent the impurity region 20a from being formed, a lithography step for masking the region so that ions are not implanted may be added. The structure of the above embodiment differs from the structure of the conventional example in that no field oxide film exists between adjacent element block regions in the cell column direction.

That is, according to the semiconductor device of this embodiment, a plurality of cell units are arranged in the column direction in the array of the DRAM cell having the one-transistor / one-capacitor structure including the trench capacitor region 21 and the MOS transistor adjacent thereto. When the element isolation structure is formed, the pattern resist 5 for forming the field insulating film can be formed continuously straight without being divided in the column direction.

Therefore, even with the resolution of the current lithography technique, the problem that the portion corresponding to the space between the element block regions of the pattern resist 5 becomes round does not occur at all. Therefore, the pattern is formed based on the element separation pattern. As shown in FIG. 5, in the element formation region surrounded by the element isolation region, the drain region side and the source region side of the channel region below the gate electrode 17 of the MOS transistor adjacent to the trench capacitor region 21 have the same channel width. It can be formed to be W0. That is, the electrical characteristics of the MOS transistors can be obtained as designed, and the electrical characteristics do not differ for each MOS transistor.

[0056]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, a plurality of semiconductor elements are arranged in rows and columns in a column direction in an element array in which rows are separated by a field insulating film. When forming an element isolation structure in units of individual elements, a pattern resist for forming a field insulating film can be formed continuously without being divided in the column direction, and the electrical characteristics of the element can be obtained as designed. .

[Brief description of the drawings]

FIG. 1 shows a DRAM according to one embodiment of a semiconductor device of the present invention.
FIG. 8 is a top view showing a planar pattern on a semiconductor substrate in a part of the manufacturing process.

FIG. 2 is a sectional view showing a sectional structure of the semiconductor substrate in the manufacturing process of FIG. 1;

FIG. 3 is a cross-sectional view showing a cross-sectional structure of the semiconductor substrate in a manufacturing process following the manufacturing process of FIG. 2;

FIG. 4 is a cross-sectional view showing a cross-sectional structure of the semiconductor substrate in a manufacturing process following the manufacturing process of FIG. 3;

FIG. 5 shows a channel width and a source on a drain region side below a gate electrode region of a transistor adjacent to a trench capacitor region in an element formation region surrounded by an element isolation region formed based on the element isolation pattern resist in FIG. FIG. 4 is a top view showing a state where the channel width on the region side is equal.

FIG. 6 is a top view showing a planar pattern on a semiconductor substrate in a part of a conventional DRAM manufacturing process.

FIG. 7 is a sectional view showing a sectional structure of the semiconductor substrate in the manufacturing process of FIG. 6;

FIG. 8 is a cross-sectional view showing a cross-sectional structure of the semiconductor substrate in a manufacturing process following the manufacturing process of FIG. 7;

FIG. 9 is a cross-sectional view showing a cross-sectional structure of the semiconductor substrate in a manufacturing process following the manufacturing process of FIG. 8;

FIG. 10 is a top view showing an example of the shape of the pattern resist actually formed due to the limit of resolution in the lithography technique when forming the element isolation pattern resist shown in FIG. 6;

11 shows a channel width and a source region on a drain region side below a gate electrode region of a transistor adjacent to a trench capacitor region in an element formation region surrounded by an element isolation region formed based on the element isolation pattern resist of FIG. FIG. 6 is a top view showing a state where the channel width on the side is different.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N type semiconductor substrate, 2 ... P type well layer, 3 ... 1st oxide film, 4 ... 1st silicon nitride film, 5 ... Element isolation pattern resist film, 5 '... Element isolation pattern actually formed Resist, 6a: field oxide film, 7: second silicon nitride film, 8: trench opening pattern resist film, 8
a: trench, 9: second oxide film, 10: first N-type polysilicon electrode, 11: capacitor gate insulating film, 12
... second N-type polysilicon electrode, 13 ... sidewall etching pattern resist, 14 ... third N-type polysilicon electrode, 15 ... third oxide film, 16 ... transistor gate insulating film, 17 ... fourth N-type Polysilicon electrode, 18: transistor electrode pattern resist, 19: arsenic ion implanted region, 20: source / drain region, 21: trench capacitor region.

Claims (4)

(57) [Claims] 1. A formed on a semiconductor substrate, an element array in which a semiconductor element is arranged in a matrix, is provided between the rows in the array, the row of the element array
A field insulating film of a straight pattern to electrically isolate between, even low <br/> without positioned therebetween element block regions which a plurality of element forming region as a unit in the column direction in the element array 1 Trenches and part of a region that is in contact with one of the mutual element block regions
Provided on the side walls of the trench except for the element block region.
An insulating film that electrically separates the columns of the region, and the insulating film that is embedded in the trench and that is removed
Area, and is electrically connected only to the one element block area.
A semiconductor device comprising: continuous polysilicon . 2. The semiconductor device according to claim 1, wherein the semiconductor element is a dynamic memory cell including one MOS transistor and one capacitor, wherein the capacitor is formed in the trench .
And the insulating film is a gate insulating film of the MOS transistor.
A semiconductor device characterized by being thicker than a film . 3. A field oxide film having a striped straight pattern is formed on a surface layer portion of the semiconductor substrate by using a lithography technique for forming an element separation pattern resist having a striped straight pattern on a semiconductor substrate. Forming a plurality of trenches at intervals in the length direction of the element forming region between the field oxide films; and forming a plurality of trenches on sidewalls in the trenches by the trenches.
A step of forming an insulating film for electrically isolating each of the divided element forming regions, and an element forming region whose length direction is divided by the trench
A part of the insulating film in contact with one of the
A step of etching and removing the insulating film from one of the element forming regions;
The trench so that it touches in a region where a part of the trench is removed.
A method of manufacturing a semiconductor device, comprising: a step of filling the inside with polysilicon ; and a step of forming a plurality of semiconductor elements in each of element forming regions whose length direction is divided by the trench. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the semiconductor element includes the step of forming a capacitor in the trench and the step of connecting a source or a drain to a charge storage node of the capacitor. Forming a MOS transistor on the substrate , wherein the step of forming the insulating film includes the step of forming the insulating film from a gate insulating film of the MOS transistor.
A method for manufacturing a semiconductor device, comprising: forming a semiconductor device;