JPH06338595A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form pattern resist continuously without dividing the resist in the direction of a line by providing one trench, which is located at a position between element block regions with a plurality of element forming regions as units in the direction of the line in an element array, and wherein the inner wall is covered with an insulating film. CONSTITUTION:A P-type well layer 2 is formed on a substrate 1. A first oxide film 3 and a silicon nitride film 4 are deposited on the P-type well layer 2. Thereafter, an element isolating pattern resist 5 is formed. With the resist as a mask, the first silicon nitride film 4 is etched. The element isolating pattern resist 5 is removed, and a field oxide film 6a is formed at a part, which is not covered with the first silicon nitride film 4, and the first oxide film 3 is exposed. Then, a second silicon nitride film 7 is deposited. Thereafter, a trench opening pattern resist 8 is formed. Two sides of the trench opening pattern resist 8, which are in parallel with the direction of the line of the trench opening patterns, are located on the field oxide film 6a and can be continuously formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, in a semiconductor device having an element array in which semiconductor elements are arranged in rows and columns, a plurality of semiconductor elements are arranged in a column direction in the element array. And a method for forming the same.

[0002]

2. Description of the Related Art As a semiconductor device having an element array in which semiconductor elements are arranged in a matrix, for example, a DRAM (dynamic type semiconductor memory) can be cited. Conventional DR
In the AM cell array, a field insulating film is used to isolate elements between rows in the array, and a plurality of semiconductor elements are isolated from each other in the column direction in the array by a field insulating film.

Here, a conventional method of forming an element isolation structure in a DRAM cell array will be described in detail with reference to the drawings. FIGS. 6A to 6C show plan patterns on a semiconductor substrate in which a DRAM cell array is formed, and FIGS. 7A to 7C and 8A to 8C.
9A to 9C show sectional structures of the substrate taken along line XX in FIGS. 6A to 6C.

First, as shown in FIGS. 6A and 7A, the N-type semiconductor substrate 1 is doped with boron,
The P-type well layer 2 is formed to a depth of about 4 μm by thermal diffusion. After that, the first oxide film 3 is deposited on the P-type well layer 2, and subsequently the first silicon nitride film 4 is deposited.

Thereafter, a resist film is applied and patterned to form an element isolation pattern resist 5 having a large number of strip-shaped island patterns. Next, using the element isolation pattern resist 5 as a mask, anisotropic etching of the first silicon nitride film 4 is performed by the RIE (reactive ion etching) technique.
To remove. As a result, the first silicon nitride film 4 becomes an element isolation pattern similar to the element isolation pattern resist 5.

Next, as shown in FIGS. 6 (b) and 7 (b), a field oxide film 6 is formed on a portion not covered with the first silicon nitride film 4 by using a thermal oxidation technique, After this, the first by CDE (chemical dry etching)
The silicon nitride film 4 is etched to expose the first oxide film 3.

Next, as shown in FIG. 7C, after depositing a second silicon nitride film 7 on the entire surface, a resist film is applied and patterned to form a trench opening pattern resist 8. . The positional relationship between the trench opening pattern resist 8 and the element isolation pattern 4a formed by the silicon nitride film 4 is shown in FIG. 6 (c).

Thereafter, by RIE, the second silicon nitride film 7, the first oxide film 3, and the P-type well layer 2 are anisotropically etched in this order to form a trench 8a.
At this time, the depth of the trench 8 a is set to 4 μm or more so that the N-type semiconductor substrate 1 is slightly reached.

Next, the trench opening pattern resist 8 is removed, and as shown in FIG. 8A, a second oxide film 9 is deposited on the entire surface, and then anisotropic etching is performed by RIE to form the trench. The second oxide film 9 remains on the inner sidewall. In other words, the second oxide film 9 is formed in the shape where the trench sidewall remains.

Similarly, the first N-type polysilicon film 1 is formed.
After 0 is deposited on the entire surface, anisotropic etching is performed by RIE to leave the first N-type polysilicon electrode 10 on the sidewall in the trench.

At this time, it is important to note that the trench is not completely filled with the total film thickness of the second oxide film 9 and the first N-type polysilicon electrode 10. And the processed first N-type polysilicon electrode 1
Etching is performed so that 0 is below the interface between the P-type well layer 2 and the first oxide film 3 (for example, about 300 nm).

Next, as shown in FIG. 8B, the first N
A capacitor gate insulating film 11 is formed on the n-type polysilicon electrode 10 and the N-type semiconductor substrate 1 by a thermal oxidation technique,
Further, the second N-type polysilicon electrode 12 is deposited.

Next, as shown in FIG. 8C, after etching back the second N-type polysilicon electrode 12 by CDE so as to fill the trench, a sidewall etching pattern resist 13 is formed. Then, using the sidewall etching pattern resist 13 as a mask, a part of the second oxide film 9 is etched with an NH ₄ F etching solution.

Next, the sidewall etching pattern resist 1
3 is removed, and as shown in FIG. 9A, a third N-type polysilicon electrode 14 is deposited so as to be in contact with the P-type well layer 2 and then etched back by CDE.

Next, a third oxide film 15 is formed on the third N-type polysilicon electrode 14 by a thermal oxidation technique. Then, the second silicon nitride film 7 is removed by CDE, and the first oxide film 3 and the third oxide film 15 are removed by NH ₄ F etching solution.

Next, as shown in FIG. 9B, the gate insulating film 16 of the MOS transistor is formed by the thermal oxidation technique. Furthermore, after depositing the fourth N-type polysilicon film 17, a transistor electrode pattern resist 18 is formed.

Then, the fourth N-type polysilicon film 17 is anisotropically etched by RIE to form a fourth N-type polysilicon electrode 17, and arsenic is ion-implanted by an ion implantation technique. Here, the arsenic ion implantation region is shown by 19 in FIG.

Next, the transistor electrode pattern resist 18 is peeled off, and the ion-implanted arsenic is activated by thermal diffusion, so that N as shown in FIG.
The source / drain regions 20 of the MOS transistor are formed.

In the structure shown in FIG. 9C formed by the manufacturing method as described above, the first N-type polysilicon electrode 10 is a plate electrode and the second N-type polysilicon electrode is in the trench. The capacitor element 12 has a storage electrode.

The storage electrode 12 of this capacitor element
Is the source / drain region 20 of the NMOS transistor
Is electrically connected to one of the two. Further, the plate electrode 10 of the capacitor element is the N-type semiconductor substrate 1
And the plate electrodes 10 of two or more capacitor elements have a common potential.

A DRAM cell having a one-transistor / one-capacitor structure is formed by each of the capacitor element and the NMOS transistor. By the way, D
Highly integrated circuits such as RAMs are becoming more highly integrated. Therefore, the coating process of the resist film by the lithography technique, which is indispensable for fine processing, has become a problem. That is, the resist film cannot be processed according to the design drawing. This is particularly serious when the resist film is processed into an island shape.

That is, as shown in FIG. 6A, the element isolation pattern resist 5 which determines the shape of the element isolation pattern.
Is very important, but even if it is planned to form an ideal rectangular pattern, due to the limit of resolution in the current lithography technology, in reality, the pattern resist 5'shown in FIG. Moreover, the tip of the resist film in the pattern length direction becomes rounded.

When an element isolation pattern is formed on the basis of the actual pattern resist 5 ', in the element formation region surrounded by the element isolation region formed on the basis of the element isolation pattern, as shown in FIG. In addition, the channel width W0 on the drain region side of the channel region under the gate electrode 17 of the NMOS transistor adjacent to the trench capacitor region 21 and the channel width W1 on the source region side are different from each other.

That is, with respect to the channel width W0 corresponding to the central portion (pattern portion formed sharply) in the pattern length direction of the actual pattern resist 5 ', the tip portion in the pattern length direction (rounded pattern). That is, the channel width W1 corresponding to the portion) becomes narrow.

This has a problem that the electrical characteristics of the transistor are greatly affected and the characteristics as designed cannot be obtained. Furthermore, the actual pattern resist 5 '
Among them, since the degree of the phenomenon that the tip end portion in the pattern length direction is rounded is not always constant, there is also a problem that the electrical characteristics differ from transistor to transistor.

[0026]

As described above, conventionally, a plurality of element units are arranged in the column direction of the array of the DRAM cell array having the one-transistor / one-capacitor structure, which includes the trench capacitor region and the MOS transistor adjacent to the trench capacitor region. When forming the element isolation structure, it is necessary to divide and form the pattern resist for forming the field insulating film in units of a plurality of elements in the column direction, and the pattern length of the pattern resist is limited due to the limit of resolution in the current lithography technology. A phenomenon that the direction tip is rounded occurs, the channel width on the drain region side and the channel width on the source region side of the channel region under the gate electrode of the MOS transistor are different, and the electrical characteristics of the MOS transistor are obtained as designed. If it becomes impossible to change the electrical characteristics of each MOS transistor, There was a cormorant problem.

The present invention has been made to solve the above problems, and a plurality of elements are arranged in a column direction in an element array in which semiconductor elements are arranged in rows and columns and rows are separated by a field insulating film. When a device isolation structure is formed in units, a pattern resist for forming a field insulating film can be continuously formed without dividing in a column direction, and a semiconductor device capable of obtaining electric characteristics of a device as designed It is an object to provide a manufacturing method thereof.

[0028]

The semiconductor device of the present invention comprises:
An element array in which semiconductor elements are arranged in a matrix, a field insulating film for element isolation provided between rows in the element array, and a plurality of element formation regions in the column direction in the element array as a unit At least one trench, which is located between the element block regions and whose inner wall is covered with an insulating film, is provided.

[0029]

The element block region is surrounded by the field insulating film and the trench whose inner wall is covered with the insulating film, so that each element block region is electrically isolated. Therefore, for example, in an array of DRAM cells having a one-transistor / one-capacitor structure including a trench capacitor region and a MOS transistor adjacent to the trench capacitor region, when forming an element isolation structure in a unit of a plurality of cells in a column direction in the array, field isolation is performed. The pattern resist for film formation can be continuously formed without dividing in the column direction.
The drain region side and the source region side of the channel region under the gate electrode region of the OS transistor can be formed to have the same channel width, and the electrical characteristics of the MOS transistor can be obtained as designed, and the electrical characteristics of each MOS transistor can be obtained. It is possible to realize a semiconductor device that does not differ.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming an element isolation structure in a column direction in a cell array of a DRAM according to an embodiment of a semiconductor device of the present invention will be described in detail below with reference to the drawings.
1A to 1C show plan patterns on a semiconductor substrate on which a DRAM cell array is formed.
1A shows a cross section taken along line XX in FIG. 1A, and FIG. 2B shows a cross section taken along line YY in FIG.
2C shows a cross section taken along line Y-Y in FIG. 1B, and FIG. 2D, FIGS. 3A to 3C, and FIG.
(A) to (c) show cross sections taken along line XX in FIG. 1 (c).

First, as shown in FIGS. 1A and 2A, the N-type semiconductor substrate 1 is doped with boron,
The P-type well layer 2 is formed to a depth of about 4 μm by thermal diffusion. After that, the first oxide film 3 is deposited on the P-type well layer 2 in a thickness of 50 nm, and then the first silicon nitride film 4 is deposited in a thickness of 100 nm.

Thereafter, as shown in FIGS. 1B and 2B, a resist film is applied and patterned to form an element isolation pattern resist 5 having a striped straight pattern. In this case, the width of the pattern resist 5 is 0.8 μm, and the width of the space between the patterns is 0.8 μm.

Next, the first silicon nitride film 4 is anisotropically etched by RIE using the element isolation pattern resist 5 as a mask, and then the element isolation pattern resist 5 is removed. As a result, the first silicon nitride film 4 becomes an element isolation pattern similar to the element isolation pattern resist 5.

Next, as shown in FIG. 2C, a field oxide film 6a is formed on a portion not covered with the first silicon nitride film 4 by using a thermal oxidation technique, and thereafter, a field oxide film 6a is formed by CDE. The first silicon nitride film 4 is etched to expose the first oxide film 3.

Next, as shown in FIG. 2D, a second silicon nitride film 7 is deposited on the entire surface to a thickness of 100 nm, and then a resist film is applied and patterned to form a trench opening pattern resist 8. .

The positional relationship between the trench opening pattern resist 8 and the element isolation pattern 4a formed by the silicon nitride film 4 is as shown in FIG. 1 (c). In this case, the trench opening pattern resist 8 is, for example, a quadrangle, and one side of the trench opening pattern is, for example, 0.8 μm.
Then, two sides of the trench opening pattern resist 8 parallel to the column direction of the trench opening pattern are located on the field oxide film 6a.

After that, the second silicon nitride film 7, the first oxide film 3 and the P-type well layer 2 are anisotropically etched in this order by RIE to form a trench 8a. At this time, the depth of the trench 8a is set to, for example, 4.4 μm so that the N-type semiconductor substrate 1 is slightly reached.

Next, the trench opening pattern resist 8 is removed by an ashing method, and as shown in FIG.
After the second oxide film 9 is deposited on the entire surface to a thickness of 50 nm, anisotropic etching is performed by RIE to form the second oxide film 9 in a shape in which the sidewall is left inside the trench.

Similarly, the first N-type polysilicon film 1 is formed.
0 is deposited over the entire surface to a thickness of 200 nm, and anisotropic etching is performed by RIE to form the first N-type polysilicon electrode 10 in a shape in which it is left on the sidewall in the trench.

At this time, it is important to note that the trench is not completely filled with the total film thickness of the second oxide film 9 and the first N-type polysilicon electrode 10. And the processed first N-type polysilicon electrode 1
Etching is performed so that 0 is below the interface between the P-type well layer 2 and the first oxide film 3 (for example, about 300 nm).

Next, as shown in FIG. 3B, the first N
A capacitor gate insulating film 11 having a thickness of 10 nm is formed on the N-type polysilicon electrode 10 and the N-type semiconductor substrate 1 by a thermal oxidation technique.
Then, the second N-type polysilicon electrode 12 is further formed by 4
00 nm is deposited.

Next, as shown in FIG. 3C, after etching back the second N-type polysilicon electrode 12 by CDE so as to fill the trench, a sidewall etching pattern resist 13 is formed. Then, using the sidewall etching pattern resist 13 as a mask, a part of the second N-type polysilicon electrode 12 and a part of the second oxide film 9 are etched with an NH ₄ F etching solution.

Next, the sidewall etching pattern resist 1
3 is removed, and as shown in FIG. 4A, a third N-type polysilicon electrode 14 is deposited to a thickness of 600 nm so as to be in contact with the P-type well layer 2, and then etched back by CDE.

Next, a third oxide film 15 of 30 nm is formed on the third N-type polysilicon electrode 14 by a thermal oxidation technique. Then, the second silicon nitride film 7 is removed by CDE, and the first oxide film 3 and the third oxide film 15 are removed by NH ₄ F etching solution.

Next, as shown in FIG. 4B, the gate insulating film 16 of the MOS transistor is formed to 20 by the thermal oxidation technique.
nm to form. Further, the fourth N-type polysilicon film 17
Is deposited to a thickness of 300 nm, and then a transistor electrode pattern resist 18 is formed.

Then, the fourth N-type polysilicon film 17 is anisotropically etched by RIE to form a fourth N-type polysilicon electrode 17, and arsenic is ion-implanted by an ion implantation technique. Here, the arsenic ion implantation region is shown by 19 in FIG.

Next, the transistor electrode pattern resist 18 is peeled off, and the ion-implanted arsenic is activated by thermal diffusion, so that N as shown in FIG.
The source / drain regions 20 of the MOS transistor are formed.

That is, in the manufacturing method of the above-described embodiment, the stripe-shaped straight pattern is formed on the surface layer portion of the semiconductor substrate by using the lithography technique for forming the element separating pattern resist 5 having the stripe-shaped straight pattern on the semiconductor substrate. A step of forming a field oxide film 6a having a pattern; a step of forming a plurality of trenches 8a at intervals in the lengthwise direction of the element forming region between the field oxide films 6a; The method includes a step of forming the insulating film 9 on the side wall and a step of forming a plurality of semiconductor elements in each of the element forming regions whose length direction is divided by the trench.

The step of forming the semiconductor element includes the step of forming a capacitor in the trench and the charge storage node (storage electrode 12) of the capacitor.
And a step of forming a MOS transistor so that one of the source / drain regions 20 is continuous.

In the structure shown in FIG. 4C formed by the manufacturing method described above, the first N-type polysilicon electrode 10 is a plate electrode and the second N-type polysilicon electrode 12 is a storage electrode. A trench capacitor region 21 having the above-described capacitor element in the trench is formed. The storage electrode 12 of the capacitor element is electrically connected to one of the source / drain regions 20 of the NMOS transistor. The plate electrode 10 of the capacitor element is electrically connected to the N-type semiconductor substrate 1, and the plate electrodes of two or more capacitor elements have a common potential.

A DRAM cell having a one-transistor / one-capacitor structure is formed by each of the above-mentioned capacitor element and one NMOS transistor. Moreover, in the structure of the above-described embodiment, the DRAM cells (element block regions) for 2 bits which are adjacent to each other in the column direction of the cells are
Each element block region is electrically isolated by having a structure in which the field insulating film 6a formed parallel to the column direction of the cell and the trench 8a whose inner wall is covered with the insulating film 9 are surrounded.

Since the region 2a of the P-type well layer 2 existing between the element block regions is in an electrically floating state, the thermal diffusion of arsenic ion-implanted into the surface layer of this region causes thermal diffusion. Even if the impurity region 20a is formed, there is no problem.

In order to prevent the impurity region 20a from being formed, a lithography process for masking the region so that ions may not be implanted may be added. The structure of the above embodiment is different from the structure of the conventional example in that there is no field oxide film between the element block regions adjacent to each other in the cell column direction.

That is, according to the semiconductor device of the present embodiment, a plurality of cell units are arranged in the column direction in the array of the DRAM cell having the one-transistor / one-capacitor structure, which includes the trench capacitor region 21 and the MOS transistor adjacent thereto. When forming the element isolation structure, the pattern resist 5 for forming the field insulating film can be continuously formed in a straight shape without being divided in the column direction.

Therefore, even with the resolution of the current lithographic technique, the problem that the pattern resist 5 is rounded at a portion corresponding to the element block region does not occur at all, so that the pattern is formed based on this element isolation pattern. In the element formation region surrounded by the element isolation region, as shown in FIG. 5, the drain region side and the source region side of the channel region under the gate electrode 17 of the MOS transistor adjacent to the trench capacitor region 21 have the same channel width. It can be formed to have W0. That is, the electrical characteristics of the MOS transistor can be obtained as designed, and the electrical characteristics do not differ for each MOS transistor.

[0056]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, a plurality of semiconductor elements are arranged in rows and columns and a plurality of rows are arranged in the column direction in the element array in which the elements are separated by the field insulating film. When the element isolation structure is formed for each element, the pattern resist for forming the field insulating film can be continuously formed without dividing in the column direction, and the electric characteristics of the element can be obtained as designed. .

[Brief description of drawings]

FIG. 1 is a DRAM according to an embodiment of a semiconductor device of the present invention.
Top view showing a plane pattern on a semiconductor substrate in a part of the manufacturing process of FIG.

2 is a cross-sectional view showing the cross-sectional structure of the semiconductor substrate in the manufacturing process of FIG.

3 is a cross-sectional view showing a cross-sectional structure of a semiconductor substrate in a manufacturing process that follows the manufacturing process in FIG.

FIG. 4 is a sectional view showing a sectional structure of a semiconductor substrate in a manufacturing process that follows the manufacturing process in FIG.

5 is a channel width and a source on a drain region side below a gate electrode region of a transistor adjacent to a trench capacitor region in an element formation region surrounded by an element isolation region formed on the basis of an element isolation pattern resist in FIG. 1; The top view which shows a mode that the channel width on the region side is equal.

FIG. 6 is a top view showing a plane pattern on a semiconductor substrate in a part of a conventional DRAM manufacturing process.

7 is a cross-sectional view showing the cross-sectional structure of the semiconductor substrate in the manufacturing process of FIG.

8 is a sectional view showing a sectional structure of a semiconductor substrate in a manufacturing process that follows the manufacturing process in FIG.

9 is a cross-sectional view showing the cross-sectional structure of the semiconductor substrate in a manufacturing process that follows the manufacturing process in FIG.

10 is a top view showing an example of the shape of the pattern resist actually formed due to the limit of resolution in the lithography technique when the element isolation pattern resist shown in FIG. 6 is formed.

11 is a drain region side channel width and a source region below a gate electrode region of a transistor adjacent to a trench capacitor region in an element formation region surrounded by an element isolation region formed on the basis of the element isolation pattern resist of FIG. 10; The top view which shows a mode that the channel width of the side differs.

[Explanation of symbols]

1 ... N-type semiconductor substrate, 2 ... P-type well layer, 3 ... First oxide film, 4 ... First silicon nitride film, 5 ... Element isolation pattern resist film, 5 ′ ... Actually formed element isolation pattern Resist, 6a ... Field oxide film, 7 ... Second silicon nitride film, 8 ... Trench hole pattern resist film, 8
a ... Trench, 9 ... Second oxide film, 10 ... First N-type polysilicon electrode, 11 ... Capacitor gate insulating film, 12
... second N-type polysilicon electrode, 13 ... sidewall etching pattern resist, 14 ... third N-type polysilicon electrode, 15 ... third oxide film, 16 ... transistor gate insulating film, 17 ... fourth N-type Polysilicon electrode, 18 ... Transistor electrode pattern resist, 19 ... Arsenic ion implantation region, 20 ... Source / drain region, 21 ... Trench capacitor region.

Claims (4)

[Claims] 1. An element array formed on a semiconductor substrate in which semiconductor elements are arranged in a matrix, a field insulating film for element isolation provided between rows in the element array, and a column in the element array. And at least one trench whose inner wall is covered with an insulating film, the semiconductor device being located between element block regions each including a plurality of element formation regions in the direction. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a dynamic memory cell including one MOS transistor and one capacitor, and the capacitor is formed in the trench. A semiconductor device characterized by the above. 3. A field oxide film having a striped straight pattern is formed on a surface layer portion of the semiconductor substrate by using a lithography technique for forming an element isolation pattern resist having a striped straight pattern on a semiconductor substrate. A step of forming a plurality of trenches at intervals in the lengthwise direction of the element forming region between the field oxide films, a step of forming an insulating film on a sidewall in the trench, and the trench And a step of forming a plurality of semiconductor elements in each of the element forming regions divided in the length direction by the method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the semiconductor element includes the step of forming a capacitor in the trench, and the source or drain is connected to a charge storage node of the capacitor. And a step of forming a MOS transistor therein.