KR960000720B1 - Dynamic semiconductor memory and its making method - Google Patents

Abstract

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Description

Dynamic semiconductor memory device and manufacturing method

1A and 1B are a plan view and a cross-sectional view taken along line A-A ', respectively, showing the structure of a DRAM according to the first embodiment of the present invention.

2 (a) to 2 (k) are cross-sectional views showing the manufacturing process of the DRAM shown in FIG.

3 is a cross-sectional view showing a structure of a DRAM according to a second embodiment of the present invention.

4 (a) to 4 (i) are cross-sectional views showing a manufacturing process of the DRAM shown in FIG.

5 is a cross-sectional view showing a structure of a DRAM according to a third embodiment of the present invention.

6 is a cross-sectional view showing a structure of a DRAM according to a fourth embodiment of the present invention.

7 is a cross-sectional view showing a structure of a DRAM according to a fifth embodiment of the present invention.

8 is a cross-sectional view showing a structure of a DRAM according to a sixth embodiment of the present invention.

9 is a perspective view showing the shape of a substrate in the first to sixth embodiments of the present invention.

10 is a perspective view showing the shape of a substrate in the seventh to ninth embodiments according to the present invention.

11A and 11B are a plan view and a sectional view taken along line A-A ', respectively, of the DRAM structure according to the seventh embodiment of the present invention.

12 (a) to 15 (b) are plan views and cross-sectional views showing the DRAM manufacturing process shown in FIG.

FIG. 16 is a cross-sectional view showing a structure of a DRAM according to an eighth embodiment of the present invention. FIG.

17 is a sectional view showing the structure of a DRAM according to the ninth embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: P ^- type silicon substrate 2: Groove

3: columnar silicon layer 4: device isolation oxide film

5: P ⁺ shaped layer 6: gate smoke film

7 gate electrode 8,9 n ⁺ type diffusion layer

10 interlayer insulating film 11 capacitor

12 capacitor capacitor 13 cell plate

14 interlayer insulating film 15 bit line

21: silicon oxide film / nitride film laminated film 22: silicon oxide film

23 silicon nitride film 31 projection

[Industrial use]

The present invention relates to a dynamic semiconductor memory device in which memory cells are formed by capacitors and MOS transistors. In particular, each memory cell is formed by using respective columnar semiconductor layers arranged in a matrix and separated by grooves. A dynamic semiconductor memory device (DRAM) and a method of manufacturing the same.

[Traditional Technology and Problems]

MOS type DRAMs are highly integrated and large in size due to the miniaturization of devices. As a DRAM structure suitable for high integration and large capacity, a columnar semiconductor layer is formed in a memory cell region by forming grooves vertically and horizontally formed on a semiconductor substrate. It is proposed to vertically stack a capacitor and a MOS transistor in a semiconductor layer (for example, Japanese Patent Laid-Open No. 60-152056). According to this structure, a capacitor electrode (cell plate) is embedded in the lower portion of the groove, and a gate electrode is formed to surround the columnar semiconductor layer thereon to form a memory cell. In such a structure, since the capacitor and the MOS transistor are stacked vertically, the occupied area of the memory cell is reduced, which enables high integration of the memory cell.

However, in this structure, a deep groove of about 10 占 퐉 must be formed, and a step of embedding and laminating a film in the longitudinal direction by the CVD method in the inside of the groove requires the formation of a diffusion layer functioning as a storage node. For this reason, the manufacturing process becomes complicated due to the fact that impurities must be diffused on the side surface of the columnar semiconductor layer. In addition, since deep grooves are formed on the substrate, distortion of the substrate is likely to occur, and the memory holding characteristics are not easy to deteriorate, and the resistance to stiff errors is also weakened.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and an object thereof is to provide a dynamic semiconductor memory device and a method for manufacturing the same, which can simplify the manufacturing process and obtain good memory holding characteristics.

[Configuration of Invention]

In accordance with another aspect of the present invention, there is provided a dynamic semiconductor memory device comprising: a plurality of columnar semiconductor layers arranged in a matrix by grooves formed longitudinally and horizontally in the substrate, an isolation region formed in a center portion of the grooves, A MOS transistor having a gate electrode provided through a gate insulating film so as to surround the columnar semiconductor layers, and a source and drain diffusion layer formed at an upper portion of the columnar semiconductor layer and a lower portion of the groove, and a gate electrode by an interlayer insulating film. An accumulation node formed to surround the pillar-shaped semiconductor layer in which the gate electrode is formed while being in contact with the diffusion layer of the lower portion of the groove; And contacting the diffusion layer on each of the columnar semiconductor layers. Which it is composed by including a bit line.

In addition, the method for manufacturing a dynamic semiconductor memory device according to the present invention comprises the steps of forming a plurality of columnar semiconductor layers arranged in a matrix by forming grooves vertically and horizontally formed on a semiconductor substrate, and forming a central portion of the grooves. Forming a device isolation region according to the present invention, forming a gate insulating film around each of the columnar semiconductor layers, and forming a gate electrode continuous in the first direction of the matrix while surrounding the columnar semiconductor layers. Forming a diffusion layer serving as a source or a drain region in the lower portion of the groove so as to surround the layer; forming an interlayer insulating film on the surface of the gate electrode, and then surrounding the columnar semiconductor layer in which the gate electrode is formed, Forming a storage node of the capacitor so as to be in contact with each other; forming a capacitor insulating film on the surface of the storage node Embedding the cell plate in the trench, covering the cell plate with an interlayer insulating film, exposing the top surface of the columnar semiconductor layer and forming a diffusion layer serving as a source or drain region on the exposed surface; and the columnar semiconductor layer And forming a bit line in contact with the diffusion layer on the upper surface and continuing in the second direction of the matrix.

(Action)

According to the present invention configured as described above, the gate electrode of the MOS transistor, the scale node of the capacitor, and the cell plate are all self-aligned to be formed so as to surround the columnar semiconductor layer in the groove. Therefore, as in the conventional structure in which the cell plates and the gate electrodes are stacked vertically, deep grooves are not required, so that the substrate is less crushed, and as a result, excellent memory retention characteristics can be obtained. In addition, the flatness is also superior to that of a conventional stack cell structure. Furthermore, since the accumulation node is formed in a cylindrical shape around the gate electrode, it has a small cell area while obtaining a sufficiently large capacitor capacity. In addition, since both the MOS transistor and the capacitor have a vertical structure, the occupied area of the memory cell is reduced, resulting in highly integrated DRAM.

In addition, in the method of manufacturing the dynamic semiconductor memory device according to the present invention, the process of forming the gate electrode, the capacitor accumulation node, and the cell plate is performed in a self-aligning manner, thereby simplifying the manufacturing process.

Example

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a plan view showing a 4-bit configuration of a DRAM according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line A-A 'of the p ^- type 100 single crystal silicon substrate. (1; or p ^- type well formed on n-type substrate) formed vertically and horizontally using reactive ion etching. The columnar silicon layer 3 is arranged in a matrix form by the grooves 2, A device isolation oxide film 4 is formed in the center portion, and a p ⁺ type inversion prevention layer 5 is formed under the device isolation oxide film 4. The gate insulating film 6 is formed on the sidewall of each columnar silicon layer 3, and the gate electrode 7 made of the first layer polycrystalline silicon is arranged so as to surround the columnar silicon layer 3. N ⁺ type diffusion layers 8 and 9 serving as a source and a drain are formed on the upper surface of each columnar silicon layer 3 and the lower part of the groove, respectively, and vertical MOS transistors are formed on each columnar silicon layer 3. Is composed. The n ⁺ type diffusion layer 9 at the bottom of the groove is separated by the element isolation oxide film 4 and formed to surround each columnar silicon layer 3. The gate electrode 7 is formed continuously in the connecting portion 7 'in the first direction (y direction) of the matrix, which becomes a word line. The connection portion 7 'is a first layer polycrystalline silicon similarly to the gate electrode 7, and is formed by using a photoresist mask in an etching process in which the first layer polycrystalline silicon is left on the sidewall of the columnar silicon layer 3. Will remain in the part. An interlayer insulating film 10 is formed on the surface of the gate electrode 7, and the second layer polycrystalline silicon is formed on the sidewall of the gate electrode 7 so as to surround each columnar silicon layer 3 like the gate electrode 7. The accumulation node 11 of the capacitor which is formed is formed. The accumulation node 11 is an independent memory node for each columnar silicon layer 3 and is in contact with each n ⁺ type diffusion layer 9 at the bottom of the groove. A capacitor insulating film 12 is formed on the surface of the storage node 11, and a cell plate 13 made of third layer polycrystalline silicon is buried in the groove 2 so as to face the storage node 11. The cell plate 13 is continuous along the grooves 2 formed vertically and horizontally, and becomes a capacitor electrode common to all memory cells. The wafer is flattened by embedding the cell plate 13. The interlayer insulating film 14 is stacked on this wafer, and bit lines 15 are arranged in contact with the upper part of the MOS transistors to contact the upper n ⁺ type diffusion layer 8 of each MOS transistor. The bit lines 15 are continuously arranged in the second direction (x direction) of the matrix.

2 (a) to 2 (k) show the fabrication process in the cross section along the line aa 'of FIG. 1 of the DRAM memory cell array according to the present embodiment, with reference to FIG. It demonstrates concretely about.

FIG. 2, p ⁺ type is deposited, the silicon substrate (1) 0.1㎛ the laminated film 21 of the CVD silicon oxide film and a silicon nitride film on, this anisotropic etching by an etching mask is patterned as shown in (a) The substrate is etched by RIE to form the grooves 2 extending vertically and horizontally. As a result, the columnar silicon layers 3 are arranged in a matrix.

Next, as shown in Fig. 2 (b), after forming the thermal oxide film 22 having a thickness of 0.1 mu m, the silicon oxide film 23 having a thickness of 1 mu m is deposited by CVD and etched to the entire surface to form the columnar silicon layer 3 Leave only on the side of). Then, after forming the p ⁺ type layer 5 by ion implantation into the discharge preventing layer in the lower portion of the groove 2, thermal oxidation is performed to obtain a device isolation oxide film having a thickness of about 03 탆 as shown in FIG. (4) is formed. This device isolation film 4 is basically the same as a conventional LOCOS method.

Subsequently, as shown in FIG. 2 (d), the silicon oxide film 23 and the silicon oxide film 22 used as the oxidation resistant mask are removed, and about 0.02 is thermally oxidized around each of the columnar silicon layers 3. A gate insulating film 6 of 탆 is formed. Then, the first layer polysilicon film is deposited on the entire surface by about 0.1 占 퐉 and then etched by the RIE method to form the gate electrode 7 so as to surround the columnar silicon layer 3. In this RIE process, a photoresist pattern is formed on the connection portion 7 ′ described in FIG. 1 so that the gate electrode 7 continues in the y direction. Thereafter, arsenic is implanted to form an n ⁺ type diffusion layer 9 which becomes either a source or a drain in the lower portion of the groove. Then, as shown in FIG. 2 (e), the oxide film is etched to expose the lower portion of the groove, and thermal oxidation is performed again, so as to show the surface of the gate electrode 7 as the oxide film as shown in FIG. The interlayer insulating film 10 is formed. Thereafter, the oxide film on the n ⁺ type diffusion layer 9 at the bottom of the groove is removed by etching with NH ₄ F, as shown in FIG. As shown in FIG. 2 (h), a second layer polysilicon film 110 having a thickness of about 0.7 m is deposited on the entire surface. Next, polysilicon etching is performed by RIE, so as to surround the gate electrode 7 as shown in FIG. 2 (i), and an accumulation node 11 of a self-aligning capacitor is formed therewith. The accumulation node 11 is in contact with the n ⁺ type diffusion layer 9 at the bottom of the groove.

Thereafter, as shown in FIG. 2 (j), after forming the capacitor insulating film 12 on the surface of the storage node 11, the third layer polysilicon is buried in the groove 2 to form the cell plate 13. Form. The capacitor insulating film 12 is, for example, a nitride oxide film (oxidized film thickness of 0.005 탆) in which a silicon oxide film is deposited on the entire surface by CVD and oxidized. The cell plate 13 deposits the third layer polycrystalline silicon, and is flattened in the groove 2 by, for example, planarizing the photoresist and etching the entire surface by RIE method under the same etching rate for the polysilicon and the photoresist. do. Thereafter, as shown in FIG. 2 (k), an interlayer insulating film 14, such as a CVD silicon oxide film, is deposited on the entire surface and anisotropically etched to expose the top surface of the columnar silicon layer 3 and implanted with arsenic ions. An n ⁺ type diffusion layer 8 is formed. Then, a conductive film such as an Al film is deposited and patterned to form a bit line 15 connected to the n ⁺ type diffusion layer 8.

According to the present embodiment, the gate electrode 7 and the storage node 11 of the capacitor are formed in self-alignment around the columnar silicon layer 3 in sequence, and the cell plate 13 is embedded in the remaining grooves. A capacitor and a MOS transistor are configured. Thus, as in the conventional structure in which the capacitor and the MOS transistor are vertically stacked in the groove, no deep groove is required. As a result, the distortion which generate | occur | produces in a board | substrate is suppressed. Since both the MOS capacitor and the MOS transistor are vertical structures, the memory cell occupies a small area, resulting in highly integrated DRAM. In addition, when the width of the columnar silicon layer 3 is reduced to a certain degree or more, the columnar silicon layer becomes a complete space charge region easily by the space charge region extending from the periphery to the inside. For this reason, the channel controllability is improved by the gate electrode, thereby improving the subthreshold characteristic. The influence of the substrate potential is also lessened.

In addition, in the method of this embodiment, since the process of forming each electrode is basically formed all around the columnar silicon layer without requiring a lithography process, the process is simple and the process control is easy.

Next, some other embodiments will be described. In the following embodiments, parts corresponding to the first embodiment are denoted by the same reference numerals.

FIG. 3 shows a cross-sectional structure of one memory cell portion of a DRAM according to the second embodiment of the present invention. In this embodiment, a projection 31 having a reduced diameter is formed on an upper portion of the columnar silicon layer 3. The n ⁺ type diffusion layer 8 is formed on the upper surface portion of the protrusion 31. This structure can be brought into self-aligned contact without requiring a lithography process when the bit line 15 is brought into contact with the n ⁺ type diffusion layer 8, as can be clearly seen in the following manufacturing process. It is structured.

4 (a) to 4 (i) are cross-sectional views sequentially showing the manufacturing process.

First, as shown in FIG. 4A, a mask formed of a silicon oxide film and a silicon nitride film laminated plate 21 is patterned on a p ⁺ type silicon substrate 1, and the substrate is then anisotropically etched to form a shallow groove. (2) is formed so that the protrusions 31 are arranged. Subsequently, as shown in FIG. 4 (b), after the silicon oxide film 22 is formed by thermal oxidation, the silicon nitride film 23 ₁ is formed on the sidewall of the projection 31. Then, the anisotropic etching is performed using the laminated film 22 and the nitride film 23 ₁ as a mask to further etch the substrate 1 to deeply form the grooves 2 as shown in FIG. Thereby, the columnar silicon layer 3 which has the small diameter processus | protrusion 31 on top is obtained. Thereafter, a silicon nitride film 23 ₂ is formed on the sidewall of the columnar silicon layer 3 and thermally oxidized to form the device isolation oxide film 4 as shown in FIG. Under the device isolation oxide film 4, a p ⁺ type layer 5 for separation is formed in the same manner as in the first embodiment.

Thereafter, the gate electrode 7, the n ⁺ -type diffusion layer 9, the storage node 11 of the capacitor, and the cell plate 13 are subjected to the same process as in the first embodiment as shown in FIG. 4E. Form in turn. In this case, as shown in the figure, the gate electrode 7, the accumulation node 11, and the cell plate 13 may be formed below the upper protrusion 31 of the columnar silicon layer 3. Next, as shown in Fig. 4 (f), the CVD silicon oxide film 14 is deposited on the entire surface so as to be flat on the surface, and then etched to form a projection 31 as shown in Fig. 4 (g). The part is exposed. On the other hand, for the surface leveling of the silicon oxide film 14, a photoresist may be used as described in the first embodiment. Then, as shown in FIG. 4 (h), the insulating film covering the exposed portions 31 is removed, and an n ⁺ type diffusion layer 8 is formed on the exposed surface. As a result, the n ⁺ type diffusion layer 8 of each columnar silicon layer 3 is obtained with its surface exposed without a lithography process. Thereafter, for example, the Al film is deposited and patterned to form the bit lines 15 as shown in FIG.

As described above, according to the present embodiment, the contact portions of the bit lines are formed to be self-aligning without using the lithography process.

FIG. 5 is a diagram showing a DRAM memory cell structure according to a third embodiment of the present invention, in which the storage node 11 of the capacitor not only has the side of the gate electrode 7 but also the columnar silicon layer 3. It is formed to further cover the upper surface of the. The cell plate 13 is also thickly formed so as to cover the upper branch from the side surface of the accumulation node 11.

Specifically, in order to obtain such a structure, the polysilicon is not etched on the columnar silicon layer 3 during the etching process of patterning the accumulation node 11 of the capacitor formed of the second layer polycrystalline silicon film, for example. A mask is formed. Even when the cell plate 13 is embedded, the cell plate 13 is covered with a portion of the columnar silicon layer 3. That is, when the silicon oxide film 14 is deposited, the second layer polycrystalline silicon film and the third layer polycrystalline silicon film remain on the columnar silicon layer 3. The second layer polysilicon film remains on top of each of the columnar silicon layers 3, but is separated between the adjacent columnar silicon layers 3 as in the previous embodiment. Then, a contact hole is drilled through the interlayer insulating film 14, and the third layer polycrystalline silicon film and the second layer polycrystalline silicon film below are etched away to form an n ⁺ type diffusion layer 8. Then, after forming the insulating film 51 on the side of the polysilicon film exposed to the contact hole, the bit lines 15 in contact with the n ⁺ type diffusion layer 8 are arranged.

According to the present embodiment, the electrode opposing area of the capacitor is larger than the area of the side of the gate electrode, so that a large capacitor capacity is obtained. The memory cell occupying area is the same as in the previous embodiment. Therefore, a high integration is possible and a DRAM having excellent characteristics can be obtained.

6 is a view showing a structure of a DRANM memory cell according to a fourth embodiment of the present invention. In this embodiment, a separation groove 61 is formed in the center of the groove 2 without using a thick device isolation oxide film by the LOCOS method. ) Is further formed to separate the elements. It is preferable to form the p ⁺ type layer 5 below this separation groove 61 as shown in the figure.

In the structure of the present embodiment, the n ⁺ type diffusion layer 9 is formed by forming the gate electrode 7 and forming the n ⁺ type layer on the entire lower portion of the groove 2 by ion implantation, and then processing the separation groove 61. Is obtained by separating each memory cell.

FIG. 7 is a diagram showing a DRAM memory cell structure according to the fifth embodiment of the present invention. In this embodiment, the SOI structure is used. That is, a wafer in which a silicon oxide film 71 is formed on the silicon substrate 1 and a p ⁻ type layer silicon layer 72 is formed thereon is used. Separation grooves 61 are formed in the element isolation region as in the embodiment of FIG.

According to the present embodiment, the memory cells are completely separated by the silicon oxide film 71. Further, the portion of the startable silicon layer 3 of each memory cell can be easily made a complete space charge region, and the controllability is improved by the gate electrode 7, and the subcritical characteristic is improved. The influence of the substrate potential is also almost eliminated.

8 shows a DRAM memory cell structure in the sixth embodiment of the present invention. Unlike in the present embodiment, the cell plate 13 is buried in the lower portion of the groove 2 in the present embodiment. The conventional vertical lamination method of laminating the gate electrodes 7 of the MOS transistors is used above. In this manner, the self-aligned contact method of the bit lines as described in the embodiment of FIG. 3 is combined.

In the present embodiment, deep grooves are required as compared with the above, but the bit line contact becomes self-aligning.

Each of the above-described embodiments uses the silicon substrate 1 shown in FIG. 9, and the substrate 1 has columnar semiconductor base layers (2) formed by grooves 2 formed vertically and horizontally as shown in FIG. 3), the gate electrode 7, the accumulation node 11, and the cell plate 13 are buried in turn to surround the columnar semiconductor layer 3 around it.

In each of the embodiments to be described below, the concave portion and the blocked portion of the substrate are reversed from those of the first to sixth embodiments. That is, as shown in FIG. 10, a plurality of grooves 2a are formed in the memory cell region of the substrate, and the silicon layer 3a located outside the grooves 2a is formed continuously in the vertical and horizontal directions. The gate electrode, the storage node, and the cell plate are embedded in each of the grooves 2a in turn.

11A and 11B are a plan view showing a structure of a DRAM according to a seventh embodiment of the present invention using the substrate shown in FIG. 10 and a cross-sectional view taken along line A-A ', respectively. The same parts as in Figs. 1A and 1B are given the same reference numerals.

Here, the element isolation oxide film 4 is formed in a stripe shape by the LOCOS method in the center of the silicon layer 3a, and the gate electrode 7 and the storage node 11 and the cell are formed in each groove 2a which is a cell region. The plate 13 is embedded in sequence. The gate electrode 7 of each memory cell is formed successively in the X direction by the connecting portion 7 'so as to be a word line. An n ⁺ type diffusion layer 9 connected to the accumulation node 11 is formed in the entire lower portion of each of the grooves 2a. In the n ⁺ type diffusion layer 8 which can be used as a bit line, the groove 9 is formed.

Next, as described above, a vertical MOSFET is formed in each of the grooves 2a, and the n ⁺ type diffusion layer 8 which functions as a drain and a bit line of the MOSFET is continuous in the y direction while the respective grooves 2a are formed. It is formed to cover. And the Al bit line 15 is formed in the upper part. The Al bit line 15 is additionally provided to reduce the resistance of the bit line formed by the n ⁺ type diffusion layer 8, and comes into contact with the n ⁺ type diffusion layer 8 at the connection portion 91.

Next, a manufacturing process of a DRAM according to the present embodiment will be described with reference to FIGS. 12 (a, b) to 15 (a, b).

First, as shown in FIGS. 12A and 12B, the element isolation oxide film 4 is formed vertically and horizontally on the silicon substrate 1 by the LOCOS method, and has a continuous shape in the y direction. Is made. Under the device isolation oxide film 4, a p ⁺ type layer 5, which is used as an anti-reversal layer, is formed. The n ⁺ type diffusion layer 8, which can be used as a drain and bit line of the MOSFET, is formed on the entire surface of the region surrounding the device isolation oxide film 4. Then, the grooves 2a are formed in each memory cell area. The size of the groove 2a is smaller than the size of the region surrounding the element isolation oxide film 4 so that the n ⁺ type diffusion layer 8 remains on its main surface. At this time, the groove 2a is formed by, for example, etching by RIE method using a CVD oxide film (not shown) as an etching mask. Accordingly, the n ⁺ type diffusion layer 8 is patterned so as to be continuous in the y direction while surrounding the groove 2a.

Thereafter, as shown in Figs. 13A and 13B, a gate oxide film 6 having a thickness of about 20 nm is formed on the inner wall of the groove 2a by the thermal oxidation method. After that, a first layer polysilicon film having a thickness of about 100 nm is deposited, and then the gate electrode 7 is formed on the inner side wall of the groove 2a by etching using an RIE method. Here, at the time of etching the first layer polysilicon film, the gate electrode 7 is formed on the inner wall of the groove 2a in a self-aligning manner. Here, the connecting portion 7 'for continuing the gate electrode 7 in the X direction is left by photolithography during the etching of the first layer polycrystalline silicon film. Thereafter, ion implantation is performed to form an n ⁺ type diffusion layer 9 which extends to the accumulation node while serving as a source of a MOSFET in the lower portion of each groove 2a.

Next, as shown in FIGS. 14A and 14B, the surface of the gate electrode 7 is oxidized and covered with the oxide film 10, and then the bottom of the groove 2a is etched using NH ₄ F. The oxide film of the part is removed. Thereafter, a second layer polysilicon having a thickness of about 20 nm is deposited and then etched by RIE to form the accumulation node 11 in the gate electrode 7 in a self-aligned manner with the gate electrode 7. do. However, in the RIE process of this embodiment, since a mask is formed around the groove 2a by photolithography so that a part of the accumulation node 11 extends outward of the groove 2a, the lower portion of the accumulation node 11 Is in contact with the diffusion layer (9).

Next, as shown in the fifteenth (a) and fifteenth (b), the capacitor insulating film 12 is formed on the surface of the accumulation node 11 by thermal oxidation and deposition of silicon nitride film. Thereafter, the cell plate 13 made of the third layer polysilicon film having a thickness of about 30 nm is embedded in the groove 2a while covering the entire surface of the substrate so as to face the accumulation node 11. The cell plate 13 is formed by photolithography with an opening 92 used as a contact portion with an Al bit line formed later.

Next, as shown in Figs. 11A and 11B, an interlayer insulating film 14 having a thickness of about 300 nm is formed by the CVD method. In this interlayer insulating film 14, a contact hole 91 overlapping the opening 92 of the cell plate 13 is formed, and then an Al bit line 15 is formed.

As described above, the seventh embodiment according to the present invention has been described. In this seventh embodiment, the same effects as in the first to sixth embodiments can be obtained.

FIG. 16 shows the structure of a DRAM memory according to the eighth embodiment, which is the same as the structure shown in FIG. 11 (b). However, in this embodiment, the element isolation oxide film 4 is formed by the LOCOS method rather than the buried method. I'm doing something different.

FIG. 17 shows the structure of a DRAM memory according to the ninth embodiment of the present invention, which is almost the same as that shown in FIG. 11 (b). However, in this embodiment, the accumulation node 11 is positioned outside the groove 2a. It does not extend to and is formed only inside the groove 2a. The capacity of the capacitor of this embodiment is smaller than that of the seventh embodiment, but since there is no photolithography process for extending the accumulation node 11 to the outside of the groove 2a, the manufacturing process becomes simpler.

[Effects of the Invention]

As described above, according to the present invention, since the deep groove is not required, the influence of the substrate distortion is small, so that excellent memory holding characteristics can be obtained and a DRAM capable of high integration can be provided.

In addition, according to the manufacturing method of the present invention, since the electrodes are sequentially filled around the columnar semiconductor layer by a self-aligning process, a highly integrated DRAM can be manufactured in a simple process.

Claims (14)

A plurality of columnar semiconductor layers 3 arranged in a matrix form by the semiconductor substrate 1 and the grooves 2 formed on the semiconductor substrate 1 in the longitudinal and horizontal direction, are formed in the center portion of the grooves 2. A capacitor formed between the device isolation region 4, the MOS transistor formed around each of the columnar semiconductor layers 3, the cell plate 13 of the storage node 11 connected to the source of the MOS transistor, The MOS transistor includes a bit line 15 connected to the drain of the MOS transistor. The MOS transistor includes a gate electrode 7 surrounding the columnar semiconductor layer 3 via a gate insulating film 6, and A drain diffusion layer 8 formed on the upper surface of the columnar semiconductor layer 3 and a source diffusion layer 9 formed on the lower portion of the groove 2; The accumulation node 11 is separated from the gate electrode 7 by the interlayer insulating film 10 surrounding the pillar-shaped semiconductor layer 3 so as to contact the source diffusion layer 9 under the groove 2. It is embedded in the groove (2); The cell plate 13 is embedded in the groove 2 so as to face the accumulation node 11 via a capacitor insulating film 12; The non-wire (15) is a dynamic semiconductor memory device, characterized in that arranged in contact with the drain diffusion layer (8) on the columnar semiconductor layer (3). The method of claim 1, wherein the gate electrodes (7) are continuously arranged in the first direction of the matrix to function as word lines, and the bit lines (15) are arranged so as to be continuous in the second direction of the matrix. Dynamic semiconductor memory device. 2. A dynamic semiconductor memory device according to claim 1, wherein an oxide film (4) is formed by said element isolation region LOCOS method. 2. The dynamic semiconductor memory device according to claim 1, wherein said device isolation region cell isolation groove (61) is formed. 2. A dynamic semiconductor memory device according to claim 1, wherein a projection (31) is provided on the columnar semiconductor layer (3) in which the drain diffusion layer (8) is formed. 2. The storage node (11) according to claim 1, wherein the storage node (11) is formed to cover not only the side surface of the gate electrode (7) but also the upper surface thereof, and the cell plate (13) has the storage node (11) as well as the side surface thereof. A dynamic semiconductor memory device, characterized in that the upper surface is also covered. MOS transistors formed on the inner sidewalls of the semiconductor substrate 1 and the respective grooves 2a arranged in a matrix form on the substrate 1, storage nodes connected to the sources of the MOS transistors, and the storage nodes and the cell plates. And having a capacitor formed between the elements, the device isolation region 4 is formed so as to be continuous in the first direction between the grooves 2a arranged in a matrix form on the substrate 1; ; The gate electrode 7 of the MOS transistor is buried so as to surround the inner wall of each of the grooves 2a via the gate insulating film 6 and connected in the second direction of the matrix to function as a word line; A source diffusion layer 9 of the MOS transistors is formed in the lower portion of each of the grooves 2a; The drain diffusion layer 8 of the MOS transistor is formed so as to surround the outer periphery of the groove 2a while continuing in the second direction of the matrix to function as a bit line; An accumulation node (11) surrounds the inner wall of the gate electrode (7) such that the gate electrode (7) is separated from the interlayer insulating layer (10) so as to contact the source diffusion layer (9) under the groove (2a); And a cell plate (12) is buried in the groove (2a) so as to face the accumulation node (11) via a capacitor insulating film (12). 8. The dynamic semiconductor memory device according to claim 7, wherein the accumulation node (11) is patterned to partially extend to the outer forest of each groove (2a). 8. The dynamic semiconductor memory device according to claim 7, wherein the accumulation node (11) is locally embedded in each of the grooves (2a). 8. The plate (13) according to claim 7, wherein the plate (13) has an opening (92) in an area to be contacted with the drain diffusion layer (8) while being deposited so that its surface is flat; The metal bit line 15 is formed on the cell plate 13 via the interlayer insulating film 14 and is in contact with the drain diffusion layer 8 through the contact hole 91 formed in the opening 92. A dynamic semiconductor memory device. Forming a plurality of columnar semiconductor layers 3 arranged in a matrix by forming grooves 2 extending longitudinally and horizontally on the semiconductor substrate 1; Forming an isolation region (4) in the center of the groove (2); Forming the columnar semiconductor layer (3); Forming an isolation region (4) in the center of the groove (2); After the gate insulating film 6 is formed around the columnar semiconductor layer 3, the gate electrode 7 is formed in a continuous direction in the matrix to surround the columnar semiconductor layers 3. ; Forming a diffusion layer (9) as a source or drain region under the groove (2) using the gate electrode (7) as a mask; After the interlayer insulating film 10 is formed on the surface of the gate electrode 7, the capacitor may be contacted with the diffusion layer 9 while surrounding the columnar semiconductor layers 3 on which the gate electrode 7 is formed. Forming an accumulation node 11; Filling a cell plate 13 in the groove 2 after forming a capacitor insulating film 12 on the surface of the storage node 11; After covering the upper surface of the cell plate 13 with the interlayer insulating film 14, exposing the upper surface of the columnar semiconductor layer 3, and forming a diffusion layer 8 as a source or a drain on the exposed upper surface The stage; And forming a bit line (15) continuous in the second direction of the matrix while being in contact with the surface of the diffusion layer (8) formed on the columnar semiconductor (3). The method of claim 11, wherein the step of forming the device isolation region 4 of the groove 2 is performed by a thermal oxidation method using a mask material formed around the columnar semiconductor layer (3). Semiconductor memory device. The method of claim 11, wherein the forming of the isolation region 4 of the groove 2 is performed by forming the diffusion layer 9 below the groove 2 using the gate electrode 7 as a mask. A dynamic semiconductor memory device, characterized in that the step of forming a separation groove (61) in the center of (2). Forming a plurality of drain diffusion layers 8 functioning as bit lines in the cell formation region of the semiconductor substrate 1; Forming a plurality of grooves (2a) formed in a matrix form on the substrate (1) deeper than the drain diffusion layer (8); Embedding the gate electrode (7) around the inner wall of the groove (2a) via a gate insulating film (6); Forming a source diffusion layer 9 at a lower portion of the groove 2a; The storage node 11 is separated from the gate electrode 7 by the insulating film 10 on the inner wall surface of the groove 2a in which the gate electrode 7 is embedded, and the lower portion thereof is in contact with the source diffusion layer 9. Landfill; Forming a capacitor insulating film (12) on the surface of the accumulation node (11); And embedding a cell plate (13) in the groove (2a) so as to face the accumulation node (11) via a capacitor insulating film (12).