JPH1084091A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM having a COB(capacitor over bit line) structure in which the positions of contact holes are secured for connecting a storage capacitor between bit lines, active region patterns enough for ensuring insulation between devices are formed and at the same time bit line patterns have the advantage of reducing stray capacitance capacity and are suitable for microfabrication. SOLUTION: The angle of active regions 2b in the form of a gull-wing is obtuse for ensuring the proximity d between the active regions 2b. A lower layer contact hole 9a of a first contact hole for connection to bit lines BL in a first semiconductor region 6a in the center of an active region 2b is formed and a plug 10a is formed in the lower layer contact hole 9a of the first contact hole. An upper layer contact hole 11a of the first contact hole is formed in a position with an offset L outside the active region 2b from the position directly above the plug 10a. Additionally, bit lines BL having an inclusive pattern DB including the upper layer contact hole 11a of the first contact hole are formed in the upper layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory that represents a large-capacity memory. The memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell must be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the storage capacitance of an information storage capacitor (capacitor) in a memory cell of a DRAM is DR
It is known that a certain amount is required regardless of the generation from the viewpoint of consideration of the operation margin of the AM, the soft error, and the like, and it is generally not possible to reduce proportionally.

Therefore, for example, November 30, 1984
Published by Ohm Co., Ltd., "LSI Handbook",
As described on page 489, in recent large-capacity DRAMs,
In order to compensate for the decrease in the amount of stored charge (Cs) of the information storage capacitor due to the miniaturization of the memory cell, a stack structure in which the information storage capacitor is disposed above the memory cell selection MISFET is employed.

There are various types of stack structures. Among them, a so-called capacitor-over-bit line in which the information storage capacitor is arranged above the bit line.
In the structure (Capacitor Over Bitline; hereinafter abbreviated as COB), the process step when forming the information storage capacitor is reduced because the underlying step of the storage electrode (storage node) is flattened by the bit line. There is a feature. In addition, since the bit line is shielded by the information storage capacitor, a high signal-to-noise (S / N) ratio can be obtained. A DRAM having a memory cell having a COB structure is described in Japanese Patent Application Laid-Open No. 7-122654.

In such a memory cell having the COB structure,
Two memory cell selecting MISFETs sharing a bit line are formed in an active region surrounded by a field insulating film,
Furthermore, a semiconductor region (first region) located at the center of the active region
A bit line is connected to the semiconductor region (second semiconductor region) through the first connection hole, and the semiconductor region (second semiconductor region) located at both ends of the active region is connected.
The storage electrode of the information storage capacitance element is connected to the semiconductor region of FIG.

In the memory cell having the COB structure, the bit line is connected to the first semiconductor region, and then the storage electrode of the information storage capacitor is connected to the second semiconductor region. If the line extends directly above the second semiconductor region connecting the storage electrode, the storage electrode cannot be connected to the second semiconductor region.

Therefore, the bit line is shifted from directly above the linear active region, and a protrusion is provided on the bit line so as to cover only the first connection hole on the first semiconductor region to form a lead pad. Pattern or US Patent No. 4,9
As described in, for example, Japanese Patent No. 70,564, a layout in which an active region and a bit line are obliquely arranged so that a bit line is not arranged immediately above a second semiconductor region to which a storage electrode is connected. Has been adopted.

However, in a layout in which the active region and the bit line are obliquely interspersed, the installation margin of an OPC (Optical Proximity Correction) pattern arranged for the purpose of preventing the shrinkage in the long side direction in the lithography process is limited. In addition, in a pattern in which a protrusion is provided on a bit line to form a lead pad, the number of steps for providing a lead pad layer for connecting an active region and a bit line is increased, and the parasitic capacitance of the bit line is increased. Is a problem.

As a measure for solving these problems, as described in Japanese Patent Application Laid-Open No. Hei 5-291532, a gull wing is formed on the active region from its outer shape.
A pattern called is used.

The active region of the gull wing structure has the shape of a symmetrical seagull wing and is arranged in plural on a semiconductor substrate. In a memory cell having an active region of the gull wing structure, A first connection hole is formed on the first semiconductor region located at the center of the active region corresponding to the body, the bit line is connected to the first semiconductor region, and the active region corresponding to the inner wing of the seagull is formed. M for memory cell selection in area
A channel region of the ISFET is located, a second connection hole is formed on the second semiconductor region corresponding to the outer wing of the seagull, and the storage electrode of the information storage capacitor is connected to the second semiconductor region. You.

If the active region has a gull-wing structure, the second connection hole is formed at a position deviated from the linear region connecting the adjacent first connection holes, so that it is not necessary to provide a lead pad portion on the bit line. Also, since the OPC pattern can be provided with a sufficient margin, the above-described problem does not occur.

[0013]

However, it has been clarified by the present inventors that the following problems occur with further miniaturization of the semiconductor integrated circuit device.

That is, when the first connection hole for connection with the bit line is included in the gull wing-shaped active region pattern and the connection is attempted to the bit line having no lead-out pad portion, the second connection Hole-1st connection hole-2nd
The angle of the active region connecting the connection holes must be sharp to some extent.

However, if the angle of the active region is made acute, it becomes difficult to secure a minimum element separation distance between adjacent active regions.

On the other hand, if the angle of the active region is set to an obtuse angle so that the first connection hole can be included in the active region pattern, it is necessary to shift the inclusion pattern of the first connection hole of the bit line. A projection similar to the pad is formed.

Due to the existence of such a convex portion of the bit line,
There is a problem in that constriction occurs at the time of lithography of a bit line, and an increase in parasitic capacitance due to a short distance between adjacent bit lines occurs.

Further, if the bit line is bent and formed to solve the above problem, it is difficult to secure a region for forming the second connection hole.

An object of the present invention is to secure a minimum element separation distance between adjacent active regions, and at the same time, enclose a first connection hole in a gull-wing-shaped active region pattern and then lead out the first connection region from the first semiconductor region. It is an object of the present invention to provide a technique capable of connecting to a bit line having no pad portion.

Another object of the present invention is to secure a minimum element separation distance between adjacent active regions, prevent a constriction from occurring at the time of lithography of bit lines, and prevent an increase in parasitic capacitance between adjacent bit lines. It is still another object of the present invention to provide a technique capable of securing an area for forming a second connection hole.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a semiconductor integrated circuit device according to the present invention, an element isolation region formed on a main surface of a semiconductor substrate and a central portion of a left-right symmetrical active region surrounded by the element isolation region. A first semiconductor region, a second semiconductor region formed at both ends of the active region, and a channel region located between the first semiconductor region and the second semiconductor region via a gate insulating film. MISFET including a gate electrode functioning as a word line and having a first semiconductor region in common, and a first connection hole opened in an insulating film formed on the semiconductor substrate and the gate electrode. First
Integrated circuit having a DRAM including in its memory cell region a bit line connected to the semiconductor region and a storage capacitor connected to the second semiconductor region through a second connection hole opened in the insulating film A device, wherein an upper surface of a first connection hole in contact with a bit line has an offset in a horizontal direction of a semiconductor substrate with respect to a first semiconductor region.

According to such a semiconductor integrated circuit device,
Since the upper surface of the first connection hole has an offset in the horizontal direction of the semiconductor substrate with respect to the first semiconductor region, the bit line that should include the upper surface of the first connection hole is activated by the active region including the first semiconductor region. It can be shifted from directly above the area.

As a result, by keeping the shape of the active region having the gull wing shape at an obtuse angle to a certain extent, the minimum element separation distance between adjacent active regions can be ensured.
The bit line can be formed at a position where the opening position of the second connection hole can be secured, and the inclusion pattern of the bit line enclosing the first connection hole is formed symmetrically with respect to the center line of the bit line. can do.

As a result, it is possible to secure the insulation between the active regions and obtain a bit line shape that can cope with fine lithography, further reduce the parasitic capacitance of the bit line, and improve the high performance. It is possible to cope with the demand for further miniaturization while maintaining it.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), wherein the first connection holes are connected in tandem with each other and extend in a direction perpendicular to the semiconductor substrate. It consists of a plurality of opened connection holes.

According to such a semiconductor integrated circuit device,
Since the first connection holes are composed of a plurality of connection holes connected in tandem with each other and opened in a direction perpendicular to the semiconductor substrate, the upper surface of the first connection hole in contact with the bit line described in (1) Can realize a structure having an offset in the horizontal direction of the semiconductor substrate with respect to the first semiconductor region.

That is, of the first connection holes connected in cascade, the connection hole forming the lowermost portion is formed directly above the first semiconductor region, and the upper connection hole connected in tandem is formed in the first connection region. By forming the first connection hole so as to be shifted from directly above the first semiconductor region, the first connection hole can have a structure in which the upper surface has an offset in the horizontal direction of the semiconductor substrate with respect to the first semiconductor region. .

Further, since the first connection hole is opened in a direction perpendicular to the semiconductor substrate, it is not necessary to employ a special etching method when opening the connection hole, and the etching which has been accumulated in the past has been used. Technology can be used, and the process can be stabilized. Furthermore, since the connection hole is formed of a plurality of connection holes, the aspect ratio of the etching for opening the connection holes can be reduced, and the etching process can be performed with a sufficient margin.

It goes without saying that an intermediate connection hole may be provided between the lower connection hole forming the lowermost portion of the first connection hole and the upper connection hole forming the uppermost portion.

The lower connection hole is filled with, for example, a plug made of polycrystalline silicon, and the uppermost connection hole is
It can be embedded by a part of the bit line.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (2), wherein the bottom surface of the lowermost one of the plurality of connection holes is in the active region. The upper surface of the connection hole located at the uppermost level and included in the first semiconductor region is included in the bit line inclusion pattern formed symmetrically with respect to the center line of the bit line, and is located at the uppermost level The connection hole is provided so as to be displaced in a direction opposite to the second connection hole with respect to the connection hole located at the lowest stage.

According to such a semiconductor integrated circuit device,
Since the bottom surface of the connection hole located at the lowermost stage is included in the first semiconductor region in the active region, the connection between the connection hole and the first semiconductor region is reliably performed. This has an advantage that a part thereof does not protrude into the element isolation region and a short circuit between the connection hole and the semiconductor substrate, which easily occurs in the element isolation region made of a silicon oxide film, and the like, does not occur.

Also, the upper surface of the connection hole located at the top is
Since the bit line is included in the bit line inclusion pattern formed symmetrically with respect to the center line of the bit line, the connection between the connection hole and the bit line is securely performed, and the bit including the inclusion pattern is also included. The line pattern can be formed symmetrically with respect to its center line, which makes the pattern less likely to become thick and thin in photolithography for forming bit lines, and can be easily adapted to fine processes. Has the advantage that it can be

Further, since the connection hole located at the uppermost stage is provided with a shift in a direction opposite to that of the second connection hole with respect to the connection hole located at the lowermost stage, the insulating property between the active regions is reduced. While securing the opening area of the second connection hole,
The requirement for miniaturization can be dealt with as described in the above (1).

(4) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), wherein the first connection hole is a single opening vertically opened with respect to the semiconductor substrate. An upper surface of the first connection hole, which is in contact with the bit line, and a bottom surface of the first connection hole, which is in contact with the first semiconductor region, are offset from the first semiconductor region in the horizontal direction of the semiconductor substrate. Have

According to such a semiconductor integrated circuit device,
In addition to the effect described in the above (1), the step of opening the first connection hole is simplified by making the first connection hole a single connection hole opened in a direction perpendicular to the semiconductor substrate. Can be

(5) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (4), wherein the element isolation region has a structure in which an insulator is embedded in a groove formed in the semiconductor substrate. And a silicon nitride film is formed on the surface of the element isolation region.

According to such a semiconductor integrated circuit device,
In addition to the effect described in the above (4), in addition to the connection between the first connection hole and the first semiconductor region, the short-circuit failure in which the first connection hole is connected to the semiconductor substrate occurs. Nothing.

That is, the first connection hole is a single connection hole opened in the vertical direction, and the top and bottom surfaces thereof are offset from the first semiconductor region in the horizontal direction of the semiconductor substrate. Therefore, a part of the bottom surface is formed in the element isolation region outside the first semiconductor region. However, the insulating layer in which the first connection hole is opened is usually a silicon oxide film, and the element isolation region is formed. In the case where the regions are made of the same material silicon oxide film, the etching for opening the connection holes is stopped immediately after the first semiconductor region is exposed so that the connection holes are not short-circuited with the semiconductor substrate. It is necessary to stop with just etch. However, in the present invention, the element isolation region is an element isolation region having a structure in which an insulator is embedded in a groove formed in a semiconductor substrate, and a silicon nitride film is formed on a surface of the element isolation region. Therefore, the silicon nitride film acts as an etching stopper at the time of opening the connection hole, and does not overetch. Thereby, the reliability of the semiconductor integrated circuit device can be improved.

(6) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (1), (2) or (3), wherein (a) an element is provided on the main surface of the semiconductor substrate. Forming an isolation region, forming a word line on a semiconductor substrate,
Forming a first and a second semiconductor region in the active region; (b) forming a first insulating layer covering the semiconductor substrate and the word line on the entire surface of the semiconductor substrate; Forming a lower-layer connection hole that becomes a part of the first connection hole in the insulating layer, and further forming a buried plug made of a conductive material in the lower-layer connection hole; (c) forming a second insulating layer over the entire surface of the semiconductor substrate; A first connection hole exposing a part of the buried plug at a position shifted from the upper layer of the lower connection hole in a horizontal direction of the semiconductor substrate and in a direction opposite to the second connection hole. And (d) forming a bit line having an inclusion pattern including the upper layer connection hole.

According to such a method of manufacturing a semiconductor integrated circuit device, the first insulating layer covering the semiconductor substrate and the word lines is formed on the entire surface of the semiconductor substrate, and the first insulating layer on the first semiconductor region is formed. A lower layer connection hole that becomes a part of the first connection hole is opened, and a buried plug made of a conductive material is further formed in the lower layer connection hole.
A first connection hole exposing a part of the embedded plug at a position shifted from the upper layer of the lower connection hole in a horizontal direction of the semiconductor substrate and in a direction opposite to the second connection hole. Since the upper layer connection hole which becomes a part of the semiconductor integrated circuit device is opened, the semiconductor integrated circuit device having the structure described in the above (1) to (3) can be easily manufactured.

(7) The method of manufacturing a semiconductor integrated circuit device according to the above (1), (4) or (5), wherein (a) the element is provided on the main surface of the semiconductor substrate. Forming an isolation region, forming a word line on a semiconductor substrate,
Forming a first and a second semiconductor region in the active region surrounded by the element isolation region; and (b) forming an insulating layer covering the semiconductor substrate and the word line, and forming the semiconductor layer directly above the first semiconductor region. A step of opening the first connection hole in the insulating layer at a position shifted in the direction opposite to the second connection hole in the horizontal direction of the substrate, (c) a bit having an inclusion pattern including the first connection hole Forming a line.

According to such a method of manufacturing a semiconductor integrated circuit device, the insulating layer covering the semiconductor substrate and the word line is formed, and the second insulating layer is formed in the horizontal direction of the semiconductor substrate from directly above the first semiconductor region. In order to open the first connection hole in the insulating layer at a position shifted in a direction opposite to the connection hole, the above (1),
A semiconductor integrated circuit device having the structure described in (4) or (5) can be manufactured.

[0046]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a top view showing an example of a layout of a main part of each constituent member constituting a DRAM according to an embodiment of the present invention with respect to a memory cell region. 2A shows a sectional view taken along the line IIa-IIa in FIG. 1, and FIG. 2B shows a sectional view taken along the line IIb-IIb in FIG. Note that, in the top view (FIG. 1), the storage electrode SN is omitted for easy understanding of the drawing.

The memory cell area of the DRAM according to the first embodiment includes a semiconductor substrate 1, a MOSFET for selecting a memory cell formed on the main surface of the semiconductor substrate 1, and a MOSFET for selecting.
It has a storage capacitor element for charge storage connected to the FET and a bit line BL.

The semiconductor substrate 1 is, for example, p ^- consists form of silicon (Si) single crystal, in its upper part, for example, a field insulation film 2a for element isolation formed of silicon dioxide (SiO ₂₎ is formed, also, On the upper part of the semiconductor substrate 1,
A p-well 3 is formed. For example, boron as a p-type impurity is introduced into the p-well 3.

The region of the semiconductor substrate 1 surrounded by the field insulating film 2a becomes the active region 2b. The active region 2b
Many are arranged in the memory cell region on the semiconductor substrate 1, and the word lines W
L is formed. Also, they are separated by the closest distance d between the active regions 2b.

One active region 2b has a symmetrical gull wing shape, and two selection MOSFs
ET is formed. The selection MOSFET is
Polycrystalline silicon film 5a and tungsten silicide (WSi ₂ ) film 5 formed on semiconductor substrate 1 via gate insulating film 4 formed on active region 2b of p well 3
a first semiconductor region 6 formed in the p-well 3 on both sides of the gate electrode 5 so as to be separated from each other
a and the second semiconductor region 6b.

The gate electrode 5 is connected to the word line WL of the DRAM.
The first and second semiconductor regions 6a and 6b are doped with, for example, an n-type impurity such as phosphorus or arsenic (As).

The semiconductor region 6a includes two selection MOSFs.
A channel region of the selection MOSFET is formed between the semiconductor regions 6a and 6b, which is shared by the ET. The gate insulating film 4 is made of, for example, SiO ₂ .

An upper surface and side surfaces of the gate electrode 5 (which is also a word line WL) are covered with an insulating film 7 made of, for example, SiO _2.
The semiconductor device is covered with a cap insulating film 7c made of, for example, silicon nitride and a side wall 7d via a and 7b. The insulating films 7a and 7b serve to prevent contamination of the film forming apparatus by the metal constituting the WSi ₂ film 5b when forming the cap insulating film 7c and the side wall 7d, and to provide thermal stress to the cap insulating film 7c and the side wall 7d. It is provided to alleviate the problem.

These cap insulating films 7c are made of, for example, B
It is covered with a first insulating film 8a made of PSG (Boro Phospho Silicate Glass). In the first insulating film 8a, the lower connection hole 9a of the first connection hole such that the first semiconductor region 6a in the upper layer of the semiconductor substrate 1 is exposed.
In addition, a lower connection hole 9b of the second connection hole is formed such that the semiconductor region 6b in the upper layer of the semiconductor substrate 1 is exposed. The cap insulating film 7c and the side wall 7
d can serve as an etching stopper when the connection holes 9a and 9b are opened in a self-aligned manner.

A plug 10a is formed in the lower connection hole 9a of the first connection hole, and a plug 10b is formed in the lower connection hole 9b of the second connection hole. Plug 10a, 1
Ob can be, for example, polycrystalline silicon into which an n-type impurity has been introduced. The plugs 10a, 10b
Has an action of relaxing the aspect ratio of the upper connection hole 11a of the first connection hole and the upper connection hole 11b of the second connection hole described below.

On the first insulating film 8a, for example, BPS
A second insulating film 8b made of G (Boro Phospho Silicate Glass) is formed, and a plug 10 is formed on the second insulating film 8b.
The upper connection hole 11a of the first connection hole where a is exposed and the upper connection hole 11b of the second connection hole where the plug 10b is exposed are formed.

The upper connection hole 11b of the second connection hole is opened directly above the plug 10b. However, the upper connection hole 11a of the first connection hole is not opened directly above the plug 10a but opened with an offset L. Is done. This offset L is taken in the direction opposite to the direction of the second connection hole, and is opened so that the connection hole comes to the center of the inclusion pattern DB of the bit line BL described later.

The bit line BL is formed on the second insulating film 8b. This bit line BL is made up of a polycrystalline silicon film 12 and a WSi ₂ film 13, and is electrically connected to the plug 10a via the upper connection hole 11a of the first connection hole.

The polycrystalline silicon film 12 and the second insulating film 8b
The polycrystalline silicon film 14 used as an etching mask when the upper connection hole 11a of the first connection hole is formed
Is left. This polycrystalline silicon film 14 is a film for increasing the etching selectivity at the time of forming the upper connection hole 11a of the first connection hole, and is made of, for example, low-resistance polycrystalline silicon and is also a part of the bit line BL.

The upper and side surfaces of the bit line BL are covered with a cap insulating film 16a made of, for example, SiO ₂ and side walls 16b via insulating films 15a and 15b. Further, the cap insulating film 16a and the side walls 16b are covered with the silicon nitride film 17. The silicon nitride film 17 is a film that functions as an etching stopper when removing the underlying insulating film after forming the storage capacitor 19 described later.

A storage capacitor 19 having a cylindrical crown shape is formed above the bit line BL. The storage capacitor 19 is made of low-resistance polycrystalline silicon,
b and a polycrystalline silicon film 2 a vertically set with respect to the semiconductor substrate 1.
0b, a capacitor insulating film 21 formed by depositing a SiO ₂ film on a silicon nitride film, for example, and a low-resistance polycrystalline silicon, which is electrically connected to a predetermined wiring. And the plate electrode 22 which is provided. Also, the polycrystalline silicon film 2
Polycrystalline silicon film 20c is formed in a part of the lower part of Oa. The polycrystalline silicon film 20c has a part of an etching mask left when opening a connection hole connecting the polycrystalline silicon film 20a and the plug 10b, and forms a part of the capacitor lower electrode 20. .

According to the DRAM of the first embodiment, the first
The upper connection hole 11a is formed with an offset L in the horizontal direction of the semiconductor substrate 1 from directly above the lower connection hole 9a of the first connection hole, and the direction of the offset L is determined by the connection hole of the storage capacitor 19. Since the direction is opposite to the direction of the certain second connection holes 9b and 11b, the closest distance d of the active region 2b can be a sufficient distance for electrical insulation of the active region 2b.
And the inclusion pattern D including the connection hole of the bit line BL.
B can be symmetric with respect to the center line of the bit line BL. As a result, a high-performance semiconductor integrated circuit device having no leak between elements is formed, and the bit line BL which is unlikely to be thickened or thinned in a pattern which tends to occur in high-definition lithography is formed.
And can meet the demand for further miniaturization.

As a comparison, the DR of the first embodiment
FIGS. 17 and 18 show an example of a layout in the case where the first connection holes are not provided in two stages as in AM.

FIG. 17 shows that the inclusion pattern DB is changed to the bit line B in consideration of miniaturization at the time of lithography of the bit line BL.
This is an example in which layout is performed with priority given to symmetry with respect to the center line of L. Second connection hole 9 which is a connection hole of storage capacitor 19
In order to secure the positions for opening b and 11b between the bit lines BL, it is necessary to make the angle of the gull wing shape of the active region 2c an acute angle. As a result, the closest distance d ₁ between the active regions 2c is reduced. Be shorter. This causes a problem that insulation between elements cannot be ensured.

On the other hand, FIG. 18 shows an example of a layout in which the angle of the gull wing shape of the active region 2d is made obtuse, with priority given to ensuring insulation between the elements. Although the closest distance d ₂ between the active region 2d may be secured, it is formed in the center line and symmetric connection hole inclusion patterns of the bit line BL from the need to ensure a position which opens the second connection hole 9b, and 11b It can not, must form part DB ₂ overhang as shown in FIG. This causes the distance between the bit lines BL to be short, causing an increase in the stray capacitance, which has various effects such as a decrease in the charge detection sensitivity of the DRAM. In addition, since the bit line BL is not symmetrical with respect to its center line, the pattern tends to be thin or thick during photolithography, which causes disconnection of the bit line BL or short-circuit between lines.

However, as described above, such a problem does not occur in the DRAM of the first embodiment.

Next, a method of manufacturing the DRAM will be described.
This will be described with reference to FIGS. 3A to FIG. 12A are cross-sectional views of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 3B is a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG. Show.

[0069] First, p ^- after forming a silicon oxide film and a silicon nitride film (not shown) on the surface of the semiconductor substrate 1 made of shape silicon single crystal, using a photoresist as a mask, to etch the silicon nitride film, a silicon this nitride By performing selective oxidation using the film as a mask, a field insulating film 2 a for element isolation is formed on the main surface of the semiconductor substrate 1. Further, an n-type impurity (for example, phosphorus (P)) is introduced into the formation region of the memory cell array of the semiconductor substrate 1 by ion implantation, and a thermal diffusion process is performed on the semiconductor substrate 1 to form a p-well 3 (FIG. 3).

The field insulating film 2a is a silicon oxide film, and its thickness is about 400 nm. At this time, a p-type impurity (for example, boron fluoride (BF ₂ )) is ion-implanted into the main surface of the active region 2b of the p-well 3 to perform a threshold voltage adjustment layer (not shown) of the memory cell selection MOSFET. ) May be formed.

Next, after the surface of the semiconductor substrate 1 is etched with a hydrofluoric acid solution, the surface of the semiconductor substrate 1 has a thickness of about 9 n.
The gate insulating film 4 of the m memory cell selecting MOSFET is formed by a thermal oxidation method, and a polycrystalline silicon film 5a in which P is introduced and a WSi ₂ film 5b are sequentially deposited on the entire surface of the semiconductor substrate 1. An insulating film 7a made of a silicon oxide film and a cap insulating film 7 made of a silicon nitride film
c is sequentially deposited, and thereafter, using a photoresist as a mask, the cap insulating film 7c, the insulating film 7a, and the WSi ₂ film 5b.
And the laminated film composed of polycrystalline silicon film 5a is sequentially etched, so that polycrystalline silicon film 5a and W
The gate electrode 5 of the memory cell selection MOSFET made of the Si ₂ film 5b is formed. Further, after removing the photoresist, the semiconductor substrate 1 is subjected to a thermal oxidation process to form an insulating film 7b on the side walls of the polycrystalline silicon film 5a and the WSi ₂ film 5b constituting the gate electrode 5 (FIG. 4). ).

Polycrystalline silicon film 5a and WSi ₂ film 5
b is formed by a CVD method, and the film thicknesses thereof can be, for example, 70 nm and 150 nm, respectively. The insulating film 7a and the cap insulating film 7c are formed by a CVD method, and these film thicknesses are, for example, respectively. It can be 10 nm and 200 nm.

Next, n-type impurities (for example, P) are ion-implanted into the main surface of the p-well 3 using the laminated film as a mask.
This n-type impurity is extended and diffused to form an n-type semiconductor region (source region, drain region) of the memory cell selection MOSFET. The n-type semiconductor region includes a first semiconductor region 6a located at the center of the active region 2b and second semiconductor regions 6b located at both ends of the active region 2b with the channel region of the memory cell selecting MOSFET interposed therebetween. It is divided into A plug 10a is later connected to the semiconductor region 6a, and a plug 10b is later connected to the semiconductor region 6b. Further, C on the semiconductor substrate 1
The silicon nitride film (not shown) deposited by the VD method is etched by anisotropic etching such as RIE (Reactive Ion Etching) to form a sidewall 7d on the side wall of the gate electrode 5 of the memory cell selection MOSFET. (FIG. 5).

The cap insulating film 7c on the gate electrode 5 of the memory cell selection MOSFET and the gate electrode 5
7d of side wall made of silicon nitride film
Is provided for electrically separating gate electrode 5 from a conductive layer formed thereover. In addition, the gate electrode 5
The upper insulating film 7a is provided to prevent the gate electrode 5 from contacting the cap insulating film 7c located thereon, and the insulating film 7b does not allow the gate electrode 5 to contact the sidewall 7d made of a silicon nitride film. Provided for.

After forming the side wall 7d, p
By implanting arsenic (As) ions into the main surface of the well 3 at a higher concentration than the n-type impurity (P), the source region and the drain region of the memory cell selecting MOSFET are LD
It may have a D (Lightly Doped Drain) structure.

Next, after a first insulating film 8a made of a silicon oxide film is deposited on the semiconductor substrate 1 by a CVD method, for example, chemical mechanical polishing (Chemical Mechanical Polishing) is performed.
A first semiconductor region 6 planarized by a CMP) method.
The lower connection hole 9a of the first connection hole is opened on the first connection hole 9a, and the lower connection hole 9b of the second connection hole is opened on the second semiconductor region 6b (FIG. 6).

At this time, an opening may be formed using the polycrystalline silicon film as a hard mask.

Since the lower connection holes 9a and 9b of the first and second connection holes are simultaneously opened by the same mask, mask misalignment occurring when the connection holes are separately opened does not occur, and the accuracy is reduced. You can open well.

Next, a polycrystalline silicon film into which P is introduced (not shown) is formed on the entire surface of the semiconductor substrate 1, and the polycrystalline silicon film is etched back using a technique such as chemical mechanical polishing or plasma etching. Plugs 10a and 10b are formed in the lower connection hole 9a of the first connection hole and the lower connection hole 9b of the second connection hole (FIG. 7).

Next, a second insulating film 8b made of a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method.
A polycrystalline silicon film 14 into which P has been introduced is deposited on the semiconductor substrate 1. Further, the polycrystalline silicon film 14 and the second insulating film 8b are sequentially etched using the photoresist as a mask, thereby forming the upper connection hole 11a of the first connection hole connected to the plug 10a. At this time, the upper connection hole 11a of the first connection hole is formed with an offset L from a position directly above the plug 10a (FIG. 8).

Next, after removing the photoresist,
P-doped polycrystalline silicon film 12 on semiconductor substrate 1
And a WSi ₂ film 13 are deposited, and an insulating film 15a and a cap insulating film 16a are sequentially deposited. Then, using the photoresist as a mask, the cap insulating film 16a, the insulating film 15a, the WSi ₂ film 13, and the polycrystalline silicon film are formed. The laminated film made of the polycrystalline silicon film 12 and the polycrystalline silicon film 14 are sequentially etched.

Thus, a bit line BL composed of the polycrystalline silicon film 14, the polycrystalline silicon film 12, and the WSi ₂ film 13 is formed (FIG. 9).

Next, after removing the photoresist,
By subjecting the semiconductor substrate 1 to a thermal oxidation process, an insulating film 15b is formed on the side walls of the polycrystalline silicon film 14, the polycrystalline silicon film 12, and the WSi ₂ film 13 constituting the bit line BL. Is etched by anisotropic etching such as RIE to form a sidewall 16b on the side wall of the bit line BL. Thereafter, a silicon nitride film 17 is deposited on the semiconductor substrate 1 by a CVD method (FIG. 10).

Next, after an interlayer insulating film 30 made of a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, the surface of the interlayer insulating film 30 is flattened by, for example, the CMP method. A polycrystalline silicon film 20c having P introduced therein is deposited by a CVD method.

Further, the polycrystalline silicon film 20c, the interlayer insulating film 30, and the silicon nitride film 17 are sequentially etched by using a photoresist as a mask, thereby forming the plug 10b.
A connection hole to be the upper connection hole 11b of the second connection hole is formed thereon (FIG. 11).

In the formation of the connection hole, since the plug 10b is formed in advance, the aspect ratio of the connection hole is small, the opening can be opened with a sufficient margin of opening accuracy, and it is possible to cope with further miniaturization of the semiconductor integrated circuit device. It is possible to do.

Next, after removing the photoresist,
P-doped polycrystalline silicon film 20 on semiconductor substrate 1
a and a silicon oxide film (not shown) are sequentially deposited by a CVD method, and using a photoresist as a mask, the silicon oxide film, the polycrystalline silicon film 20a and the polycrystalline silicon film 2 are formed.
0c is sequentially etched. Further, after removing the photoresist, a polycrystalline silicon film (not shown) is deposited on the entire surface of the semiconductor substrate 1 and anisotropically etched to form a polycrystalline silicon film 20 on the side surface of the silicon oxide film.
Then, the capacitor lower electrode 20 is formed. Thereafter, the silicon oxide film and the interlayer insulating film 30 are removed by, for example, wet etching using a hydrofluoric acid solution (FIG. 12).

Finally, a silicon nitride film (not shown) is
A silicon oxide film is formed on the surface of the silicon nitride film by depositing on the semiconductor substrate 1 by the VD method and subsequently performing an oxidation process, and a capacitor insulating film 21 made of the silicon oxide film and the silicon nitride film is formed. Lower electrode 20
Formed on the surface of Thereafter, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 1 by a CVD method, and the polycrystalline silicon film is etched using a photoresist as a mask to form a plate electrode 22. And the DRAM shown in FIG. 2 is almost completed.

Note that a known technique can be used for the metal wiring and the like, and a description thereof will be omitted.

According to the above-described DRAM manufacturing method, the DRAM of the first embodiment can be easily formed, and since the plugs 10a and 10b are formed, the aspect ratio of the connection hole is reduced. The reliability of the etching process can be improved.

(Embodiment 2) FIG. 13 is a top view showing an example of a layout of a main part of each constituent member constituting a DRAM according to another embodiment of the present invention with respect to a memory cell region. FIG. 14A shows XIVa in FIG.
FIG. 14B is a cross-sectional view of FIG.
The XIVb-XIVb sectional view is shown. Note that, in the top view (FIG. 13), the storage electrode SN is omitted for easy understanding of the drawing.

The DRAM according to the second embodiment has the same structure as that of the first embodiment except for the element isolation region and the first connection hole.
Since it has a configuration similar to that of the RAM, only different portions will be described below, and description of the same portions will be omitted.

The DRAM of the second embodiment has a gull-wing shaped active region 2b similar to that of the first embodiment, and the structure of the selection MOSFET is also the same.

However, in the element isolation region of the DRAM of the second embodiment, a groove structure 40 is formed in the semiconductor substrate 1 instead of the field insulating film formed by using the LOCOS method. It has a structure in which an insulator 41 made of a film is embedded. Also,
On the insulator 41, an insulating film 42 made of, for example, a silicon nitride film is formed.

Unlike the first embodiment, the first connection hole 43 connected to the first semiconductor region 6a of the selection MOSFET is formed of a single connection hole. It is connected to the region 6a and formed so as to protrude into the element isolation region. That is, the first connection hole 43 is formed right above the first semiconductor region 6a in a state shifted from the position, that is, in a state having an offset L. The direction of this displacement is opposite to the direction of the second connection hole 45, as in the first embodiment.

According to such a DRAM, as described in the first embodiment, since the first connection hole 43 is opened so as to be shifted from directly above the first semiconductor region 6a, the active region 2b is opened. A second connection for connecting the storage capacitor 19 while making the closest distance d between them sufficient to ensure insulation between the elements, making the bit line pattern symmetrical with respect to the center line thereof, A position for opening the hole can be secured.

Further, in the DRAM of the second embodiment,
Since the first connection hole 43 is a single connection hole, the opening step is one step, and the steps can be simplified.

Next, a method of manufacturing the DRAM will be described with reference to FIGS. FIG. 15 and FIG.
6A shows a cross-sectional view of a portion corresponding to the XIVa-XIVa cross section in FIG. 13, and FIG. 6B shows a XIVb in FIG.
FIG. 4 shows a cross-sectional view of a portion corresponding to a −XIVb cross section.

First, as shown in FIG.
A groove structure 40 is formed on the main surface of the substrate by using a known etching technique using a silicon nitride film as a mask, for example. After that, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, and an insulator 41 is embedded in the trench structure 40. Thereafter, the surface of the semiconductor substrate 1 is flattened by, for example, etch back by a CMP method. Further, an insulating film 42 made of, for example, a silicon nitride film is formed on the insulator 41. The insulating film 42 functions as an etch stopper when the first connection hole 43 is opened later.

Next, on the main surface of the semiconductor substrate 1, the MO for selection is
An SFET is formed, and its manufacturing method is described in Embodiment 1.
Therefore, the description is omitted.

Next, as shown in FIG.
An insulating film 46 made of, for example, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 on which the FET is formed, and a first connection hole 43 is opened. At this time, the polycrystalline silicon film 47 can be used as a hard mask. When the insulating film 46 made of the silicon oxide film is etched, the stop point of the etching is the insulating film 42 made of the silicon nitride film on the surface of the silicon wafer or the element isolation region.
Both are materials having a high etching selectivity with the silicon oxide film, and are not over-etched. As a result,
A process margin in the etching process can be expected, and a highly reliable DRAM can be manufactured.

Next, a bit line BL and a storage capacitor 19 are formed. The manufacturing method is the same as that of the first embodiment, and the description is omitted.

According to such a method of manufacturing a DRAM, the DRAM can be easily manufactured and the process of opening the first connection hole 43 can be stabilized. Having.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, the case where the active region has a gull-wing shape has been described, but the active region may be a linear active region.

In the first embodiment, an example of a field insulating film formed by the LOCOS method has been described as an element isolation region. However, an element isolation region having a trench structure may be used.

Further, in the second embodiment, the example in which the element isolation region having the trench structure is used as the element isolation region has been described.
A field insulating film formed by the OS method may be used.

[0108]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) At the same time as securing the minimum element separation distance between adjacent active regions, the first connection is made to the inclusion pattern of a bit line having a symmetrical pattern with respect to its center line, that is, having no extraction pad. Contains a hole, and
An opening position of the second connection hole for connecting the storage capacitor can be secured.

(2) A minimum element separation distance between adjacent active regions is ensured to maintain insulation between elements, and constriction does not occur at the time of lithography of bit lines, and parasitic capacitance between adjacent bit lines increases. Can be prevented, and a region for forming the second connection hole can be secured.

[Brief description of the drawings]

FIG. 1 is a top view showing an example of a layout of a main part of a constituent member constituting a DRAM according to an embodiment of the present invention with respect to a memory cell region.

2A is a sectional view taken along a line IIa-IIa in FIG. 1, and FIG. 2B is a sectional view taken along a line IIb-IIb in FIG.

3A and 3B are cross-sectional views of a main part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps, and FIG.
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIG. 4 is a cross-sectional view of a main part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIGS. 5A and 5B are cross-sectional views of an essential part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIG. 6 is a cross-sectional view of a principal part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIGS. 7A and 7B are cross-sectional views of a main part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

8A and 8B are cross-sectional views of a main part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps, and FIG.
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIGS. 9A and 9B are cross-sectional views of a principal part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIGS. 10A and 10B are main-portion cross-sectional views illustrating an example of a method for manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

11A and 11B are cross-sectional views of a principal part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps;
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

12A and 12B are cross-sectional views of a main part showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps, and FIG.
1 shows a cross-sectional view of a portion corresponding to the IIa-IIa cross section in FIG. 1, and FIG. 2B shows a cross-sectional view of a portion corresponding to the IIb-IIb cross section in FIG.

FIG. 13 is a top view showing an example of a layout of a main part of a constituent member constituting a DRAM according to another embodiment of the present invention with respect to a memory cell region.

14A is a cross-sectional view taken along the line XIVa-XIVa in FIG. 13, and FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb in FIG.

FIG. 15 is a fragmentary cross-sectional view showing one example of a method of manufacturing a DRAM according to another embodiment of the present invention in the order of steps;
13A is a cross-sectional view of a portion corresponding to the XIVa-XIVa cross section in FIG. 13, and FIG. 13B is a cross-sectional view of XIVb-XI in FIG.
FIG. 3 shows a cross-sectional view of a portion corresponding to a Vb cross section.

FIG. 16 is a fragmentary cross-sectional view showing one example of a method of manufacturing a DRAM according to another embodiment of the present invention in the order of steps;
13A is a cross-sectional view of a portion corresponding to the XIVa-XIVa cross section in FIG. 13, and FIG. 13B is a cross-sectional view of XIVb-XI in FIG.
FIG. 3 shows a cross-sectional view of a portion corresponding to a Vb cross section.

FIG. 17 is a comparative layout diagram in a case where priority is given to making the inclusion pattern symmetrical to the center line of the bit line in consideration of miniaturization at the time of lithography of the bit line.

FIG. 18 gives priority to ensuring insulation between elements;
FIG. 7 is a comparative layout diagram when the angle of the gull wing shape of the active region is made obtuse.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2a field insulating film 2b active region 2c active region 2d active region 3 p well 4 gate insulating film 5 gate electrode 5a polycrystalline silicon film 5b WSi ₂ film 6a first semiconductor region 6b second semiconductor region 7a insulating film 7b Insulating film 7c Cap insulating film 7d Sidewall 8a First insulating film 8b Second insulating film 9a Lower connecting hole of first connecting hole 9b Lower connecting hole of second connecting hole 10a Plug 10b Plug 11a First Upper connection hole of connection hole 11b Upper connection hole of second connection hole 12 Polycrystalline silicon film 13 WSi ₂ film 14 Polycrystalline silicon film 15a Insulating film 15b Insulating film 16a Cap insulating film 16b Sidewall 17 Silicon nitride film 19 Storage capacitance Reference Signs List 20 capacitor lower electrode 20a polycrystalline silicon film 20b polycrystalline silicon film 20c Polycrystalline silicon film 21 Capacitor insulating film 22 Plate electrode 30 Interlayer insulating film 40 Groove structure 41 Insulator 42 Insulating film 43 First connection hole 44 Bottom 45 Second connection hole 46 Insulating film 47 Polycrystalline silicon film BL Bit line DB ₂ overhang portion DB inclusion pattern L offset SN storage electrode WL word line d ₁ closest distance d ₂ closest distance d closest distance

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Mitsue Amemiya 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Inside the corporation

Claims (7)

[Claims] An element isolation region formed on a main surface of a semiconductor substrate; a first semiconductor region formed at a central portion of a symmetrical active region surrounded by the element isolation region; It functions as a word line formed via a gate insulating film over a second semiconductor region formed at both ends and a channel region located between the first semiconductor region and the second semiconductor region. A gate electrode;
MISFETs for selection having common semiconductor regions
A bit line connected to the first semiconductor region through a first connection hole opened in the insulating film formed on the semiconductor substrate and the gate electrode; and a bit line opened in the insulating film. And a storage capacitor connected to the second semiconductor region via the second connection hole in the memory cell region.
M, wherein an upper surface of a first connection hole that is in contact with the bit line is formed by the first connection hole.
A semiconductor region having an offset in a horizontal direction of the semiconductor substrate with respect to the semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein the first connection holes are connected in tandem with each other and include a plurality of connection holes opened in a direction perpendicular to the semiconductor substrate. A semiconductor integrated circuit device characterized by the above-mentioned. 3. The semiconductor integrated circuit device according to claim 2, wherein a bottom surface of a lowermost connection hole of the plurality of connection holes is included in the first semiconductor region in the active region. The upper surface of the connection hole positioned at the top is included in the bit line inclusion pattern formed symmetrically with respect to the center line of the bit line, and the connection hole positioned at the top is A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is provided so as to be displaced in a direction opposite to the second connection hole with respect to a connection hole located at a lowermost stage. 4. The semiconductor integrated circuit device according to claim 1, wherein said first connection hole comprises a single connection hole opened in a direction perpendicular to said semiconductor substrate, and said first connection hole is formed in said bit line. An upper surface of the first connection hole in contact with the first connection hole and a bottom surface of the first connection hole in contact with the first semiconductor region have an offset in the horizontal direction of the semiconductor substrate with respect to the first semiconductor region. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein said element isolation region is an element isolation region having a structure in which an insulator is embedded in a groove formed in said semiconductor substrate. A semiconductor integrated circuit device, wherein a silicon nitride film is formed on a surface of an element isolation region. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein: (a) forming an element isolation region on a main surface of the semiconductor substrate;
Forming the word line on the semiconductor substrate and further forming the first and second semiconductor regions in the active region; and (b) covering the entire surface of the semiconductor substrate with the semiconductor substrate and the word line. Forming an insulating layer, opening a lower connecting hole that becomes a part of the first connecting hole in the first insulating layer on the first semiconductor region, and further forming a conductive material in the lower connecting hole. (C) forming a second insulating layer on the entire surface of the semiconductor substrate;
A position shifted from the upper layer of the lower connection hole in the horizontal direction of the semiconductor substrate and in a direction opposite to the second connection hole,
Opening an upper layer connection hole that becomes a part of the first connection hole exposing a part of the buried plug; and (d) forming the bit line having an inclusion pattern including the upper layer connection hole. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein: (a) forming an element isolation region on a main surface of the semiconductor substrate;
The word line is formed on the semiconductor substrate, and the first and second lines are formed in an active region surrounded by the element isolation region.
(B) forming an insulating layer covering the semiconductor substrate and the word line, and forming the second connection in a horizontal direction of the semiconductor substrate from directly above the first semiconductor region; A step of opening the first connection hole in the insulating layer at a position shifted in a direction opposite to the hole, and (c) a step of forming the bit line having an inclusion pattern including the first connection hole. A method for manufacturing a semiconductor integrated circuit device, comprising: