KR100365754B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR100365754B1 KR100365754B1 KR1020000086600A KR20000086600A KR100365754B1 KR 100365754 B1 KR100365754 B1 KR 100365754B1 KR 1020000086600 A KR1020000086600 A KR 1020000086600A KR 20000086600 A KR20000086600 A KR 20000086600A KR 100365754 B1 KR100365754 B1 KR 100365754B1
- Authority
- KR
- South Korea
- Prior art keywords
- interlayer insulating
- bit line
- forming
- plug
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000003860 storage Methods 0.000 description 13
- 239000000126 substance Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
반도체기판상에 다수의 워드라인을 형성하는 단계, 상기 워드라인상에 제 1 층간절연막을 형성하는 단계, I형 마스크를 이용하여 상기 제 1 층간절연막을 선택적으로 식각하여 플러그영역을 노출시키는 단계, 상기 노출된 플러그영역에 매립되는 폴리실리콘플러그를 형성하는 단계, 상기 폴리실리콘플러그상에 제 2 층간절연막을 형성하는 단계, 및 타원형 마스크를 이용하여 상기 제 2 층간절연막을 선택적으로 식각하여 비트라인콘택 영역을 노출시키는 단계를 포함하여 이루어진다.Forming a plurality of word lines on the semiconductor substrate, forming a first interlayer insulating film on the word lines, selectively etching the first interlayer insulating film using an I-type mask to expose a plug region; Forming a polysilicon plug embedded in the exposed plug region, forming a second interlayer insulating film on the polysilicon plug, and selectively etching the second interlayer insulating film using an elliptical mask to form a bit line contact Exposing the area.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 플러그간 브릿지를 방지하도록 한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing bridges between plugs.
통상적으로, 비트라인콘택(Bitline contact)과 스토리지노드콘택(Storagenode contact)을 형성하기 위하여 디자인룰(Design rule)에 해당하는 스몰 콘택(Small contact)을 정의해야 하기 때문에, 해상 능력에 있어서 콘택의 경우는 요구되는 해상 능력을 얻기가 힘들뿐만 아니라 웨이퍼내에서의 균일도(Uniformity)를 확보하는 것도 어렵다.In general, since a small contact corresponding to a design rule must be defined in order to form a bitline contact and a storage node contact, a contact in terms of resolution capability is required. Not only is it difficult to obtain the required resolution capability, but it is also difficult to ensure uniformity in the wafer.
도 1은 종래기술에 따른 스토리지노드 콘택과 비트라인 콘택이 형성될 영역을 도시한 평면도이고, 도 2는 도 1의 X-X'선에 따른 단면도이다.1 is a plan view illustrating a region where a storage node contact and a bit line contact are to be formed according to the prior art, and FIG. 2 is a cross-sectional view taken along the line X-X 'of FIG.
도 1 및 도 2를 참조하면, 종래기술의 반도체 소자의 제조 방법은 반도체기판(11)에 다수의 워드라인(12)을 형성하고 워드라인(12)을 포함한 전면에 제 1 층간절연막(13)을 형성한 후, T형 마스크(100)를 이용하여 제 1 층간절연막(13)을 식각하여 후속 폴리실리콘플러그 영역을 노출시킨다. 이 때, T형 마스크를 이용하므로 이웃한 셀의 비트라인콘택 부분과의 간격이 좁아진다.1 and 2, a method of manufacturing a semiconductor device according to the related art includes forming a plurality of word lines 12 on a semiconductor substrate 11 and forming a first interlayer insulating layer 13 on a front surface including the word lines 12. After forming, the first interlayer insulating layer 13 is etched using the T-type mask 100 to expose the subsequent polysilicon plug region. At this time, since the T-type mask is used, the interval between the bit line contact portions of neighboring cells is narrowed.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 증착하고 화학적기계적연마나 에치백을 실시하여 워드라인(12) 사이의 반도체기판(11)에 접합되는 폴리실리콘플러그(14)를 형성한다.Subsequently, polysilicon is deposited on the entire surface including the contact hole, and chemical mechanical polishing or etch back is formed to form the polysilicon plug 14 bonded to the semiconductor substrate 11 between the word lines 12.
이 때, 폴리실리콘플러그(13)는 워드라인(12)에 의해 서로 분리되는 비트라인콘택용 폴리실리콘플러그와 스토리지노드콘택용 폴리실리콘플러그로 구분된다.At this time, the polysilicon plug 13 is divided into a polysilicon plug for a bit line contact and a polysilicon plug for a storage node contact separated from each other by a word line 12.
계속해서, 폴리실리콘플러그(14)를 포함한 전면에 제 2 층간절연막(15)을 형성한 후 평탄화한 다음, 홀형(Hole type) 마스크를 이용하여 제 2 층간절연막(15)을 식각하여 비트라인콘택(15a) 부분을 노출시킨다.Subsequently, the second interlayer insulating film 15 is formed on the entire surface including the polysilicon plug 14, and then planarized. Then, the second interlayer insulating film 15 is etched using a hole type mask to etch the bit line contact. Part 15a is exposed.
이 때, 비트라인콘택(15a) 부분은 홀(Hole) 형태이며, 비트라인 콘택(15a)부분에 비해 스토리지노드 콘택(15b) 부분에 노출되는 폴리실리콘플러그(13)의 길이가 서로 다르되, 비트라인 콘택(15a) 부분이 더 길다.In this case, the bit line contact 15a portion has a hole shape, and the length of the polysilicon plug 13 exposed to the storage node contact 15b portion is different from that of the bit line contact 15a portion. The bit line contact 15a portion is longer.
후속 공정으로 노출된 폴리실리콘 플러그(13)에 접속되는 비트라인콘택(15a) 및 스토리지노드 콘택을 형성한후, 비트라인(16) 및 스토리지노드를 형성한다.After forming the bit line contact 15a and the storage node contact connected to the exposed polysilicon plug 13 in a subsequent process, the bit line 16 and the storage node are formed.
상술한 종래기술은, 폴리실리콘플러그 영역을 형성하기 위한 T형 마스크를 이용한 노광 공정은 인접한 폴리실리콘 플러그간 간격(A)이 좁아서 활성영역과의 넓은 접합 부위 확보를 위한 DICD 제어가 제한적이다.In the above-described prior art, in the exposure process using a T-type mask for forming the polysilicon plug region, the distance A between adjacent polysilicon plugs is narrow, so that DICD control for securing a wide junction with the active region is limited.
만약, 활성영역과의 넓은 접합 면적 형성을 위해 T형 폴리실리콘 플러그의 접합 부분의 DICD를 확대시키면, 비트라인콘택 부분과 인접한 스토리지노드콘택 부분과의 간격이 매우 감소되어 노광 공정이 어려울 뿐만 아니라, 후속 폴리실리콘 플러그의 화학적기계적연마 공정에서의 폴리실리콘 브릿지를 유발할 수 있는 문제점이 있다.If the DICD of the junction portion of the T-type polysilicon plug is enlarged to form a large junction area with the active region, the distance between the bit line contact portion and the storage node contact portion adjacent to the bit line contact portion is greatly reduced and the exposure process is difficult. There is a problem that can lead to polysilicon bridges in the chemical mechanical polishing process of subsequent polysilicon plugs.
한편, 실제로 DICD가 매우 좁게 결정된 겨우 후속 세정 공정 등에 의해 브릿지를 유발하며, 인접한 폴리실리콘 플러그간의 브릿지를 방지하기 위해 노광 공정의 DICD(Develop Inspect Critical Dimension)를 작게하는데 이 경우 활성영역과의 접합 면적 축소로 저항이 증가하는 문제점이 있다.On the other hand, when DICD is very narrowly determined, the bridge is caused by a subsequent cleaning process and the like. In order to prevent the bridge between adjacent polysilicon plugs, the DICD (Develop Inspect Critical Dimension) of the exposure process is reduced. There is a problem that resistance increases due to shrinkage.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 폴리실리콘 플러그 영역을 형성하기 위한 노광 공정의 마진을 확보하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for securing a margin of an exposure process for forming a polysilicon plug region.
도 1은 종래기술에 따른 반도체 소자의 평면도,1 is a plan view of a semiconductor device according to the prior art,
도 2는 도 1의 X-X'선에 따른 단면도,2 is a cross-sectional view taken along the line X-X 'of FIG.
도 3은 본 발명의 실시예에 따른 반도체 소자의 평면도,3 is a plan view of a semiconductor device according to an embodiment of the present invention;
도 4는 도 3의 Y-Y'선에 따른 단면도.4 is a cross-sectional view taken along the line Y-Y 'of FIG.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
22 : 워드라인 25a : 비트라인 콘택22: word line 25a: bit line contact
25b : 스토리지노드 콘택 26 : 비트라인25b: Storage node contact 26: Bit line
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체기판상에 다수의 워드라인을 형성하는 단계, 상기 워드라인상에 제 1 층간절연막을 형성하는 단계, I형 마스크를 이용하여 상기 제 1 층간절연막을 선택적으로 식각하여 플러그영역을 노출시키는 단계, 상기 노출된 플러그영역에 매립되는 폴리실리콘플러그를 형성하는 단계, 상기 폴리실리콘플러그상에 제 2 층간절연막을 형성하는 단계, 및 타원형 마스크를 이용하여 상기 제 2 층간절연막을 선택적으로 식각하여 비트라인콘택 영역을 노출시키는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of word lines on a semiconductor substrate, forming a first interlayer insulating film on the word line, using the I-type mask Selectively etching a first interlayer insulating film to expose a plug region, forming a polysilicon plug embedded in the exposed plug region, forming a second interlayer insulating film on the polysilicon plug, and an elliptical mask And selectively etching the second interlayer dielectric layer to expose the bit line contact region.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3은 본 발명의 실시예에 따른 비트라인콘택 및 스토리지노드콘택의 평면도이고, 도 4는 도 3의 Y-Y'선에 따른 단면도이다.3 is a plan view of a bit line contact and a storage node contact according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line YY ′ of FIG. 3.
도 3에 도시된 바와 같이, 반도체기판(21) 상부에 다수의 워드라인(22)을 형성하고 워드라인(22)상에 제 1 층간절연막(23)을 형성한 후, I 형 마스크(200)를 이용하여 제 1 층간절연막(23)을 식각하여 폴리실리콘 플러그 영역을 노출시킨다.As shown in FIG. 3, after forming a plurality of word lines 22 on the semiconductor substrate 21 and forming a first interlayer insulating layer 23 on the word lines 22, the I-type mask 200 is formed. The polysilicon plug region is exposed by etching the first interlayer insulating layer 23 by using a.
이 때, 노출되는 폴리실리콘플러그 영역은 활성영역과 동일한 형태의 I형태로 동일 위치에서 노출된다.In this case, the exposed polysilicon plug region is exposed at the same position in an I shape having the same shape as the active region.
이와 같이, I형 마스크를 이용하면 이웃한 셀의 후속 비트라인콘택 부분과의 간격이 넓어지고, 워드라인(22) 사이의 활성영역에 접하는 폴리실리콘플러그의 접촉면적을 증가시킨다.As such, the use of an I-type mask widens the distance between subsequent bit line contact portions of neighboring cells and increases the contact area of the polysilicon plug in contact with the active region between the word lines 22.
계속해서, 전면에 폴리실리콘을 증착한 후, 화학적기계적연마나 에치백을 실시하여 반도체기판(21)에 접합되는 폴리실리콘 플러그(24)를 형성한다. 이 때, 포리실리콘플러그(24)는 서로 분리된 비트라인콘택용 폴리실리콘플러그(24)와 스토리지노드콘택용 폴리실리콘플러그이다.Subsequently, polysilicon is deposited on the entire surface, followed by chemical mechanical polishing or etching back to form a polysilicon plug 24 bonded to the semiconductor substrate 21. At this time, the polysilicon plug 24 is a polysilicon plug 24 for a bit line contact and a polysilicon plug for a storage node contact separated from each other.
계속해서, 폴리실리콘플러그(24)를 포함한 전면에 제 2 층간절연막(25)을 형성한 후 평탄화한 다음, 타원형 마스크를 이용하여 제 2 층간절연막(25)을 식각하여 타원형태로 노출되는 비트라인콘택(25a)을 형성한다. 이 때, 비트라인콘택(25a) 부분은 폴리실리콘플러그(24)의 일측에 소정 폭 오버랩되며 폴리실리콘플러그(24)의 측면부분의 제 2 층간절연막(25) 및 제 1 층간절연막(23)의 소정 부분도 함께 식각되어 비트라인콘택(25a) 부분과 폴리실리콘플러그(24)의 접합 면적이 증가한다.Subsequently, the second interlayer insulating film 25 is formed on the entire surface including the polysilicon plug 24, and then planarized. Then, the second interlayer insulating film 25 is etched using an elliptical mask to expose the bit line in an elliptical shape. The contact 25a is formed. At this time, a portion of the bit line contact 25a overlaps a predetermined width of one side of the polysilicon plug 24, and a portion of the second interlayer insulating film 25 and the first interlayer insulating film 23 of the side surface of the polysilicon plug 24 are formed. The predetermined portion is also etched together to increase the junction area between the bit line contact 25a portion and the polysilicon plug 24.
이러한 후속 비트라인폭을 벗어나는 비트라인콘택(25a) 부분이 비트라인 건식 식각시 드러나게 되지만, 후속 층간절연막 증착 및 평탄화 공정을 통해 다시 감추어지고 후속 공정에서도 다시 오픈되는 경우가 발생되지 않으므로 전혀 영향을 주지 않는다.A portion of the bit line contact 25a beyond this subsequent bit line width is exposed during the dry etching of the bit line, but it is not hidden because it is hidden again through the subsequent interlayer insulating film deposition and planarization process and is not opened again in the subsequent process. Do not.
또한, 이웃한 폴리실리콘플러그와의 간격(A')이 넓어지므로 활성영역과의 넓은 접합 부위 확보를 위한 DICD 제어가 용이하다.In addition, since the distance (A ') with the neighboring polysilicon plug is widened, it is easy to control the DICD for securing a wide junction with the active area.
후속 공정으로 노출된 폴리실리콘 플러그(24)에 접속되는 비트라인콘택(25a) 및 스토리지노드 콘택을 형성한후, 비트라인(26) 및 스토리지노드를 형성한다.A bit line contact 25a and a storage node contact are formed to be connected to the exposed polysilicon plug 24 in a subsequent process, and then the bit line 26 and the storage node are formed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체 소자의 제조 방법은 T형 마스크대신 I형 마스크를 이용하여 폴리실리콘플러그의 노광 공정을 진행하므로써 이웃한 스토리지노드 콘택간 브릿지를 방지할 수 있는 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the effect of preventing the bridge between neighboring storage node contacts by performing the exposure process of the polysilicon plug using the I-type mask instead of the T-type mask.
또한, 비트라인콘택과 폴리실리콘플러그간의 접합면적을 증가시켜 저항을 감소시킬 수 있는 효과가 있다.In addition, the resistance can be reduced by increasing the junction area between the bit line contact and the polysilicon plug.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086600A KR100365754B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086600A KR100365754B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020058493A KR20020058493A (en) | 2002-07-12 |
| KR100365754B1 true KR100365754B1 (en) | 2002-12-26 |
Family
ID=27689589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000086600A KR100365754B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100365754B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1084091A (en) * | 1996-09-09 | 1998-03-31 | Hitachi Ltd | Semiconductor integrated circuit and its manufacture |
| JPH10189899A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Semiconductor storage device and its manufacture |
| JPH1145982A (en) * | 1997-07-28 | 1999-02-16 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| KR20010060041A (en) * | 1999-12-31 | 2001-07-06 | 박종섭 | A method for forming a bit line of a semiconductor device |
-
2000
- 2000-12-30 KR KR1020000086600A patent/KR100365754B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1084091A (en) * | 1996-09-09 | 1998-03-31 | Hitachi Ltd | Semiconductor integrated circuit and its manufacture |
| JPH10189899A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Semiconductor storage device and its manufacture |
| JPH1145982A (en) * | 1997-07-28 | 1999-02-16 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| KR20010060041A (en) * | 1999-12-31 | 2001-07-06 | 박종섭 | A method for forming a bit line of a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020058493A (en) | 2002-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100471410B1 (en) | Bit line contact formation method of semiconductor device | |
| KR100298458B1 (en) | Method for forming a electrode line of a semiconductor device | |
| KR100365754B1 (en) | Method for fabricating semiconductor device | |
| KR100368321B1 (en) | Method of manufacturing a semiconductor device | |
| KR100351897B1 (en) | Method for fabricating semiconductor device | |
| KR100294696B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100881411B1 (en) | Method for manufacturing merged dram in logic device | |
| KR100267773B1 (en) | Method for fabricating semiconductor device | |
| KR100363701B1 (en) | Method for Forming the Bit line contact of Semiconductor Device | |
| KR100300063B1 (en) | Manufacturing method for semiconductor memory | |
| KR100345066B1 (en) | Manufacturing method of SRAM element | |
| KR100402935B1 (en) | Method for manufacturing semiconductor device | |
| KR100454627B1 (en) | Method for manufacturing contact hole of semiconductor device | |
| KR100277883B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100942981B1 (en) | Method for fabricating semiconductor device | |
| KR100721186B1 (en) | Method for manufacturing semiconductor device | |
| KR0172778B1 (en) | Method of manufacturing semiconductor device | |
| KR940000312B1 (en) | Sram having a resistance resistor and fabricating method thereof | |
| KR100252887B1 (en) | Method for fabricating semiconductor device | |
| KR100244261B1 (en) | Plug forming method in semiconductor device | |
| KR20040072269A (en) | Method for forming dual storage node contact plug | |
| KR20010060441A (en) | High density semiconductor memory device and method for manufacturing thereof | |
| KR20010063078A (en) | Method for manufacturing of capacitor | |
| KR20010039149A (en) | Method of forming a conductive layer pattern in a semiconductor device | |
| KR20010077100A (en) | Method for forming self aligned via contact of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091126 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |