KR100300063B1 - Manufacturing method for semiconductor memory - Google Patents
Manufacturing method for semiconductor memory Download PDFInfo
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- KR100300063B1 KR100300063B1 KR1019980063508A KR19980063508A KR100300063B1 KR 100300063 B1 KR100300063 B1 KR 100300063B1 KR 1019980063508 A KR1019980063508 A KR 1019980063508A KR 19980063508 A KR19980063508 A KR 19980063508A KR 100300063 B1 KR100300063 B1 KR 100300063B1
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- plug
- forming
- bit line
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- field oxide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
본 발명은 반도체 메모리 제조방법에 관한 것으로, 종래 반도체 메모리 제조방법은 워드라인인 게이트의 사이에 증착된 절연물질을 식각한 후, 그 식각된 영역에 플러그를 형성함으로써, 상기 절연물질을 식각하는 공정은 게이트 측벽과 절연물질 간의 선택비가 높아야 하는 난이도가 높은 공정이며, 액티브영역에 손상을 주게되어 반도체 메모리의 특성이 저하되는 문제점과 아울러 비트라인 형성을 위한 공정단계가 복잡하여 제조비용이 증가하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 반도체 기판의 상부에 셀 트랜지스터를 제조하고, 그 셀 트랜지스터의 공통 소스와 각각의 드레인에 접속되는 플러그를 형성하는 플러그 형성단계와; 상기 공통 소스의 상부에 형성된 플러그에 접속되는 비트라인을 형성하는 비트라인 형성단계를 포함하는 반도체 메모리 제조방법에 있어서, 상기 플러그 형성단계는 상기 공통 소스에 접속되는 플러그를 필드산화막의 상부측 까지 길게 형성하고, 상기 비트라인 형성단계에서, 상기 필드산화막의 상부에 위치하는 플러그에 접속되는 비트라인을 형성하도록 구성하여, 비트라인 형성을 위한 플러그를 기판 및 필드산화막의 일부에 이르도록 길게 형성하고, 그 필드산화막의 상부에 위치하는 플러그에 선택적으로 접속되는 비트라인을 형성함으로써, 비트라인의 정합성을 향상시킴으로써, 반도체 소자의 특성 향상 및 신뢰성을 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory. In the related art, a method of manufacturing a semiconductor memory is performed by etching an insulating material deposited between a gate, which is a word line, and then forming a plug in the etched region, thereby etching the insulating material. Is a highly difficult process that requires a high selection ratio between the gate sidewall and the insulating material, which causes damage to the active region, deteriorates the characteristics of the semiconductor memory, and increases the manufacturing cost due to the complicated process steps for forming the bit line. There was this. In view of the above problems, there is provided a plug forming step of manufacturing a cell transistor on an upper surface of a semiconductor substrate and forming a plug connected to a common source and a drain of the cell transistor; A method of manufacturing a semiconductor memory including forming a bit line connected to a plug formed on an upper portion of the common source, wherein the plug forming step extends the plug connected to the common source to an upper side of a field oxide layer. And forming a bit line connected to a plug located above the field oxide film in the bit line forming step, and forming a plug for forming the bit line to reach a portion of the substrate and the field oxide film, By forming a bit line selectively connected to a plug located above the field oxide film, the matching of the bit lines is improved, thereby improving the characteristics and reliability of the semiconductor element.
Description
본 발명은 반도체 메모리 제조방법에 관한 것으로, 특히 비트라인과 플러그를 접속할 콘택을 게이트사이영역 까지 확장하여 공정여유도를 향상시키는데 적당하도록 한 반도체 메모리 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory, and more particularly, to a method of manufacturing a semiconductor memory in which a contact for connecting a bit line and a plug is extended to a region between gates so as to be suitable for improving process margin.
일반적으로, 반도체 메모리는 소스를 공유하는 두 모스 트랜지스터를 제조하고, 워드라인인 상기 모스 트랜지스터의 게이트와 수직으로 교차하는 비트라인을 상기 워드라인과 절연되도록 형성한다. 이와 같은 공정에서 소자의 집적도가 향상되면서 비트라인이 형성되는 액티브영역간의 간격이 좁아지게 되어, 비트라인을 형성하는 영역이 좁아지게 되어 공정 여유도가 감소하게 되며, 이와 같은 종래 반도체 메모리 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a semiconductor memory fabricates two MOS transistors sharing a source, and forms a bit line that is perpendicular to the gate of the MOS transistor, which is a word line, to be insulated from the word line. In this process, as the degree of integration of the device is improved, the gap between the active regions in which the bit lines are formed is narrowed, the area in which the bit lines are formed is narrowed, and the process margin is reduced. When described in detail with reference to the accompanying drawings as follows.
도1은 종래 반도체 메모리의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 워드라인인 게이트(2)를 포함하며, 공통 소스(3) 및 독립적인 드레인(4)을 갖는 두 모스 트랜지스터를 제조하고, 그 모스 트랜지스터의 상부전면에 제 1절연층(5)을 형성한 후, 그 제 1절연층(5)에 콘택홀을 형성하여 상기 모스 트랜지스터의 공통 소스(3)를 노출키고 금속을 증착 및 패터닝하여 상기 두 모스 트랜지스터의 게이트(2)사이에 위치하며, 공통 소스(3)에 접속되는 비트라인(6)을 형성하며, 비트라인(6)과 제 1절연층(5)의 상부에 제 2절연층(7)을 증착하고, 콘택홀을 형성하여 상기 드레인(4)을 노출시킨 후, 그 드레인(4)에 접속되는 커패시터(8)를 형성하고, 제 3절연층(10)을 그 커패시터(8)의 상부에 증착하여 제조하게 된다.FIG. 1 is a cross-sectional view of a conventional semiconductor memory, as shown therein. A MOS transistor including a gate line, which is a word line, on top of a substrate 1, and having a common source 3 and an independent drain 4. After forming the first insulating layer (5) on the upper surface of the MOS transistor, and forming a contact hole in the first insulating layer (5) to expose the common source (3) of the MOS transistor and Is deposited and patterned to form a bit line 6 located between the gates 2 of the two MOS transistors and connected to a common source 3, and forming the bit line 6 and the first insulating layer 5. After depositing a second insulating layer 7 on the upper portion, forming a contact hole to expose the drain 4, a capacitor 8 connected to the drain 4 is formed, and the third insulating layer 10 is formed. Is deposited on top of the capacitor (8).
이하, 상기와 같은 종래 반도체 메모리 제조방법을 좀 더 상세히 설명한다.Hereinafter, a conventional method of manufacturing a semiconductor memory as described above will be described in more detail.
먼저, 반도체 기판(1)의 상부에 필드산화막(9)을 형성하여 반도체 소자가 형성될 영역을 정의하고, 그 영역의 상부에 게이트(2), 공통 소스(3), 드레인(4)을 포함하는 두 모스 트랜지스터를 제조한다. 이때, 상기 필드산화막(9)의 상부에도 게이트 패턴을 형성하여 모스 트랜지스터의 형성으로 인해 이후의 공정에서 단차가 발생하는 것을 방지하게 된다.First, a field oxide film 9 is formed on the semiconductor substrate 1 to define a region where a semiconductor device is to be formed, and includes a gate 2, a common source 3, and a drain 4 on the region. Two MOS transistors are manufactured. In this case, the gate pattern is formed on the field oxide layer 9 to prevent the step from occurring in the subsequent process due to the formation of the MOS transistor.
그 다음, 상기 두 모스 트랜지스터의 상부전면에 제 1절연층(5)을 증착한 후, 사진식각공정을 통해 콘택홀을 형성하여, 상기 모스 트랜지스터의 공통 소스(3)를 노출시킨다.Next, after the first insulating layer 5 is deposited on the upper surfaces of the two MOS transistors, a contact hole is formed through a photolithography process to expose the common source 3 of the MOS transistors.
그 다음, 상기 콘택홀이 형성된 제 1절연층(5)의 상부전면에 금속을 증착하고, 사진식각공정을 통해 패터닝하여 상기 콘택홀을 통해 공통 소스(3)에 접속 되는 비트라인(6)을 형성한다.Then, a metal is deposited on the upper surface of the first insulating layer 5 on which the contact hole is formed, and the bit line 6 connected to the common source 3 through the contact hole is patterned by a photolithography process. Form.
그 다음, 상기 비트라인(6)과 제 1절연층(5)의 상부에 제 2절연층(7)을 증착하고, 그 제 2절연층(7)과 제 1절연층(5)에 콘택홀을 형성하여 상기 모스 트랜지스터의 드레인(4)을 노출시키고, 그 제 2절연층(7)의 상부에 다결정실리콘을 증착하고 패터닝하여 커패시터의 하부전극을 형성한 후, 유전막과 상부전극 물질을 순차적으로 증착하여 커패시터(8)를 형성한 다음, 그 커패시터(8)의 상부전면에 제 3절연막(10)을 증착하여 반도체 메모리의 제조공정을 완료하게 된다.Next, a second insulating layer 7 is deposited on the bit line 6 and the first insulating layer 5, and contact holes are formed in the second insulating layer 7 and the first insulating layer 5. To form a lower electrode of the capacitor by depositing and patterning polycrystalline silicon on the second insulating layer 7 to form a drain 4 of the MOS transistor, and then forming a dielectric film and an upper electrode material sequentially. After the deposition to form the capacitor (8), the third insulating film 10 is deposited on the upper surface of the capacitor (8) to complete the manufacturing process of the semiconductor memory.
도2는 종래 반도체 메모리의 다른 실시예를 보인 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트(2), 공통 소스(3) 및 독립적인 드레인(4)을 갖는 두 모스 트랜지스터를 제조한 후, 그 모스 트랜지스터의 상부에 제 1절연층(5)을 형성한 후, 사진식각공정을 통해 상기 제 1절연층(5)에 콘택홀을 형성하여 상기 공통 소스(3) 및 드레인(4)을 노출시킨다.FIG. 2 is a cross-sectional view of another embodiment of a conventional semiconductor memory, and as shown therein, two MOS transistors having a gate 2, a common source 3, and an independent drain 4 on the substrate 1. After manufacturing, the first insulating layer 5 is formed on the MOS transistor, and then a contact hole is formed in the first insulating layer 5 through a photolithography process to form the common source 3 and the drain ( 4) is exposed.
그 다음, 상기 제 1절연층(5)의 상부전면에 다결정실리콘을 증착하고, 평탄화하여 상기 콘택홀을 통해 각각 소스(3)와 드레인(4)에 접속되는 플러그(11),(12)를 형성한다.Next, polysilicon is deposited on the upper surface of the first insulating layer 5, and planarized to connect the plugs 11 and 12 connected to the source 3 and the drain 4 through the contact holes, respectively. Form.
그 다음, 상기 플러그(11)에 접속되며, 그 후면으로 긴 형태의 연결패턴(13)을 형성한다.Then, it is connected to the plug 11, to form a long connection pattern 13 to the rear.
그 다음, 상기 절연층 증착 및 패터닝공정을 통해 비트라인의 형성위치를 정한 후, 금속을 증착 및 패터닝하여 도3에 도시한 바와 같이 비트라인(6)을 상기 소스에 접속되는 플러그(11)에 접속되는 연결패턴(13)에 접속되며, 상기 제 1절연층(5)의 상부에서 상기 모스 트랜지스터의 게이트(2)와 수직인 방향으로 교차하도록 형성한다.Next, after forming the bit line through the insulating layer deposition and patterning process, the metal is deposited and patterned to connect the bit line 6 to the plug 11 connected to the source as shown in FIG. It is connected to the connection pattern 13 to be connected, and is formed to cross in the direction perpendicular to the gate 2 of the MOS transistor on the first insulating layer (5).
이때, 비트라인(6) 및 연결패턴(13) 형성과정에서도 식각공정을 사용하므로, 플러그(11)의 상부에 손상을 줄수 있으며, 상기 연결패턴(13) 또한 비트라인(6) 형성시 손상받을 수 있다.At this time, since the etching process is also used in the process of forming the bit line 6 and the connection pattern 13, the upper part of the plug 11 may be damaged, and the connection pattern 13 may also be damaged when the bit line 6 is formed. Can be.
그리고, 상기 도3에 보인 구조의 플러그(11)에 접속되는 비트라인(6)을 형성하기 위해서 절연막 증착 및 콘택홀 형성과정을 포함하는 연결패턴(13) 형성단계를 거치게 되어 비트라인(6) 형성과정은 2단계의 절연막 증착 및 콘택홀 형성, 금속공정을 수행해야 함으로써, 공정단계가 상대적으로 복잡해진다.In addition, in order to form the bit line 6 connected to the plug 11 having the structure shown in FIG. 3, the connection pattern 13 forming process including the insulating layer deposition and the contact hole forming process is performed. The formation process is relatively complicated by the two-step insulating film deposition, contact hole formation, and metal processing.
그러나, 상기한 바와 같이 종래 반도체 메모리 제조방법 중 도1에 보인 실시예는 비트라인 형성을 위한 콘택홀을 두 게이트의 사이에 직접형성하여 소자의 집적도가 향상되면서, 공정 여유도를 확보하기 어려워, 콘택홀 형성시 게이트가 파손되거나, 비트라인이 상기 모스 트랜지스터의 공통 소스에 정확히 접속되지 않아 반도체 메모리의 신뢰성이 저하되는 문제점이 있으며, 상기 도2에 보인 실시예는 워드라인인 게이트의 사이에 증착된 절연물질을 식각한 후, 그 식각된 영역에 플러그를 형성함으로써, 상기 절연물질을 식각하는 공정은 게이트 측벽과 절연물질 간의 선택비가 높아야 하는 난이도가 높은 공정이며, 액티브영역에 손상을 주게되어 반도체 메모리의 특성이 저하되는 문제점과 아울러 비트라인 형성을 위한 공정단계가 복잡하여 제조비용이 증가하는 문제점이 있었다.However, as described above, the embodiment shown in FIG. 1 of the conventional semiconductor memory manufacturing method forms a contact hole for forming a bit line directly between two gates, thereby increasing the integration degree of the device and making it difficult to secure process margin. When the contact hole is formed, the gate is broken or the bit line is not connected to the common source of the MOS transistor correctly, thereby reducing the reliability of the semiconductor memory. The embodiment shown in FIG. 2 is deposited between the gates, which are word lines. After the insulating material is etched, a plug is formed in the etched area, and the process of etching the insulating material is a highly difficult process in which the selectivity between the gate sidewall and the insulating material must be high, and damages the active area to the semiconductor. In addition to the problem of deteriorating memory characteristics, the manufacturing cost for forming bit lines is complicated. There was a problem that the dragon increased.
이와 같은 문제점을 감안한 본 발명은 1회의 금속공정에 의해 비트라인을 형성하면 서도, 게이트사이에 콘택홀을 형성하는 과정을 생략할 수 있는 반도체 메모리 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a semiconductor memory manufacturing method capable of omitting the process of forming contact holes between gates while forming a bit line by one metal process.
도1은 종래 반도체 메모리의 일실시 단면도.1 is a cross-sectional view of one embodiment of a conventional semiconductor memory.
도2는 종래 반도체 메모리의 다른 실시 단면도.2 is a cross-sectional view of another embodiment of a conventional semiconductor memory.
도3은 도2의 구성에서 비트라인 및 비트라인 플러그를 입체적으로 보인 모식도.FIG. 3 is a schematic diagram showing in three dimensions the bit line and the bit line plug in the configuration of FIG. 2; FIG.
도4a 내지 도4f는 본 발명 반도체 메모리의 제조공정 수순 평면도.4A to 4F are plan views showing the manufacturing process of the semiconductor memory of the present invention.
도5a 내지 도5b는 도4a 내지 도4f의 A-A'방향의 단면도.5A to 5B are sectional views taken along the line AA ′ of Figs. 4A to 4F;
도6a 내지 도6c는 도4c 내지 도4e의 B-B'방향의 단면도.6A to 6C are cross-sectional views taken along the line BB ′ in FIGS. 4C to 4E.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
51:기판 52:필드산화막51: substrate 52: field oxide film
53:플러그 54:제 1절연막53: plug 54: first insulating film
55:측벽 56:비트라인55: side wall 56: bit line
57:산화막 58:커패시터 제조용 플러그57: oxide film 58: capacitor manufacturing plug
상기와 같은 목적은 반도체 기판의 상부에 셀 트랜지스터를 제조하고, 그 셀 트랜지스터의 공통 소스와 각각의 드레인에 접속되는 플러그를 형성하는 플러그 형성단계와; 상기 공통 소스의 상부에 형성된 플러그에 접속되는 비트라인을 형성하는 비트라인 형성단계를 포함하는 반도체 메모리 제조방법에 있어서, 상기 플러그 형성단계는 상기 공통 소스에 접속되는 플러그를 필드산화막의 상부측 까지 길게 형성하고, 상기 비트라인 형성단계에서, 상기 필드산화막의 상부에 위치하는 플러그에 접속되는 비트라인을 형성하도록 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a plug forming step of manufacturing a cell transistor on top of a semiconductor substrate and forming a plug connected to a common source and a respective drain of the cell transistor; A method of manufacturing a semiconductor memory including forming a bit line connected to a plug formed on an upper portion of the common source, wherein the plug forming step extends the plug connected to the common source to an upper side of a field oxide layer. And a bit line connected to a plug positioned on the field oxide film in the bit line forming step. The present invention will be described in detail with reference to the accompanying drawings. .
도4a 내지 도4f는 본 발명 반도체 메모리의 제조공정 수순 평면도이고, 도5a 내지 도5f는 도4a 내지 도4f의 A-A'방향의 단면도로서, 이에 도시한 바와 같이 기판(51)의 상부에 필드산화막(52)을 형성하여 소자형성영역을 정의하고, 상기 필드산화막(52)의 상부에 게이트(G3,G4)를 형성함과 아울러 그 소자 형성영역인 기판(1)의 상부에 공통 소스를 갖으며, 각각 게이트(G1,G2)를 포함하는 모스 트랜지스터를 제조하는 단계(도4a, 도5a)와; 상기 모스 트랜지스터가 형성된 기판(1)의 상부전면에 다결정실리콘을 증착하고, 식각공정을 통해 상기 게이트(G1~G4)의 사이에 다결정실리콘 플러그(53)를 형성하는 단계(도4b, 도5b)와; 상기 플러그(53)와 게이트(G1~G4)의 상부전면에 제 1절연막(54)를 증착하고, 상기 사진식각공정을 통해 상기 게이트(G1,G2)의 사이에 형성된 플러그(53)의 상부를 노출시킴과 아울러 그 후면에 형성된 플러그(53)의 상부를 노출시키는 콘택홀을 형성하는 단계(도4c, 도5c)와; 상기 제 1절연막(54)의 상부에 상기 제 1절연막(54)과는 선택적 식각이 가능한 제 2절연막를 증착하고 에치백하여 상기 플러그(53)를 노출시키는 콘택홀의내측면에 측벽(55)을 형성하여 게이트(G1,G2)의 사이에 노출된 플러그(53)의 일부가 노출되는 것을 방지하는 단계(도4d, 도5d)와; 상기 제 1절연막(54)과 제 2절연막 측벽(55)에 의해 노출된 플러그(53)에 접속되는 비트라인(56)을 형성하는 단계(도4e, 도5e)와; 상기 비트라인(56)과 제 1절연막(54)의 상부전면에 산화막(57)을 증착하고, 패터닝하여 상기 게이트(G3,G1),(G2,G4)의 사이에 형성한 플러그(53)를 노출시킨 후, 그 노출된 플러그(53)의 상부에 커패시터 제조용 플러그(58)를 형성하는 단계(도4f, 도5f)를 포함하여 구성된다.4A to 4F are plan views showing the manufacturing process of the semiconductor memory of the present invention, and FIGS. 5A to 5F are cross-sectional views taken along the line A-A 'of FIGS. 4A to 4F. A field oxide layer 52 is formed to define an element formation region, and gates G3 and G4 are formed on the field oxide layer 52 and a common source is formed on the substrate 1 which is the element formation region. Manufacturing MOS transistors each having gates G1 and G2 (FIGS. 4A and 5A); Depositing polysilicon on the upper surface of the substrate 1 on which the MOS transistor is formed, and forming a polysilicon plug 53 between the gates G1 to G4 through an etching process (FIGS. 4B and 5B). Wow; The first insulating layer 54 is deposited on the upper surface of the plug 53 and the gates G1 to G4, and the upper portion of the plug 53 formed between the gates G1 and G2 through the photolithography process. Exposing and forming a contact hole exposing the upper portion of the plug 53 formed on the rear surface thereof (Figs. 4c and 5c); A sidewall 55 is formed on an inner side surface of the contact hole exposing the plug 53 by depositing and etching back a second insulating layer that is selectively etched with the first insulating layer 54 on the first insulating layer 54. Preventing a portion of the plug 53 exposed between the gates G1 and G2 from being exposed (FIGS. 4D and 5D); Forming bit lines 56 connected to the plugs 53 exposed by the first insulating film 54 and the second insulating film sidewalls 55 (FIGS. 4E and 5E); The plug 53 formed between the gates G3 and G1 and G2 and G4 is deposited by patterning and patterning an oxide film 57 on the upper surface of the bit line 56 and the first insulating layer 54. After exposure, a step (FIG. 4F, 5F) is formed to form a plug 58 for capacitor manufacture on top of the exposed plug 53. FIG.
이하, 상기와 같이 구성된 본 발명 반도체 메모리 제조방법을 좀 더 상세히 설명한다.Hereinafter, the method of manufacturing the semiconductor memory of the present invention configured as described above will be described in more detail.
먼저, 도4a 및 도5a에 도시한 바와 같이 기판(51)의 상부에 필드산화막(52)을 형성하여 소자형성영역(ACTIVE)을 정의한다.First, as shown in FIGS. 4A and 5A, a field oxide film 52 is formed on the substrate 51 to define an element formation region ACTIVE.
그 다음, 게이트산화막, 다결정실리콘, 질화막을 순차적으로 증착하고, 패터닝하여 상기 필드산화막(52)의 상부에 게이트(G3),(G4)를 형성함과 아울러 기판(1) 상에 상호 소정거리 이격되는 게이트(G1,G2)를 형성한다.Subsequently, the gate oxide film, the polysilicon, and the nitride film are sequentially deposited and patterned to form gates G3 and G4 on the field oxide film 52 and spaced apart from each other on the substrate 1 by a predetermined distance. Gates G1 and G2 are formed.
그 다음, 저농도 소스 및 드레인(도면미도시)을 형성하고, 각 게이트(G1~G4)의 측면에 질화막 측벽을 형성한 후, 고농도 소스 및 드레인(도면미도시)을 형성하여 공통 소스를 갖는 모스 트랜지스터를 형성하고, 기판과의 단차발생을 제거하기 위해 필드산화막(52)의 상부에 게이트(G3,G4)를 형성하는 과정을 완료하게 된다.Next, a low concentration source and drain (not shown) are formed, a nitride film sidewall is formed on the side surfaces of the gates G1 to G4, and a high concentration source and drain (not shown) are formed to form a morse having a common source. The process of forming the transistors and forming the gates G3 and G4 on the field oxide film 52 is completed to eliminate the step difference with the substrate.
그 다음, 도4b 및 도5b에 도시한 바와 같이 상기 모스 트랜지스터가 형성된 기판(51)의 상부전면 및 게이트(G3,G4)가형성된 필드산화막(52)의 상부전면에 다결정실리콘을 증착하고, 평탄화 및 사진식각공정을 통해 상기 게이트(G1~G4)의 사이에 위치하는 플러그(53)를 형성한다. 이때, 상기 게이트(G1,G2)의 사이에 형성되는 플러그(53)는 상기 기판(51) 상에 형성한 공통 소스의 상부와 연결되어 필드산화막(52)의 상부로 길게 형성한다.Next, as shown in FIGS. 4B and 5B, polysilicon is deposited on the upper surface of the substrate 51 on which the MOS transistor is formed and on the upper surface of the field oxide film 52 on which the gates G3 and G4 are formed. A plug 53 positioned between the gates G1 to G4 is formed through planarization and photolithography. In this case, the plug 53 formed between the gates G1 and G2 is connected to an upper portion of the common source formed on the substrate 51 to form a long portion over the field oxide layer 52.
이와 같이 게이트(G1,G2) 사이의 플러그(53)를 필드산화막(52)의 상부측으로 길게 형성하는 이유는 이후의 공정에서 비트라인을 상기 게이트(G1,G2) 사이에 직접 형성하지 않고 필드산화막(52)의 상부에 위치하는 플러그(53)에 비트라인을 접속하기 위한 것이다.The reason why the plug 53 between the gates G1 and G2 is formed long to the upper side of the field oxide film 52 is that the field oxide film is not directly formed between the gates G1 and G2 in a subsequent process. The bit line is connected to the plug 53 located at the upper portion of the 52.
그 다음, 도4c 및 도5c에 도시한 바와 같이 상기 플러그(53)가 형성된 기판(51) 및 필드산화막(52)의 상부전면에 제 1절연막(54)을 증착하고, 사진식각공정을 통해 상기 제 1절연막(54)에 콘택홀을 형성하여 상기 형성한 게이트(G1,G2) 사이의 플러그(53)의 일부를 노출시킨다. 이때, 콘택홀의 형태는 상기 게이트(G1,G2) 사이인 모스 트랜지스터의 공통소스 상부에 위치하는 플러그(53)를 노출시키고, 상기 공통소스와 인접한 필드산화막(52)의 상부측에 위치한 플러그(53)의 상부를 상기 공통소스 상부영역보다 크게 노출시키는 구조로 형성한다.Next, as shown in FIGS. 4C and 5C, the first insulating layer 54 is deposited on the upper surface of the substrate 51 and the field oxide layer 52 on which the plug 53 is formed, and the photo-etching process is performed. A contact hole is formed in the first insulating layer 54 to expose a part of the plug 53 between the gates G1 and G2. In this case, the shape of the contact hole exposes the plug 53 positioned on the common source of the MOS transistor between the gates G1 and G2, and the plug 53 positioned on the upper side of the field oxide layer 52 adjacent to the common source. ) Is formed to have a structure exposing the upper portion than the common source upper region.
즉, 도6a는 도4c에 있어서 B-B'의 단면도로서, 이에 도시한 바와 같이 상기 필드산화막(52)의 상부측에 형성한 콘택홀은 게이트(G1,G2)의 상부인 질화막이 노출될 정도로 크게 형성한다.That is, FIG. 6A is a cross-sectional view taken along line B-B 'of FIG. 4C, and the contact hole formed on the upper side of the field oxide film 52 is exposed to the nitride film, which is the upper part of the gates G1 and G2. Form large enough.
그 다음, 도4d 및 도5d에 도시한 바와 같이 상기 콘택홀이 형성된 제 1절연막(54)의 상부에 상기 제 1절연막(54)과는선택적식각이 가능한 제 2절연막을 증착하고, 이를 건식식각하여 상기 제 1절연막(54)에 형성한 콘택홀의 내측면에 측벽(55)을 형성한다. 이와 같은 측벽(55)의 형성으로, 상기 기판(51) 상에 형성한 모스 트랜지스터의 공통 소스 상부영역에서 노출된 플러그(53)의 상부는 측벽(55)에 의해 노출되지 않으며, 상기 필드산화막(52)의 상부영역에서 노출된 플러그(53)의 상부는 상기 측벽(55)에 의해 그 노출된 면적이 줄어들게 된다.Next, as shown in FIGS. 4D and 5D, a second insulating layer that is selectively etchable with the first insulating layer 54 is deposited on the first insulating layer 54 having the contact hole, and the dry etching is performed. As a result, sidewalls 55 are formed on the inner surface of the contact hole formed in the first insulating layer 54. As a result of the formation of the side wall 55, the upper portion of the plug 53 exposed in the upper region of the common source of the MOS transistor formed on the substrate 51 is not exposed by the side wall 55, and the field oxide film ( The exposed portion of the plug 53 exposed in the upper region of 52 is reduced by the side wall 55.
즉, 도6b는 상기 도4d의 B-B'방향의 단면도로서, 이에 도시한 바와 같이 상기 필드산화막(52)의 상부에 위치하는 게이트(G1,G2)의 사이에 위치하는 플러그(53)의 상부는 노출된 면적을 갖게 되어 이후에 형성하는 비트라인이 모스 트랜지스터의 공통소스에 접속되도록 한다.FIG. 6B is a cross-sectional view taken along the line B-B 'of FIG. 4D. As shown therein, the plug 53 positioned between the gates G1 and G2 positioned on the field oxide film 52 is shown in FIG. The upper portion has an exposed area so that subsequent bit lines are connected to a common source of a MOS transistor.
그 다음, 도4e 및 도5e에 도시한 바와 같이 상기 제 1절연층(54), 측벽(55) 및 노출된 플러그(53)의 상부에 금속을 증착하고, 사진식각공정을 통해 상기 노출된 플러그(53)에 접속되며, 상기 게이트(G1~G4)의 방향과는 수직방향으로 긴 비트라인(56)을 형성한다. 상기와 같은 과정으로 모스 트랜지스터의 게이트로서 직접적으로 사용되는 기판(51) 상에 형성된 게이트(G1,G2)에 영향을 주지 않게 되며, 금속증착 및 패터닝과정을 상기 모스 트랜지스터의 공통 소스에 직접연결되는 플러그(53)의 상부를 제 2절연막 측벽(55)에 의해 보호되도록 한 후 실시하여 플러그(53) 및 게이트(G1,G2)에 손상을 주는 것을 방지하게 된다.Next, as illustrated in FIGS. 4E and 5E, metal is deposited on the first insulating layer 54, the sidewalls 55, and the exposed plug 53, and the exposed plug is formed through a photolithography process. It is connected to the 53, and forms a bit line 56 long in the direction perpendicular to the direction of the gate (G1 ~ G4). The above process does not affect the gates G1 and G2 formed on the substrate 51 directly used as the gate of the MOS transistor, and the metal deposition and patterning process is directly connected to the common source of the MOS transistor. The upper part of the plug 53 is protected by the second insulating layer sidewall 55 and then prevented from damaging the plug 53 and the gates G1 and G2.
도6c는 상기 도4e의 B-B'방향의 단면도로서, 이에 도시한 바와 같이 필드산화막(52)의 상부에 형성된 게이트(G1,G2)의사이에서 노출된 플러그(53)의 상부에 접속되는 비트라인(56)을 형성할 수 있게 된다. 이때의 비트라인(56)은 그 구성이 단순하여 1회의 금속증착 및 패터닝공정을 통해 제조할 수 있게 되며, 상기 게이트(G1~G4)의 사이에 형성된 플러그(53)와는 소정거리 이격된 위치에 형성되어 이후에 커패시터 형성을 위한 플러그 형성마진을 확보할 수 있게 된다.FIG. 6C is a cross-sectional view taken along the line B-B 'of FIG. 4E, and the bit connected to the upper portion of the plug 53 exposed between the gates G1 and G2 formed on the field oxide film 52 as shown therein. Line 56 can be formed. At this time, the bit line 56 may be manufactured by a simple metal deposition and patterning process due to its simple configuration, and may be spaced apart from the plug 53 formed between the gates G1 to G4 by a predetermined distance. After forming, it is possible to secure a plug forming margin for capacitor formation.
그 다음, 도4f 및 도5f에 도시한 바와 같이 상기 비트라인(56) 및 제 1절연층(54)의 상부에 산화막(57)을 증착하고, 사진식각공정을 통해 패터닝하여 상기 게이트(G3,G1)와 게이트(G2,G4)의 사이에 형성된 커패시터 연결용 플러그(53)를 노출시키고, 다결정실리콘을 증착 및 평탄화하여 커패시터 제조용 플러그(58)를 형성하게 된다.Next, as shown in FIGS. 4F and 5F, an oxide film 57 is deposited on the bit line 56 and the first insulating layer 54, and patterned by a photolithography process to form the gate G3, The capacitor connecting plug 53 formed between the G1 and the gates G2 and G4 is exposed, and the polycrystalline silicon is deposited and planarized to form the plug 58 for manufacturing the capacitor.
이후의 공정에서는 상기 커패시터 제조용 플러그(58)에 접속되는 커패시터를 형성하여 반도체 메모리의 제조공정을 완료하게 된다.In a subsequent process, a capacitor connected to the capacitor manufacturing plug 58 is formed to complete a process of manufacturing a semiconductor memory.
상기한 바와 같이 본 발명은 비트라인 형성을 위한 플러그를 기판 및 필드산화막의 일부에 이르도록 길게 형성하고, 그 필드산화막의 상부에 위치하는 플러그에 선택적으로 접속되는 비트라인을 형성함으로써, 공정단계를 단순화하여 소자의 불량발생률을 줄임과 아울러, 기판영역을 노출시키는 식각공정을 사용하지 않게 됨으로써 반도체 메모리의 신뢰성을 향상시키는 효과가 있으며, 반도체 메모리의 집적도가 심화되어 게이트의 사이가 좁아지는 경우에도 게이트 사이의 이격거리 이상의 콘택홀을 형성하고, 그 콘택홀 내에 측벽을 형성한 후 비트라인 물질을 증착하여 정합성을 향상시킴으로써, 반도체 소자의 특성 향상 및 신뢰성을 향상시키는 효과가 있고, 상기 비트라인을 플러그에 직접접속되도록 형성할 수 있어 비트라인과 플러그를 접속하는 수단의 형성을 생략하여 공정단계를 단순화함으로써 제조비용을 절감하는 효과가 있다.As described above, the present invention provides a process step by forming a plug for forming a bit line so as to reach a part of a substrate and a field oxide film, and forming a bit line selectively connected to a plug located above the field oxide film. Simplification reduces the defect rate of the device and eliminates the etching process of exposing the substrate region, thereby improving the reliability of the semiconductor memory. By forming contact holes greater than the separation distance therebetween, forming sidewalls in the contact holes, and depositing bit line materials to improve conformity, thereby improving the characteristics and reliability of semiconductor devices, and plugging the bit lines. It can be configured to be connected directly to the bit line and plug Is effective to reduce the manufacturing cost by simplifying the process steps by eliminating the formation of a unit.
Claims (4)
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