KR100321759B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR100321759B1
KR100321759B1 KR1019950006073A KR19950006073A KR100321759B1 KR 100321759 B1 KR100321759 B1 KR 100321759B1 KR 1019950006073 A KR1019950006073 A KR 1019950006073A KR 19950006073 A KR19950006073 A KR 19950006073A KR 100321759 B1 KR100321759 B1 KR 100321759B1
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South Korea
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conductive film
film
forming
mask
gate electrode
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KR1019950006073A
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Korean (ko)
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KR960035900A (en
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인성욱
최진호
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to guarantee a process margin regarding misalignment in a bitline process or Vss line contact mask process by making the upper corner of a gate pattern formed of an insulation layer so that a space between a gate electrode and a bitline is increased. CONSTITUTION: The first conductive layer for the gate electrode is deposited on a semiconductor substrate(11). A predetermined central region of the gate electrode is covered with a mask and a partial thickness of the first conductive layer is etched. The first insulation layer is deposited on the resultant structure. The first insulation layer is etched back. The first insulation layer and the first conductive layer are sequentially etched to form the gate pattern having the first insulation layer in the upper corner of the gate pattern by using a gate mask. A source/drain junction is formed. The second insulation layer which is planarized is formed on the resultant structure. The second conductive layer contact is formed which passes through the side surface of the first conductive layer and comes in contact with the source/drain junction.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 발명은 반도체소자 제조방법에 관한 것으로, 특히 게이트전극의 프로파일을 변형시켜 게이트전극과 측면 부위 또는 게이트전극과 게이트전극 사이를 통과하여 콘텍되는 비트라인 또는 Vss 라인간의 누설전류를 방지하기 위한 반도체 소자제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a semiconductor device for preventing leakage current between a bit line or a Vss line contacted through a gate electrode and a side portion or a gate electrode and a gate electrode by modifying a profile of the gate electrode. It relates to a manufacturing method.

일반적으로, 공간이 좁은 게이트 폴리실리콘 패턴 사이의 공간에 비트라인 또는 Vss 라인을 콘텍시키는 방법은 OSCON(oxide spacer contact) 혹은 SOSCON(sidewall oxide spacer contact) 공정을 사용하고 있다.In general, a method of contacting a bit line or a Vss line in a space between a narrow gate polysilicon pattern uses an oxide spacer contact (OSCON) or sidewall oxide spacer contact (SOSCON) process.

상기 OSCON 또는 SOSCON 형성방법은 통상적인 트랜지스터 구조를 완성한 상태에서, 전체구조 상부에 절연막 증착 및 평탄화 작업을 실시한 후, 콘택 마스크(mask)를 형성한 다음에 절연막을 부분적(OSCON 공정) 혹은 완전히(SOSCON 공정)식각하고 콘택홀 측벽 스페이서를 형성 한 후 비트라인 또는 Vss 라인을 증착하는 방법이다.In the OSCON or SOSCON forming method, the insulating film is deposited and planarized on the entire structure in a state where the conventional transistor structure is completed, and then a contact mask is formed, and then the insulating film is partially (OSCON process) or completely (SOSCON). Process) etching and forming contact hole sidewall spacers and then depositing bit lines or Vss lines.

그러나, 상기와 같은 종래의 방법은 게이트 폴리시릴콘막에 의한 토포로지(topology)와 마스크 작업시 발생되는 오정렬에 의해 게이트전극과 비트라인 또는 Vss 라인 사이의 접속 또는 절연마진 축소로 인해 누설전류과 유발되는 문제점이 있었다.However, the conventional method described above is caused by leakage current and leakage current due to the connection between the gate electrode and the bit line or the Vss line or the reduction of the insulation margin due to the topology and the misalignment generated during the masking operation. There was a problem.

따라서, 본 발명은 게이트전극 측면 부위 또는 게이트전극과 게이트전극 사이의 공간에 콘택되는 비트라인 또는 Vss 라인 등의 전도층과 상기 게이트전극 간에 누설전류가 발생하는 것을 방지하여 소자의 특성 및 제조 수율을 향상시키는 반도체 소자 제조방법을 제공함을 그 목적으로 한다.Accordingly, the present invention prevents leakage current from occurring between a conductive layer such as a bit line or a Vss line contacting a space between a gate electrode side portion or a space between the gate electrode and the gate electrode, and the gate electrode, thereby improving device characteristics and manufacturing yield. It is an object of the present invention to provide a method for manufacturing a semiconductor device to be improved.

상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은, 반도체기판 상부에 게이트전극용 제1전도막을 증착하는 단계; 예정된 게이트전극 중앙 영역을 마스크로 가리고 상기 제1전도막의 전체두께중 일부두께를 식각하는 단계; 결과물전면에 제1절연막을 증착하는 단계; 상기 제1절연막을 에치백하는 단계; 게이트 마스크를 사용하여 상기 제1절연막, 상기 제1전도막을 차례로 식각하여 상부 코너에 상기 제1절연막을 갖는 게이트 패턴을 형성하는 단계; 소오스/드레인 접합을 형성하는 단계; 전체구조 상부에 평탄화된 제2절연막을 형성하는 단계; 및 상기 제1전도막 측면 부위를 통과하여 상기 소오스/드레인 접합에 콘택되는 제2전도막 콘택을 실시하는 단계를 포함하여 이루어진 것을 특징으로 한다.A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of depositing a first conductive film for a gate electrode on a semiconductor substrate; Covering a predetermined center portion of the gate electrode with a mask and etching a portion of the entire thickness of the first conductive film; Depositing a first insulating film on the entire surface of the resultant material; Etching back the first insulating layer; Etching the first insulating layer and the first conductive layer in sequence using a gate mask to form a gate pattern having the first insulating layer in an upper corner; Forming a source / drain junction; Forming a planarized second insulating layer on the entire structure; And performing a second conductive film contact passing through the side surface of the first conductive film and contacting the source / drain junction.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

제 1A 도 내지 제 1G 도는 본 발명의 일실시예에 따른 버퍼용 비트라인 형성 공정도로소, 제 1A 도와 같이 실리콘 기판(11) 상에 게이트 산화막(12) 및 게이트 전극용 폴리실리콘막(13)을 차례로 형성하고, 상기 폴리실리콘막(13)의 소정부위를 전체두께중 일부두께 식각한다. 즉, 예정된 게이트전극의 중앙부분이 돌출되도록 이 부분을 마스크로 가리고 다른 영역의 폴리실리콘 일부두께를 식각한다.1A to 1G illustrate a process of forming a bit line for a buffer according to an embodiment of the present invention. The gate oxide film 12 and the polysilicon film 13 for a gate electrode are formed on the silicon substrate 11 as shown in FIG. 1A. Are formed sequentially, and a predetermined portion of the polysilicon film 13 is etched at a part of the total thickness. That is, the mask is covered with a mask so that the center portion of the predetermined gate electrode protrudes and the partial thickness of polysilicon in the other region is etched.

이어서, 제 1B 도와 같이 산화막 증착 및 에치백 공정(돌출부의 폴리실리콘 표면이 드러나도록 에치백 실시)을 실시하여 평탄화한다. 이에 의해 상기 폴리실리콘막(13)이 부분적으로 식각된 부위에 산화막(14)이 형성될 것이다. 물론 산화막 이외에 다른 절연막을 적용할 수도 있다.Subsequently, an oxide film deposition and an etch back process (etch back is carried out so that the surface of the polysilicon of the protrusion part is exposed) are performed and planarized like 1B. As a result, the oxide layer 14 may be formed at a portion where the polysilicon layer 13 is partially etched. Of course, other insulating films may be applied in addition to the oxide films.

이어서, 제 1C 도와 같이 게이트전극 마스크를 사용하여 상기 산화막(14), 폴리실리콘막(13) 및 게이트 산화막(12)을 차례로 시각한다. 그러면, 상단코너(conner) 부위에 산화막(14)을 가지는 게이트패턴이 형성된다.Subsequently, the oxide film 14, the polysilicon film 13, and the gate oxide film 12 are sequentially viewed using a gate electrode mask as shown in the 1C diagram. Then, the gate pattern having the oxide film 14 is formed in the upper corner portion.

이어서, 제 1D 도와 같이 저농도 불순물 이온주입, 게이트 측벽 스페이서(15) 형성 및 고농도 불순물 이온주입을 차례로 실시하여 LDD 구조의 소오스/드레인 접합영역(16)을 형성한 후, 제 1E 도와 같이 전체구조 상부에 평탄화 절연막(17)을 형성한다.Subsequently, the source / drain junction region 16 having the LDD structure is formed by sequentially performing the low concentration impurity ion implantation, the gate sidewall spacer 15, and the high concentration impurity ion implantation as shown in the 1D diagram. The planarization insulating film 17 is formed in it.

이어서, 제 1F 도와 같이 비트라인 콘택 마스크 및 상기 평탄화 절연막(17) 식각공정으로 접합영역(16)을 오픈시키고, 산화막 증착 후 이 산화막을 다시 비등방성 전면식각하여 콘택홀 측벽에 스페이서 산화막(18)을 형성한다.Subsequently, as shown in FIG. 1F, the junction region 16 is opened by the bit line contact mask and the planarization insulating layer 17. The oxide layer is anisotropically etched again after the deposition of the oxide layer, and the spacer oxide layer 18 is formed on the sidewall of the contact hole. To form.

끝으로, 제 1G 도는 비트라인 콘택용 폴리실리콘막(19)을 증착 및 패터닝한 상태이다.Finally, the polysilicon film 19 for the 1G or bit line contact is deposited and patterned.

상기 본 발명의 실시예는 게이트전극 패턴의 상부 코너 부분을 산화막과 같은 절연막으로 형성한 후 SOSCON 공정을 적용한 것으로, 제 1E 도의 상태에서 제 2도에 도시된 바와 같이 비트라인 콘택 마스크를 사용하여 평탄화 절연막(17)을 식각하되 전체두께중 일부두께만을 식각한 다음, 평탄화 절연막(17)의 일부식각부위측벽에 스페이서 절연막(20)을 형성한 후, 접합영역(16)을 오픈시키는 OSCON 공정에 적용할 수 있다.According to the exemplary embodiment of the present invention, the upper corner portion of the gate electrode pattern is formed of an insulating film such as an oxide film, and then the SOSCON process is applied. The planarization is performed by using a bit line contact mask as shown in FIG. The insulating film 17 is etched, but only a part of the total thickness is etched, and then the spacer insulating film 20 is formed on the sidewall of the etched portion of the planarization insulating film 17, and then applied to the OSCON process of opening the junction region 16. can do.

이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상, 상기 설명과 같은 본 발명은 게이트 패턴 상부 코너(conner) 부분을 절연막으로 형성함으로써 게이트전극 및 비트라인간의 공간을 증가시켜, 비트라인 또는 Vss 라인 콘택 마스크 작업시의 오정렬에 관련된 공정 마진을 확보하여 누설 전류 방지와 소자의 제조 수율을 향상시키는 효과가 있다.As described above, the present invention increases the space between the gate electrode and the bit line by forming the upper portion of the gate pattern as an insulating film, thereby securing process margins related to misalignment during bit line or Vss line contact mask operation. Therefore, there is an effect of preventing leakage current and improving the manufacturing yield of the device.

제 1A 도 내지 제 1G 도는 본 발명의 일 실시예에 따른 버퍼용 비트라인 형성 공정도,1A to 1G are a bit line forming process diagram for a buffer according to an embodiment of the present invention,

제 2 도는 본 발명의 다른 실시예에 따라 비트라인 콘텍홀이 형성된 상태의 단면도.2 is a cross-sectional view of a bit line contact hole formed according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 실리콘 기판 12 : 게이트 산화막11 silicon substrate 12 gate oxide film

13 : 게이트전극용 폴리실리콘막 14 : 산화막13 polysilicon film for gate electrode 14 oxide film

15 : 게이트 측벽 스페이서 16 : 접합영역15 gate sidewall spacer 16 junction region

17 : 평탄화 절연막 18,20 : 스페이서 산화막17 planarization insulating film 18,20 spacer oxide film

19 : 버퍼용 비트라인 콘택용 폴리실리콘막19: polysilicon film for buffer bit line contact

Claims (5)

반도체소자 제조방법에 있어서,In the semiconductor device manufacturing method, 반도체기판 상부에 게이트전극용 제1전도막을 증착하는 단계;Depositing a first conductive film for a gate electrode on the semiconductor substrate; 예정된 게이트전극 중앙 영역을 마스크로 가리고 상기 제1전도막의 전체두께중 일부두께를 식각하는 단계;Covering a predetermined center portion of the gate electrode with a mask and etching a portion of the entire thickness of the first conductive film; 결과물 전면에 제1절연막을 증착하는 단계;Depositing a first insulating film on the entire surface of the resultant product; 상기 제1절연막을 에치백하는 단계;Etching back the first insulating layer; 게이트 마스크를 사용하여 상기 제1절연막, 상기 제1전도막을 차례로 식각하여 상부 코너에 상기 제1절연막을 갖는 게이트 패턴을 형성하는 단계;Etching the first insulating layer and the first conductive layer in sequence using a gate mask to form a gate pattern having the first insulating layer in an upper corner; 소오스/드레인 접합을 형성하는 단계;Forming a source / drain junction; 전체구조 상부에 평탄화된 제2절연막을 형성하는 단계; 및Forming a planarized second insulating layer on the entire structure; And 상기 제1전도막 측면 부위를 통과하여 상기 소오스/드레인 접합에 콘택되는 제2전도막 콘택을 실시하는 단계Performing a second conductive film contact through the side surface of the first conductive film and contacting the source / drain junction; 를 포함하여 이루어진 것을 특징으로 하는 반도체 소자 제조방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제2전도막 콘택 단계는,The second conductive film contacting step, 콘택 마스크 및 상기 제2절연막 식각공정으로 상기 소오스/드레인 접합을 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole exposing the source / drain junction by a contact mask and the second insulating layer etching process; 상기 콘택홀 측벽에 스페이서 제3절연막을 형성하는 단계; 및Forming a spacer third insulating layer on the sidewalls of the contact hole; And 결과물 전면에 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Forming a second conductive film on the entire surface of the resulting semiconductor device manufacturing method. 제1항에 있어서;The method of claim 1; 상기 제2전도막 콘택 단계는,The second conductive film contacting step, 콘택 마스크를 사용하여 상기 제2연막의 전체두께중 일부두께를 식각하는 단계;Etching a portion of the total thickness of the second smoke film using a contact mask; 상기 제2절연막이 식각된 부위의 측벽에 스페이서 제3절연막을 형성하는 동시에 잔류하는 두께의 상기 제2절연막을 식각하여 접합영역을 오픈시키는 단계;Forming a spacer third insulating film on a sidewall of the portion where the second insulating film is etched and etching the second insulating film having a remaining thickness to open a junction region; 결과물 전면에 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Forming a second conductive film on the entire surface of the resulting semiconductor device manufacturing method. 제2항 또는 제3항에 있어서,The method according to claim 2 or 3, 상기 제2전도막은 비트라인 전도막 또는 Vss 라인용 전도막임을 특징으로 하는 반도체 소자 제조방법.And the second conductive film is a bit line conductive film or a conductive film for a Vss line. 제2항 또는 제3항에 있어서,The method according to claim 2 or 3, 상기 제1 및 제2 전도막은 폴리실리콘막이며, 상기 제1절연막은 산화막임을 특징으로 하는 반도체 소자 제조방법.Wherein the first and second conductive films are polysilicon films, and the first insulating film is an oxide film.
KR1019950006073A 1995-03-22 1995-03-22 Method for fabricating semiconductor device KR100321759B1 (en)

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