KR100460704B1 - Method for fabricating bottom gate-type tft of sram to increase capacitance of node - Google Patents
Method for fabricating bottom gate-type tft of sram to increase capacitance of node Download PDFInfo
- Publication number
- KR100460704B1 KR100460704B1 KR1019960076383A KR19960076383A KR100460704B1 KR 100460704 B1 KR100460704 B1 KR 100460704B1 KR 1019960076383 A KR1019960076383 A KR 1019960076383A KR 19960076383 A KR19960076383 A KR 19960076383A KR 100460704 B1 KR100460704 B1 KR 100460704B1
- Authority
- KR
- South Korea
- Prior art keywords
- source
- bottom gate
- gate electrode
- drain
- ion implantation
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 3
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Abstract
Description
본 발명은 SRAM(Static Random Access Memory) 제조 공정 중 바텀 게이트(bottom gate)형 박막 트랜지스터 제조방법에 관한 것으로, 특히 게이트와소오스의 면적을 늘려 노드 정전용량(node capacitance)을 증가시킨 박막 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bottom gate type thin film transistor during a static random access memory (SRAM) manufacturing process, and more particularly, a method of manufacturing a thin film transistor having increased node capacitance by increasing the area of a gate and a source. It is about.
일반적으로, SRAM의 고집적화에 따라 셀 크기가 작아지며, 이에 따라 셀 내의 노드 정전용량이 감소하게 된다. 이러한 노드 정전용량의 감소는 소프트 에러비(soft error rate, 이하 SER이라 약칭함)를 증가시켜 메모리 장치의 신뢰도를 저하시키는 요인이 된다.In general, the cell size is reduced by the high integration of the SRAM, thereby reducing the node capacitance in the cell. This reduction in node capacitance increases the soft error rate (hereinafter, referred to as SER), which causes a decrease in reliability of the memory device.
첨부된 도면 도 1은 종래 기술에 따라 제조된 바텀 게이트형 박막 트랜지스터를 도시한 것으로, 도면 상에 표시된 도면 부호 10은 층간절연막, 11은 바텀 게이트 전극, 12는 게이트 산화막, 13은 소오스, 14는 드레인, 15는 채널 영역을 각각 나타낸 것이다.1 is a bottom gate type thin film transistor manufactured according to the related art, in which reference numeral 10 denotes an interlayer insulating film, 11 a bottom gate electrode, 12 a gate oxide film, 13 a source, and 14 Drain 15 represents a channel region, respectively.
도 1에 도시된 바와 같이 종래 기술에 따라 제조된 바텀 게이트형 박막 트랜지스터는 소오스/드레인(13,14)과 바텀 게이트 전극(11) 사이의 게이트 산화막(12)을 통해 노드 정전용량이 형성되기 때문에 노드 정전용량 확보에 어려움이 있다.In the bottom gate type thin film transistor manufactured according to the prior art as shown in FIG. 1, the node capacitance is formed through the gate oxide film 12 between the source / drain 13 and 14 and the bottom gate electrode 11. There is difficulty in securing node capacitance.
도 2는 SRAM 셀의 회로도를 나타낸 것으로, 박막 트랜지스터의 게이트와 소오스간에 형성되는 정전용량을 가시화한 것이다. 도면 부호 A는 노드 정전용량을 모델링한 캐패시터를 나타내고 있다.2 shows a circuit diagram of an SRAM cell, which visualizes the capacitance formed between the gate and the source of the thin film transistor. Reference numeral A denotes a capacitor modeling node capacitance.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 노드 정전용량을 증가시킨 에스램의 바텀 게이트형 박막 트랜지스터 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a bottom gate type thin film transistor of SRAM having increased node capacitance.
도 1은 종래 기술에 따라 형성된 박막 트랜지스터 단면도.1 is a cross-sectional view of a thin film transistor formed according to the prior art.
도 2는 통상적인 SRAM 셀 및 박막 트랜지스터의 노드 정전용량을 나타낸 회로도.2 is a circuit diagram showing node capacitance of a conventional SRAM cell and thin film transistor.
도 3A 내지 도 3C는 본 발명의 일실시예에 따른 박막 트랜지스터 제조 공정도.3A to 3C are diagrams illustrating a manufacturing process of a thin film transistor according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawing
10,30 : 층간절연막 11,31 : 바텀 게이트 전극10,30: interlayer insulating film 11,31: bottom gate electrode
12,33 : 게이트 산화막 13,34 : 소오스12,33: gate oxide film 13,34 source
14,35 : 드레인 15,36 : 채널 영역14,35 drain 15,36 channel region
32 : 포토레지스트 패턴32: photoresist pattern
A : 노드 정전용량을 나타낸 캐패시터A: Capacitor showing node capacitance
상기와 같은 목적을 달성하기 위한 본 발명의 일 측면에 따르면, 소정의 층간절연막 상에 바텀 게이트 전극을 형성하는 단계; 상기 바텀 게이트 전극이 형성된 전체구조 상부에 포토레지스트를 도포하는 단계; 소오스/드레인 이온주입 마스크를 사용한 사진 공정을 통해 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 장벽으로 하여 상기 층간절연막을 습식식각하여 상기 바텀 게이트 전극의 소오스측 하부에 언더컷 부위를 형성하는 단계; 노출된 상기 바텀 게이트 전극의 표면에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막이 형성된 전체구조 표면을 따라 폴리실리콘막을 형성하는 단계; 및 소오스/드레인 영역의 상기 폴리실리콘막에 소오스/드레인 이온주입을 실시하여 소오스/드레인 영역 및 채널 영역을 정의하는 단계를 포함하는 에스램의 바텀 게이트형 박막 트랜지스터 제조방법이 제공된다.According to an aspect of the present invention for achieving the above object, forming a bottom gate electrode on a predetermined interlayer insulating film; Applying a photoresist on the entire structure where the bottom gate electrode is formed; Forming a photoresist pattern through a photolithography process using a source / drain ion implantation mask; Wet etching the interlayer insulating layer using the photoresist pattern as an etch barrier to form an undercut portion under a source side of the bottom gate electrode; Forming a gate insulating film on an exposed surface of the bottom gate electrode; Forming a polysilicon film along an entire structure surface of the gate insulating film; And source / drain ion implantation into the polysilicon film in the source / drain region to define a source / drain region and a channel region.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 3A 내지 도 3C는 본 발명의 일실시예에 따른 박막 트랜지스터 제조 공정도이다. 도면 부호 30은 층간절연막, 31은 바텀 게이트 전극, 32는 포토레지스트패턴, 33은 게이트 산화막, 34는 소오스, 35는 드레인, 36은 채널 영역을 각각 나타낸 것이다.3A to 3C are flowcharts illustrating a manufacturing process of a thin film transistor according to an embodiment of the present invention. Reference numeral 30 denotes an interlayer insulating film, 31 a bottom gate electrode, 32 a photoresist pattern, 33 a gate oxide film, 34 a source, 35 a drain, and 36 a channel region.
본 실시예에 따른 박막 트랜지스터 제조 공정은, 먼저 도 3A에 도시된 바와같이 하부에 기형성된 n형 또는 p형 전계 효과 트랜지스터(도시되지 않음)와 그 상부에 형성될 박막 트랜지스터 간의 절연을 위한 층간절연막(30) 상부에 게이트 전극용 폴리실리콘막을 증착하고, 이를 패터닝하여 바텀 게이트 전극(31)을 형성한다.In the thin film transistor manufacturing process according to the present embodiment, as shown in FIG. 3A, an interlayer insulating film for insulation between an n-type or p-type field effect transistor (not shown) previously formed at a lower portion and a thin film transistor to be formed thereon is formed. 30, a polysilicon film for a gate electrode is deposited and patterned to form a bottom gate electrode 31. As shown in FIG.
다음으로, 도 3B에 도시된 바와 같이 전체구조 상부에 포토레지스트를 도포하고, 소오스/드레인 이온주입 마스크를 사용한 노광 및 현상 공정을 통해 채널 영역에 오버랩되는 포토레지스트 패턴(32)을 형성한다. 계속하여, 포토레지스트 패턴(32)을 사용하여 층간절연막(30)을 습식 식각함으로써 게이트 전극(31)의 소오스측 하부에 언더컷(undercut) 부위를 형성한다. 물론, 포토레지스트 패턴(32)은 게이트전극(31)으로부터 드레인 영역까지를 모두 덮도록 형성해도 무방하나, 후속 공정에서 사용되는 소오스/드레인 이온주입 마스크를 사용하면 별도의 포토마스크를 제작하지 않아도 되는 장점이 있다.Next, as shown in FIG. 3B, a photoresist is applied over the entire structure, and a photoresist pattern 32 overlapping the channel region is formed through an exposure and development process using a source / drain ion implantation mask. Subsequently, the interlayer insulating film 30 is wet-etched using the photoresist pattern 32 to form an undercut portion under the source side of the gate electrode 31. Of course, the photoresist pattern 32 may be formed to cover all of the drain region from the gate electrode 31, but it is not necessary to fabricate a separate photomask by using a source / drain ion implantation mask used in a subsequent process. There is an advantage.
이어서, 도 3C에 도시된 바와 같이 포토레지스트 패턴(32)을 제거하고, 전체 구조 표면에 게이트 산화막(33)을 형성한다. 계속하여, 그 상부에 폴리실리콘막을 증착하고, 그 상부에 포토레지스트를 도포한 후, 소오스/드레인 이온주입 마스크를 사용한 노광 및 현상 공정을 실시하여 채널 영역 상에 오버랩되는 포토레지스트 패턴(도시되지 않음)을 형성하고, 이를 이온주입 마스크로 사용하여 불순물 이온주입을 실시하여 소오스(34)/드레인(35) 및 채널 영역(36)을 정의한다. 이때, 언더컷부위를 그리 깊게 형성하지 않는 경우에는 일반적인 이온주입 공정(수직 이온주입)을 수행한 후 도펀트 안정화를 위하여 수행되는 통상의 열공정에서의 도펀트 확산이일어나기 때문에 소오스/드레인 형성에 별 어려움이 없다. 한편, 언더컷 부위가 아주 깊어 도펀트 확산만으로는 불완전하다면 경사 이온주입을 실시하면 된다.Subsequently, as shown in FIG. 3C, the photoresist pattern 32 is removed, and a gate oxide film 33 is formed on the entire structure surface. Subsequently, a polysilicon film is deposited thereon, a photoresist is applied thereon, and an exposure and development process using a source / drain ion implantation mask is performed to overlap the photoresist pattern on the channel region (not shown). ) And impurity ion implantation is used as an ion implantation mask to define the source 34 / drain 35 and the channel region 36. In this case, when the undercut portion is not formed deeply, since the dopant diffusion occurs in a general thermal process performed for stabilization of the dopant after performing a general ion implantation process (vertical ion implantation), it is difficult to form a source / drain. none. On the other hand, if the undercut region is very deep and incomplete by diffusion of dopant, gradient ion implantation may be performed.
상기와 같은 일실시예에 나타난 바와 같이 본 발명은 박막 트랜지스터 형성시 게이트 전극의 소오스측 하부에 언더컷을 형성하여 소오스와 게이트 전극 간의 접촉 면적을 넓힘으로써 정전용량을 증가시켜 SER 특성을 개선한다.As shown in the above embodiment, the present invention improves the SER characteristic by increasing the capacitance by forming an undercut under the source side of the gate electrode when the thin film transistor is formed to widen the contact area between the source and the gate electrode.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 본 발명을 실시하면 현재 사용하고 있는 소오스/드레인 이온주입 마스크를 사용하므로 별도의 레티클을 제조하지 않고, 간단한 공정을 추가하여 SRAM 셀의 노드 정전용량을 증가시킴으로써 SER 특성 등을 개선하여 반도체 장치의 신뢰도를 향상시키는 효과가 있다.As described above, the present invention uses a source / drain ion implantation mask that is currently used, so that a semiconductor process is improved by increasing the node capacitance of the SRAM cell by adding a simple process without manufacturing a separate reticle. There is an effect of improving the reliability of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076383A KR100460704B1 (en) | 1996-12-30 | 1996-12-30 | Method for fabricating bottom gate-type tft of sram to increase capacitance of node |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076383A KR100460704B1 (en) | 1996-12-30 | 1996-12-30 | Method for fabricating bottom gate-type tft of sram to increase capacitance of node |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980057113A KR19980057113A (en) | 1998-09-25 |
| KR100460704B1 true KR100460704B1 (en) | 2005-01-27 |
Family
ID=37376999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960076383A KR100460704B1 (en) | 1996-12-30 | 1996-12-30 | Method for fabricating bottom gate-type tft of sram to increase capacitance of node |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100460704B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06177353A (en) * | 1992-12-02 | 1994-06-24 | Seiko Epson Corp | Semiconductor device |
| KR960005896A (en) * | 1994-07-21 | 1996-02-23 | 문정환 | Method of manufacturing thin film transistor |
| KR960035905A (en) * | 1995-03-24 | 1996-10-28 | 김주용 | Method for manufacturing thin film transistor with drain offset structure |
| US5578838A (en) * | 1994-05-12 | 1996-11-26 | Lg Semicon Co., Ltd. | Structure of and fabricating method for a thin film transistor |
-
1996
- 1996-12-30 KR KR1019960076383A patent/KR100460704B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06177353A (en) * | 1992-12-02 | 1994-06-24 | Seiko Epson Corp | Semiconductor device |
| US5578838A (en) * | 1994-05-12 | 1996-11-26 | Lg Semicon Co., Ltd. | Structure of and fabricating method for a thin film transistor |
| KR960005896A (en) * | 1994-07-21 | 1996-02-23 | 문정환 | Method of manufacturing thin film transistor |
| US5547883A (en) * | 1994-07-21 | 1996-08-20 | Lg Semicon Co., Ltd. | Method for fabricating thin film transistor |
| KR960035905A (en) * | 1995-03-24 | 1996-10-28 | 김주용 | Method for manufacturing thin film transistor with drain offset structure |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980057113A (en) | 1998-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100610465B1 (en) | Method for fabricating semiconductor device | |
| KR960011664B1 (en) | Capacitor manufacturing method of semiconductor device | |
| KR100289808B1 (en) | Manufacturing method for mos transistor | |
| KR100460704B1 (en) | Method for fabricating bottom gate-type tft of sram to increase capacitance of node | |
| KR0135690B1 (en) | Fabrication method of contact in semiconductor device | |
| KR100223333B1 (en) | Method for forming a contact of semiconductor device | |
| KR100252899B1 (en) | Mask rom and method for fabricating the same | |
| KR100321758B1 (en) | Method for fabricating semiconductor device | |
| KR100242378B1 (en) | Manufacturing method of gate for a field effect transistor | |
| KR100197987B1 (en) | Method of manufacturing drain transistor | |
| KR100256259B1 (en) | Method of preparing common gate in semiconductor device | |
| KR100525114B1 (en) | Manufacturing method of semiconductor device | |
| KR100198637B1 (en) | Fabricating method of semiconductor device | |
| KR100192547B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR100250728B1 (en) | Method for fabricating transistor of semiconductor device | |
| KR100204006B1 (en) | Nand type mask rom | |
| KR100668840B1 (en) | Method of manufacturing semiconductor device | |
| KR930009590B1 (en) | Method for manufacturing a lsi mos device with capacitor | |
| KR100399965B1 (en) | Method for forming storage node contact of semiconductor device | |
| KR100252767B1 (en) | A semiconductor device and method for fabricating the same | |
| KR100503358B1 (en) | Manufacturing method of semiconductor device | |
| KR0136928B1 (en) | Manufacture of semiconductor | |
| KR19990004401A (en) | Method of manufacturing transistor of semiconductor device | |
| KR20020049934A (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR19990074731A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |