KR100250728B1 - Method for fabricating transistor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor of a semiconductor device is provided to remove a short channel effect by preventing an undercut of a lower portion of a polysilicon layer. CONSTITUTION: A trench is formed on a selected region of a silicon substrate(11). A gate oxide layer(13) and a polysilicon layer(14) are formed thereon. A high-density phosphorus ion implantation process is performed on an upper portion of the whole structure. The silicon substrate(11) is exposed by etching polysilicon layer and the gate oxide layer(13). A low-density phosphorus ion implantation process is performed on the upper portion of the whole structure. A spacer layer is deposited on the upper portion of the whole structure. A spacer(16) is formed at a sidewall of the gate electrode. A source and a drain(17) are formed by implanting a high-density ion of the fifth group.

Description

Method of manufacturing transistor of semiconductor device

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor of a semiconductor device.

In general, the effective channel length of the gate of the semiconductor device decreases as the degree of integration of the device increases. For 4M DRAM, the effective channel length is 0.6 ~ 0.7㎛, and the length of the channel becomes shorter as it goes to 16M, 64M, and 256M DRAM. In this case, the gate is responsible for opening / closing the applied voltage (ON / OFF) in the MOS device, so it is necessary to maintain a more stable threshold voltage. Therefore, the channel length and threshold voltage of the gate are becoming more important as they become more integrated devices.

In order to form a gate of a conventional transistor device, a gate oxide film and a polysilicon film are sequentially formed on a silicon substrate. Subsequently, selected regions of the polysilicon film and the gate oxide film are sequentially etched to form a gate pattern. However, when etching to form the gate pattern, an under cut occurs due to overetching in the gate oxide layer under the polysilicon layer, thereby reducing the channel region, thereby causing a problem of dropping the reliability of the device.

Accordingly, an object of the present invention is to provide a method of manufacturing a transistor of a semiconductor device for preventing undercuts generated during etching of a doped polysilicon film and securing a stable channel region essential for manufacturing a highly integrated memory device.

The present invention for achieving the above object is to form a trench in a selected region of the silicon substrate, sequentially forming a gate oxide film and a polysilicon film on the silicon substrate formed with the trench, and then implanting phosphorus ions into the entire structure Forming a photoresist pattern on the selected region on the polysilicon layer, sequentially etching the polysilicon layer and the gate oxide layer using the photoresist pattern as a mask to expose a silicon substrate, and Implanting a low concentration of phosphorus ions on the entire structure using a mask, depositing a spacer film on the entire structure, patterning the spacers to form a spacer on the sidewall of the gate electrode, and then injecting a high concentration of Group 5 ions to form a source and a drain. Characterized in that it comprises a step of forming.

1 (a) to 1 (e) are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

11: silicon substrate 12: trench

13 gate oxide film 14 polysilicon film

15 photosensitive film 16 spacer

17: source / drain

The present invention will be described in detail with reference to the accompanying drawings.

1 (a) to 1 (e) are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.

FIG. 1A is a cross-sectional view of the trench 12 formed by determining a portion where a gate electrode is to be formed on the silicon substrate 11 and performing a mask and etching process. At this time, the trench 12 is formed to a depth of 0.3 ~ 0.4㎛ and a width of 0.5 ~ 0.6㎛.

As shown in FIG. 1B, a gate oxide film 13 having a thickness of about 170 to 180 전극 is formed on the silicon substrate 11 on which the trench 12 is formed, and then the polysilicon film 14 is used as a gate electrode. Is deposited to a thickness of about 3000 mm 3. At this time, the polysilicon film 14 is doped and deposited by LPCVD equipment. In order to increase the conductivity of the gate electrode and improve the RC delay, a high concentration of phosphorus is doped over the entire structure.

As shown in FIG. 1 (c), the photoresist film 15 is coated on the polysilicon film 14 and then patterned to form a photoresist pattern on a portion where the gate electrode is to be formed. Using the photoresist pattern as a mask, the polysilicon film 14 and the gate oxide film 13 are etched until the silicon substrate 11 is exposed to form a gate electrode. A low concentration of phosphorus is injected into both sides of the gate electrode using the photoresist pattern as a mask. Therefore, the characteristics of the device can be maintained by reducing the linear resistance of the channel and facilitating electron movement from the source to the drain while preventing the channel region from shrinking. In addition, an oxide layer on both sides of the lower end of the electrode may prevent a short channel effect of the transistor.

As shown in FIG. 1D, a spacer layer is deposited on the entire structure and then patterned to form a spacer 16 on sidewalls of the gate electrode. The spacer film is a BSG, PSG or BPSG film is deposited to a thickness of 2000 kPa using the LPCVD method. Thereafter, high concentrations of Group 5 ions (As, P, etc.) are implanted to form the source and drain of the transistor.

Fig. 1 (e) is a cross-sectional view of a transistor in which a process is completed by forming a source / drain 17 by performing such a process.

As described above, according to the present invention, by preventing under-cut under the polysilicon layer, short channel effects can be eliminated and a stable channel region can be secured, and linear resistance is reduced to reduce high integration memory. Since a small transistor can be implemented, sufficient gate electrodes can be opened and closed even with low current.

Claims (3)

Forming a trench in a selected region of the silicon substrate, sequentially forming a gate oxide film and a polysilicon film on the silicon substrate on which the trench is formed, and implanting a high concentration of phosphorus ions into the entire structure; Forming a photoresist pattern in a selected region of the upper portion, exposing the silicon substrate by sequentially etching the polysilicon layer and the gate oxide layer using the photoresist pattern as a mask, and using the photoresist pattern as a mask, a low concentration on the entire structure Implanting phosphorus ions, and depositing a spacer film over the entire structure to form a spacer on the sidewall of the gate electrode, and then implanting a high concentration of Group 5 ions to form a source and a drain. A transistor manufacturing method of a semiconductor device. The method of claim 1, wherein the trench is formed to a depth of 0.3 to 0.4 μm and a width of 0.5 to 0.6 μm. The method of claim 1, wherein the spacer film is made of any one of BSG, PSG, and BPSG films.

Images