KR19990004943A - Transistor Formation Method With Low Doping Drain Structure - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs

Regarding the field of semiconductor manufacturing.

2. Technical problem to be solved by the invention

A method of forming a transistor having a low concentration doped drain structure in which a gate completely covering a low concentration doped drain region can be formed in a relatively simple process without process limitation depending on the size of the device is provided.

3. Summary of the Solution of the Invention

The ion implantation prevention layer is etched to form a hole exposing only a low concentration doped region and a region where a channel is to be formed, a low concentration doped drain region is formed, a spacer is formed on the sidewall of the hole with a conductive film, and a channel region is formed by ion implantation. Is embedded with a conductive film and the ion implantation prevention film is removed to form a gate electrode.

4. Important uses of the invention

Used to manufacture semiconductor devices

Description

Transistor Formation Method With Low Doping Drain Structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a transistor having a lightly doped drain structure.

As semiconductor devices become more integrated, the channel length of transistors is decreasing. If the channel length of the transistor is 2 μm or less, deterioration of the device may occur due to a hot carrier effect. As the size of the device decreases, the channel length of the device shortens, and the source region and the drain region are formed close to each other, so that high temperature carriers crossing the barrier are trapped in the oxide film to change the threshold voltage and voltage-current characteristics. The high temperature carrier effect can be reduced by reducing the doping concentration in the source and drain regions, i.e., by making the electric field of the junction less. However, reducing the doping of the source and drain regions has a problem of increasing contact resistance.

To solve this problem, a modified drain structure, such as a lightly doped drain, is used to reduce the electric field applied to the drain to reduce the electric field. Lightly doped drain (LDD) structures utilize two doping levels. That is, it consists of a high concentration source and drain region and a low concentration region adjacent to the channel. The low concentration doped drain structure reduces the electric field between the drain and the channel region to prevent hot carriers from being injected into the oxide film.

There are several types of low concentration doped drain structures: Inverted-type gate inversed T gate LDD semiconductor transistors are formed so that the gate low concentration doped drain region does not exceed the gate electrode width, which can improve device lifetime in high electric fields. Drive current characteristics can be improved.

Hereinafter, a method for forming an inverted-type gate low concentration doped drain semiconductor transistor according to the related art will be described with reference to the accompanying drawings.

First, as shown in FIG. 1A, a polysilicon film 12 for forming a gate insulating film 11 and a gate electrode is formed on the semiconductor substrate 10, and selectively etched to form a rectangular gate electrode. Subsequently, a photosensitive film pattern 13 for selectively etching a portion of the polysilicon film is formed on the polysilicon film 12.

Next, as shown in FIG. 1B, a portion of the polysilicon layer 12 is etched using the photoresist pattern 13 as an etch stop layer to form an inverted tee type gate electrode. Subsequently, an ion implantation process is performed to form the lightly doped region 14.

Next, as shown in FIG. 1C, a sidewall oxide film 15 is formed on the inverted tee-type gate electrode and a high concentration ion implantation is performed to form a high concentration doped region 16 of a source and a drain.

The prior art for completely covering the low concentration doped drain region formed as described above with the gate electrode is complicated in the process and there are process limitations due to the reduction of the gate electrode width. In addition, the step of removing the polysilicon film having a predetermined thickness to form an inverted tee-type gate electrode has a problem in terms of process control.

Disclosure of Invention The present invention devised to solve the above problems is to provide a method for forming a transistor which can completely cover a low concentration doped drain region which is relatively simple in processing and does not cause reduction constraints of the gate electrode by the process. .

1A to 1C are cross-sectional views of a transistor forming process having a lightly doped drain structure according to the prior art.

2A through 2D are cross-sectional views of a transistor forming process having a lightly doped drain structure according to an embodiment of the present invention.

* Description of the main parts of the drawing

10, 20: semiconductor substrate 11, 21: gate insulating film

12 and 26 polysilicon film 13: photosensitive film pattern

14, 23: lightly doped region 15: sidewall oxide film

16, 27: heavily doped region 24: spacer

22 nitride layer 25 channel region

In accordance with another aspect of the present invention, a transistor forming method includes: forming a gate insulating film on a semiconductor substrate and forming an ion implantation prevention film pattern; A second step of forming a lightly doped region by performing an ion implantation process on an active region of the semiconductor substrate; A third step of depositing a first conductive layer on the semiconductor substrate on which the second step is completed and etching the entire surface to form a spacer on a sidewall of the ion implantation prevention film pattern to expose a portion of the lightly doped region; A fourth step of performing an ion implantation process for adjusting a threshold voltage on the lightly doped region exposed in the third step; A fifth step of depositing a second conductive film on the semiconductor substrate on which the fourth step is completed and etching back to expose the ion implantation prevention film pattern; A sixth step of removing the ion implantation prevention film; And a seventh step of forming a source and a drain region by performing a high concentration ion implantation process on the semiconductor substrate on which the sixth step is completed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a process of forming a semiconductor transistor having a lightly doped drain structure according to an embodiment of the present invention.

First, as shown in FIG. 2A, an oxide film 21 and a nitride film 22 are formed on a semiconductor substrate 10 on which a predetermined lower layer is formed to fabricate an NMOS transistor, and the nitride film 22 is selectively etched to form low concentration doping. The nitride film of the region a where the drain region and the channel are to be formed is removed. Subsequently, an ion implantation process is performed to form the lightly doped region 23.

Next, as shown in FIG. 2B, a polysilicon film is deposited on the entire structure and etched to form a spacer 24 on the sidewall of the nitride film. Since the width of the spacer varies according to the thickness of the polysilicon film, the size of the lightly doped drain region may be arbitrarily adjusted. Subsequently, an ion implantation process for forming a channel 25 is performed.

Next, as shown in FIG. 2C, the polysilicon film 26 is deposited and etched back on the entire structure to expose the nitride film 22.

Next, as shown in FIG. 2D, the nitride film 22 is removed and ion implantation is performed to form a highly doped region 27 of the source and drain.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the gate electrode can be formed to completely cover the low concentration doped drain region in a relatively simple process, and the size of the low concentration doped region can be freely adjusted to facilitate the fabrication of a device having a fine channel length.

Claims (3)

Forming a gate insulating film on the semiconductor substrate and forming an ion implantation prevention film pattern; A second step of forming a lightly doped region by performing an ion implantation process on an active region of the semiconductor substrate; A third step of depositing a first conductive layer on the semiconductor substrate on which the second step is completed and etching the entire surface to form a spacer on a sidewall of the ion implantation prevention film pattern to expose a portion of the lightly doped region; A fourth step of performing an ion implantation process for adjusting a threshold voltage on the lightly doped region exposed in the third step; A fifth step of depositing a second conductive film on the semiconductor substrate on which the fourth step is completed and etching back to expose the ion implantation prevention film pattern; A sixth step of removing the ion implantation prevention film; And And a seventh step of forming a source and a drain region by performing a high concentration ion implantation process on the semiconductor substrate on which the sixth step is completed. The method of claim 1, And forming the nitride implantation prevention film as a nitride film. The method of claim 1, And forming the first and second conductive films as polysilicon films.