KR100215858B1 - Method for coating mask rom - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of coding a mask rom.

Such a mask ROM coding method according to the present invention comprises the steps of preparing a semiconductor substrate defined by the active region and the field region, forming a plurality of gate insulating film and gate electrodes on the active region of the semiconductor substrate at regular intervals; Forming a source / drain impurity region in the semiconductor substrate on both sides of the gate electrode, masking a gate electrode of one region of the semiconductor substrate on which the plurality of gate electrodes are formed, and a source / drain impurity region on both sides of the gate electrode And performing a code ion implantation into a source / drain impurity region including a gate electrode of the same depth as that of the source / drain impurity region.

Description

Mask ROM Coding Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of coding a mask rom.

FIG. 1A is a graph illustrating operating characteristics of a general depletion transistor, and FIG. 1B is a graph illustrating operating characteristics of a conventional enhancement transistor.

As shown in FIGS. 1A to 1B, the depletion type transistor shows that a channel is formed even when a voltage is not applied to the gate electrode.

Hereinafter, a conventional method of coding a mask ROM will be described with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a conventional mask ROM coding method. First, as shown in FIG. 2A, a field region and an active region are defined in an n-type semiconductor substrate 11, and then field ions are implanted into the field region. Is performed to form a plurality of field oxide films 12 having a predetermined interval from each other.

A photo process and a depletion ion implantation are performed on the entire surface of the semiconductor substrate 11 including the field oxide film 12.

At this time, as the impurity used in the NMOS deflation mode, the channel must be made N-type, and therefore, acenic (As) ions which are N-type impurities are used.

Subsequently, as illustrated in FIG. 2B, the gate insulating layer 13 and the polycrystalline silicon layer are formed on the entire surface of the semiconductor substrate 11 including the field oxide layer 12, and then patterned through a photolithography process to form the semiconductor substrate ( A plurality of gate insulating films 13 and gate electrodes 14 are formed in the active region of 11.

In addition, an insulating film is deposited on the entire surface of the semiconductor substrate 11 including the gate electrodes 14 and then etched back to form sidewall spacers 15 on both sides of the gate electrode 14. .

Next, a source / drain impurity region 16 is formed on the semiconductor substrate 11 on both sides of the gate electrode 14 through a source / drain ion implantation process using the gate electrode 14 and the sidewall spacer 15 as a mask. do.

Subsequently, as shown in FIG. 2C, coding ion implantation is performed according to a customer's request. For this purpose, other regions except for the gate electrode 14 required to make an off transistor are masked.

That is, after the photoresist 17 is coated on the entire surface of the semiconductor substrate 11 including the gate electrodes 14, the photoresist 17 is patterned by an exposure and display process so that only the gate electrode 14 necessary for off transistor formation is exposed.

Code ions are implanted through the gate electrode 14 using the patterned photoresist 17 as a mask.

Accordingly, as shown in FIG. 2D, the photoresist 17 is removed, thereby creating an off transistor implemented by an on transistor and a coding ion implantation, thereby completing data coding.

However, the conventional mask ROM coding method has the following problems.

First, the implantation of the coding ions into the channel region causes damage to the substrate of the channel region.

This damage acts as a resistance component when viewed from the current flowing through the channel region and consequently interrupts the flow of current.

Second, since the deflation photo process and ion implantation are performed, the manufacturing process is complicated.

The present invention has been made to solve the above problems, to provide a mask ROM coding method suitable for improving the electrical properties of the device by preventing the substrate of the channel region due to the simplified manufacturing process and the implantation of coding ions. There is a purpose.

1A is a graph showing operation characteristics of a general depletion transistor.

1B is a graph showing operation characteristics of a general enhancement transistor.

2A through 2D are cross-sectional views illustrating a conventional mask ROM coding method.

3A to 3D are cross-sectional views illustrating a mask ROM coding method according to the present invention.

Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 field oxide film

23 gate insulating film 24 gate electrode

25 sidewall spacer 26 source / drain impurity region

27: photoresist

The mask ROM coding method according to the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate defined by an active region and a field region, a plurality of gate insulating film and gate on the active region of the semiconductor substrate at regular intervals Forming an electrode, forming a source / drain impurity region in the semiconductor substrate on both sides of the gate electrode, and forming a gate electrode in one region of the semiconductor substrate on which the plurality of gate electrodes are formed and source / drain impurity on both sides of the gate electrode And masking the region and performing code ion implantation in the source / drain impurity region including the gate electrode of another region to the same depth as the source / drain impurity region.

3A to 3D are cross-sectional views illustrating a method of coding a mask rom according to the present invention.

First, as shown in FIG. 3A, a field region and an active region are defined in the first conductivity type semiconductor substrate 21, and then a plurality of field oxide films 22 having a predetermined interval are formed by implanting field ions into the field region. To form.

Subsequently, as illustrated in FIG. 3B, a gate insulating film 23 and a polycrystalline silicon layer are formed on the entire surface of the semiconductor substrate 21 including the field oxide film 22, and then patterned through a photolithography process. The gate insulating film 23 and the gate electrodes 24 are formed in the active region of the 21.

In addition, an insulating film is deposited on the entire surface of the semiconductor substrate 21 including the gate electrodes 24 and then etched back to form sidewall spacers 25 on both sides of the gate electrode 24. .

Next, a source / drain impurity region 26 is formed in the semiconductor substrate 21 on both sides of the gate electrode 24 through a source / drain ion implantation process using the gate electrode 24 and the sidewall spacer 25 as a mask. do.

Subsequently, as shown in FIG. 3C, coding ion implantation is performed according to a customer's request. For this purpose, other regions except for the gate electrode 24 required to make an off transistor are masked.

That is, after the photoresist 27 is coated on the entire surface of the semiconductor substrate 21 including the gate electrodes 24, the photoresist 27 is patterned by an exposure and display process so that only the gate electrode 24 necessary for off transistor formation is exposed.

Code ions are implanted through the gate electrode 24 using the patterned photoresist 27 as a mask.

Code ion implantation implants p-type impurity ions as deep as the source / drain impurity region 26.

The reason is to reduce the breakdown voltage due to the decrease in the concentration difference between the source / drain impurity region 26 and the semiconductor substrate 21.

In other words, the breakdown voltage is lowered to Vcc or lower so that the deflation region is attached after Vcc is applied, and current flows using punch-through (ie, always turned on).

Accordingly, as shown in FIG. 3D, removing the photoresist 27 creates an off transistor implemented by an on transistor and a coding ion implantation, thereby completing data coding.

As described above, the mask ROM coding method according to the present invention has the following effects.

First, the mask ROM coding method is simple because deflation photo process and ion implantation process are omitted.

Second, current sensing is improved because the current charge caused by the channel resistance is rapidly increased by using the punch through voltage.

Claims (2)

Preparing a semiconductor substrate defined by an active region and a field region; Forming a plurality of gate insulating films and gate electrodes on the active region of the semiconductor substrate at regular intervals; Forming a source / drain impurity region in the semiconductor substrate on both sides of the gate electrode; Masking a gate electrode of one region and a source / drain impurity region on both sides of the semiconductor substrate on which the plurality of gate electrodes are formed, and a source / drain impurity region including a gate electrode of another region to the same depth as the source / drain impurity region A mask rom coding method comprising the step of performing a code ion implantation. The method of claim 1, And the code ion is formed of a p-type impurity when the n-type semiconductor substrate.

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