KR100205342B1 - Coding method of rom - Google Patents

Abstract

The present invention relates to a ROM coding method, to simplify the process and to increase the breakdown voltage of the depletion transistor to prevent punch through to provide a ROM coding method suitable for improving device reliability.

The ROM coding method of the present invention for this purpose comprises the steps of performing a second conduction type depletion ion implantation on a first conductive substrate in coding a ROM having a depletion transistor and an enhancement transistor; Selectively forming a plurality of device isolation regions in a predetermined portion of the substrate, implanting field ions of a first conductivity type into the entire surface including the device isolation region, and elements in the region where the enhancement transistor is to be formed; Selectively removing a portion of the isolation region, sequentially forming a gate insulating layer and a polysilicon layer on the entire surface including the substrate, and then selectively removing a portion to form a plurality of gate electrodes in an active region on the substrate; And forming a source / drain impurity region in the substrate on both sides of the electrode.

Description

ROM Coding Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of coding a NAND ROM device, and in particular, to simplify the process and improve the electrical characteristics of a transistor by using a field oxide film used as an isolation layer of the transistor. ) Coding method.

Hereinafter, a conventional ROM coding method will be described with reference to the accompanying drawings.

1A to 1C illustrate a ROM coding method using ion implantation according to the prior art, and FIG. 2 is a graph illustrating an operation characteristic of a transistor according to the related art.

First, as shown in FIG. 1A, a field region and an active region are defined in a predetermined region on the first conductive semiconductor substrate 1, and then field ions are implanted into the field region to form a plurality of field oxide films having a predetermined distance from each other ( 2) form.

Subsequently, the depletion ion implantation is selectively performed on the active region of the first conductive semiconductor substrate 1 by using the depletion ion implantation mask 3 (that is, masking the portion where the enhancement transistor is to be formed). .

At this time, as the impurity used in the NMOS depletion mode, the channel must be made N-type, and therefore an ionic (As) ion, which is N-type impurity, is used.

Subsequently, as shown in FIG. 1B, enhancement ions are selectively applied to an active region of the semiconductor substrate 1 by using the depletion ion implantation mask 4 (that is, masking a portion where an enhancement transistor is to be formed). Inject.

Boron (B) is used as a P-type impurity used at this time.

After removing the enhancement ion implantation mask as shown in FIG. 1C, the gate oxide film and the polysilicon are sequentially deposited on the semiconductor substrate 1, and then selectively removed to form the gate electrodes 5.

Next, source / drain impurity ions are implanted using the gate electrodes 5 as a mask to form source / drain impurity regions 6 and 7 in the semiconductor substrate 1 on both sides of the gate electrode 5.

Thus, depletion and enhancement coding are performed to implement a NAND ROM.

Figure 2a is a graph showing the operating characteristics of the depletion transistor according to the prior art, Figure 2b is a graph showing the operating characteristics of the enhancement transistor according to the prior art, the depletion transistor does not need to apply a voltage to the gate electrode The channel is formed and the enhancement transistor shows that the channel is formed only when the threshold voltage is applied to the gate electrode.

However, the conventional ROM coding method as described above has the following problems.

First, the process of coding ion implantation is complicated.

Second, as the size of the device is downsized, breakdown due to the punch-throw phenomenon occurs, thereby reducing the reliability of the device.

An object of the present invention is to provide a ROM coding method suitable for simplifying the process and improving the degree of integration and device reliability.

1a to 1c is a process diagram showing a conventional ROM coding method.

2a to 2b are graphs showing the operation characteristics of the depletion and enhancement transistor according to the prior art.

3a to 3g is a process chart showing the ROM coding method of the present invention.

4A to 4B are graphs showing the operating characteristics of the depletion and enhancement transistor according to the present invention.

* Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate insulating layer 34: polysilicon layer

34a: gate electrode 35, 36 source / drain impurity region

In the ROM coding method of the present invention for achieving the above object, in the coding of a ROM having a depletion transistor and an enhancement transistor, a depletion ion implantation of a second conductive type is applied to a first conductive type substrate. Performing a step of selectively forming a plurality of element isolation regions in a predetermined portion of the substrate, implanting field conduction of a first conductivity type into the entire surface including the element isolation region, and the enhancement transistor Selectively removing a portion of the device isolation region of the region to be formed, and sequentially forming a gate insulating layer and a polysilicon layer on the entire surface including the substrate, and then selectively removing a plurality of gate electrodes in the active region on the substrate. And forming a source / drain impurity region in the substrate on both sides of the gate electrode.

Hereinafter, the ROM coding method of the present invention will be described with reference to the accompanying drawings.

3A to 3G are process charts showing the ROM coding method as shown, and FIG. 4 is a graph showing the operation characteristics of the depletion type and enhancement type transistors according to the present invention.

First, as shown in FIG. 3A, an N conductivity type depletion ion implantation is performed in the P conductive semiconductor substrate 31 to adjust the threshold voltage of the depletion transistor.

Subsequently, as shown in FIG. 3B, a plurality of field oxide films 32 are selectively formed in predetermined regions on the P conductive semiconductor substrate 31 for isolation between the elements.

As shown in FIG. 3C, P-conductive field ions are implanted into the entire surface of the semiconductor substrate 31 including the field oxide film 32. As shown in FIG.

At this time, the field ion increases the breakdown voltage of the depletion transistor and determines the threshold voltage Vt of the enhancement transistor.

Subsequently, as shown in FIG. 3D, the field oxide film 32 of the portion where the enhancement transistor is to be formed is etched by a predetermined portion to expose the substrate 31.

In this case, in the selective etching of the field oxide layer 32, a channel portion is used as an interface of the field oxide layer 32, thereby forming a curved channel.

Subsequently, as shown in FIG. 3E, the gate insulating layer 33 is formed on the entire surface of the substrate 31 including the field oxide film 32, and then the polysilicon layer 34 is sequentially formed on the gate insulating layer 33. do.

As shown in FIG. 3F, a photoresist (not shown) is applied onto the polysilicon layer 34, and then the polysilicon layer 34 is selectively removed through a photolithography process. Electrodes 34a are formed.

Next, source / drain impurity ions are implanted using the gate electrodes 34a as a mask to form source / drain impurity regions 35 and 36 in the semiconductor substrate 31 on both sides of the gate electrode 34a.

Figure 4a is a graph showing the operating characteristics of the depletion transistor according to the present invention, Figure 4b is a graph showing the operating characteristics of the enhancement transistor according to the present invention.

That is, as shown in the figure, the punch-through phenomenon can be prevented by increasing the breakdown voltage of the depletion transistor by the field ion implantation.

As described above, the ROM coding method of the present invention has the following effects.

First, the process is simplified by coding the NAND ROM by implementing the depletion transistor and the enhancement transistor by using the step difference of the substrate. Improve reliability

Second, it reduces the number of processes because of the multi-use of one field ion.

Third, the channel length can be minimized because the curved channel is formed by using the boundary surface of the peak oxide film, thereby improving the degree of integration.

Claims (5)

In the coding of a ROM having a depletion transistor and an enhancement transistor, a step of performing depletion ion implantation of a second conductive type on a first conductive type substrate, and a plurality of elements in a predetermined portion of the substrate. Selectively forming an isolation region, implanting field conduction of a first conductivity type into the front surface including the element isolation region, and selectively removing a portion of the element isolation region in the region where the enhancement transistor is to be formed; And sequentially forming a gate insulating layer and a polysilicon layer on the entire surface including the substrate, and then selectively removing the gate insulating layer to form a plurality of gate electrodes in an active region on the substrate, and source / drain impurities in the substrate on both sides of the gate electrode. ROM coding method comprising the step of forming a region. The ROM coding method of claim 1, wherein the channel region of the enhancement transistor is curved. The ROM coding method of claim 1, wherein the first conductive type is P type and the second conductive type is N type. The ROM coding method according to claim 1, wherein the device isolation region is formed of a field oxide film. The ROM coding method of claim 1, wherein the field ion is P conductive.