KR100268924B1 - method for manufacturing semiconductor device - Google Patents

method for manufacturing semiconductor device Download PDF

Info

Publication number
KR100268924B1
KR100268924B1 KR1019970065617A KR19970065617A KR100268924B1 KR 100268924 B1 KR100268924 B1 KR 100268924B1 KR 1019970065617 A KR1019970065617 A KR 1019970065617A KR 19970065617 A KR19970065617 A KR 19970065617A KR 100268924 B1 KR100268924 B1 KR 100268924B1
Authority
KR
South Korea
Prior art keywords
region
gate electrode
semiconductor substrate
field oxide
oxide film
Prior art date
Application number
KR1019970065617A
Other languages
Korean (ko)
Other versions
KR19990047274A (en
Inventor
권우현
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970065617A priority Critical patent/KR100268924B1/en
Publication of KR19990047274A publication Critical patent/KR19990047274A/en
Application granted granted Critical
Publication of KR100268924B1 publication Critical patent/KR100268924B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent high concentrated impurity ion forming a source/drain from being injected into a field oxide layer in order to reduce leakage current and to improve insulation property. CONSTITUTION: The method includes following steps. At first field ions are injected into an isolated region of a semiconductor substrate(21). At the second step, a field oxide layer(26) is formed on the insulated region and a gate electrode is formed on an active region. At the third step, an insulator layer is formed on the front face and a photosensitive layer is formed. Then, the photosensitive layer is patterned to leave with bigger width on the field oxide layer, the insulator layer is etched back to form a sidewall on the sides of the gate. At the fifth step, a high concentration impurity region is formed with a predetermined spacing from the field ion injection region and a channel region below the gate electrode. At last, low concentration impurities are injected into both substrates of the gate electrode including the region where no high concentration impurities are injected.

Description

반도체소자의 제조방법{method for manufacturing semiconductor device}Method for manufacturing semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로 특히, LDD 구조 모스 트랜지스터의 PN접합 누설전류를 줄이고, 절연특성을 향상시킨 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a PN junction leakage current of an LDD structure MOS transistor is reduced and an insulation characteristic is improved.

이하에서 첨부된 도면을 참조하여 종래 반도체소자의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1i는 종래 반도체소자의 제조공정 단면도이다.1A to 1I are cross-sectional views of a manufacturing process of a conventional semiconductor device.

먼저, 도 1a에 나타낸 바와 같이, 반도체기판(1)상에 산화막(2)과 질화막(3)을 차례로 형성한다. 이어서, 격리영역 및 활성영역을 정의하여 격리영역의 상기 산화막(2) 및 질화막(3)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 격리영역으로 정의된 반도체기판(1)을 노출시키는 오프닝(opening) 영역(4)을 형성한다. 그다음, 상기 오프닝 영역(4)을 통해 반도체기판(1)에 임계전압값 조절을 위한 필드이온(5)을 주입한다.First, as shown in FIG. 1A, an oxide film 2 and a nitride film 3 are sequentially formed on the semiconductor substrate 1. Next, an opening for defining the isolation region and the active region to selectively pattern the oxide film 2 and the nitride film 3 in the isolation region (photolithography process + etching process) to expose the semiconductor substrate 1 defined as the isolation region. (opening) region 4 is formed. Then, the field ions 5 for controlling the threshold voltage value are implanted into the semiconductor substrate 1 through the opening region 4.

도 1b에 나타낸 바와 같이, 통상의 로코스(LOCOS : LOCal Oxidation of Silicon)공정을 사용하여 필드산화막(6)을 형성한다. 그다음, 상기 질화막(3)과 산화막(2)을 제거한다. 이때, 상기 필드산화막(6)하부로 필드이온주입영역(5a)이 형성된다.As shown in FIG. 1B, the field oxide film 6 is formed using a conventional LOCOS (LOCal Oxidation of Silicon) process. Then, the nitride film 3 and the oxide film 2 are removed. At this time, the field ion implantation region 5a is formed under the field oxide film 6.

도 1c에 나타낸 바와 같이, 상기 반도체기판(1) 전면에 채널 이온(7)을 주입한다.As shown in FIG. 1C, channel ions 7 are implanted into the entire surface of the semiconductor substrate 1.

도 1d에 나타낸 바와 같이, 상기 반도체기판(1) 전면에 게이트 산화막(8), 폴리실리콘층 및 캡 게이트 산화막(10)을 형성한다음 게이트 전극 영역을 정의하여 상기 게이트 전극 영역에만 남도록 상기 캡 게이트 산화막(10), 폴리실리콘층 및 게이트 산화막(8)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 게이트 전극(9)을 형성한다.As shown in FIG. 1D, a gate oxide layer 8, a polysilicon layer, and a cap gate oxide layer 10 are formed on the entire surface of the semiconductor substrate 1, and then a gate electrode region is defined so that the cap gate remains only in the gate electrode region. The gate electrode 9 is formed by selectively patterning the oxide film 10, the polysilicon layer and the gate oxide film 8 (photolithography process + etching process).

도 1e에 나타낸 바와 같이, 상기 반도체기판(1) 전면에 감광막(PR1)을 도포한다음 노광 및 현상공정으로 저농도 불순물 이온주입 영역 이외의 영역을 마스킹한다. 그다음, 상기 감광막(PR1)을 마스크로 이용한 이온주입공정으로 상기 반도체기판(1)에 상기 반도체기판(1)과 반대도전형의 저농도 불순물 이온을 주입하고 열처리하여 저농도 불순물 영역(11)을 형성한다. 즉, 상기 반도체기판(1)을 p형기판이라고 하였을 경우 상기 저농도 불순물 영역(11)은 n형의 불순물 이온을 주입하여 형성하는 것이다. 이때, 상기 저농도 불순물 이온이 상기 필드산화막(6) 및 게이트 전극(9)하부의 반도체기판(1)으로 소정거리만큼 확산(diffusion)된다.As shown in FIG. 1E, the photoresist film PR 1 is applied to the entire surface of the semiconductor substrate 1, and then, other than the low concentration impurity ion implantation region is masked by the exposure and development processes. Next, a low concentration impurity region 11 is formed by implanting and conducting heat treatment of the low concentration impurity ions of the opposite conductivity type to the semiconductor substrate 1 in the ion substrate using the photosensitive film PR 1 as a mask. do. That is, when the semiconductor substrate 1 is referred to as a p-type substrate, the low concentration impurity region 11 is formed by implanting n-type impurity ions. At this time, the low concentration impurity ions diffuse into the semiconductor substrate 1 under the field oxide film 6 and the gate electrode 9 by a predetermined distance.

도 1f에 나타낸 바와 같이, 상기 감광막(PR1)을 제거한다. 이어서, 상기 게이트 전극(9) 및 필드 산화막(6)을 포함한 반도체기판(1) 전면에 측벽 스페이서 형성용 산화막(12)을 형성한다.As shown in FIG. 1F, the photosensitive film PR 1 is removed. Subsequently, an oxide film 12 for forming sidewall spacers is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 9 and the field oxide film 6.

도 1g에 나타낸 바와 같이, 상기 측벽 형성용 산화막(12)을 에치백하여 상기 캡 게이트 산화막(10), 게이트 전극(9) 및 게이트 산화막(8)의 측면에 측벽 스페이서(12a)를 형성한다.As shown in FIG. 1G, the sidewall forming oxide film 12 is etched back to form sidewall spacers 12a on the side surfaces of the cap gate oxide film 10, the gate electrode 9, and the gate oxide film 8.

도 1h에 나타낸 바와 같이, 상기 게이트 전극(9)을 포함한 상기 반도체기판(1)전면에 감광막(PR2)을 도포한다음, 노광 및 현상공정으로 고농도 불순물 이온 주입 영역 이외의 영역을 마스킹한다음, 상기 감광막(PR2) 및 게이트 전극(9)과 측벽 스페이서(12a)를 마스크로 이용하여 상기 반도체기판(1)에 상기 반도체기판(1)과 반대 도전형의 고농도 불순물 이온을 주입하여 소오스/드레인 영역(13)을 형성한다.As shown in FIG. 1H, the photoresist film PR 2 is applied to the entire surface of the semiconductor substrate 1 including the gate electrode 9, and then masked a region other than the high concentration impurity ion implantation region by an exposure and development process. By using the photoresist film PR 2 , the gate electrode 9, and the sidewall spacers 12a as a mask, a high concentration of impurity ions opposite to the semiconductor substrate 1 are implanted into the semiconductor substrate 1. The drain region 13 is formed.

도 1i에 나타낸 바와 같이, 상기 감광막(PR2)을 제거한다.As shown in FIG. 1I, the photosensitive film PR 2 is removed.

도 2는 도 1h중 필드산화막(6)에 인접한 접합부 상세도이다.FIG. 2 is a detailed view of the junction adjacent to the field oxide film 6 in FIG. 1H.

즉, 종래 반도체소자를 도 2에서와 같이 상세히 살펴보면 필드산화막(6)아래의 필드이온주입영역(5a)의 일측으로 형성된 저농도 불순물 영역(11) 및 소오스/드레인 영역(13)이 "A"에서와 같이 겹치는 부분이 발생한다.That is, when the semiconductor device is described in detail as shown in FIG. 2, the low concentration impurity region 11 and the source / drain region 13 formed on one side of the field ion implantation region 5a under the field oxide film 6 are formed at “A”. The overlapping part occurs.

종래 반도체 소자의 제조방법에 있어서는 다음과 같은 문제점이 있었다.The conventional method of manufacturing a semiconductor device has the following problems.

첫째, 소오스/드레인 영역을 형성하기 위하여 고농도로 주입하는 불순물 영역과 임계전압값을 조절하기 위하여 주입한 필드이온주입영역이 계면에서 소정영역 겹치게 됨으로써 PN접합 부근에서의 이온농도가 크며 그로 인해 소오스/드레인과 반도체기판간에 역방향 전압 인가 시 필드산화막 일측 접합부(A)에서의 전기장이 커지게 되므로 누설전류가 많이 발생되는 문제점이 있었다.First, an impurity region implanted at a high concentration to form a source / drain region and a field ion implantation region implanted to control a threshold voltage value overlap a predetermined region at an interface, thereby increasing the ion concentration in the vicinity of the PN junction. When the reverse voltage is applied between the drain and the semiconductor substrate, the electric field at the junction A of one side of the field oxide film is increased, which causes a large amount of leakage current.

둘째, 게이트 전극의 양측면에 측벽 스페이서를 형성하기 위한 에치백 공정시 필드산화막 또한 식각되어 소오스/드레인 영역 형성을 위한 고농도 불순물 이온이 그만큼 더 확산됨에 따라 필드산화막으로 인한 격리 효과(절연 특성)가 저하되어 반도체소자의 신뢰성이 저하되는 문제점이 있었다.Second, in the etch back process to form sidewall spacers on both sides of the gate electrode, the field oxide film is also etched, so that the higher concentration of impurity ions for forming the source / drain regions is diffused. There is a problem that the reliability of the semiconductor device is lowered.

본 발명은 상기한 바와 같은 종래 반도체소자 제조방법의 문제점들을 해결하기 위하여 안출한 것으로 필드산화막에 인접한 영역에 소오스/드레인을 형성할 고농도 불순물 이온의 주입을 방지하여 누설전류를 줄이고, 절연특성은 향상시킨 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional semiconductor device manufacturing method as described above, to prevent the injection of high concentration impurity ions to form the source / drain in the region adjacent to the field oxide film to reduce the leakage current, improve the insulation characteristics It is an object of the present invention to provide a method for manufacturing a semiconductor device.

도 1a 내지 도 1i는 종래 반도체소자의 제조공정 단면도1A to 1I are cross-sectional views of a manufacturing process of a conventional semiconductor device.

도 2는 도 1h의 필드산화막에 인접한 접합부 상세도FIG. 2 is a detailed view of a junction adjacent to the field oxide film of FIG. 1H

도 3a 내지 도 3j는 본 발명 반도체소자의 제조공정 단면도3A to 3J are cross-sectional views of a manufacturing process of the semiconductor device according to the present invention.

도 4는 도 3i의 필드산화막에 인접한 접합부 상세도4 is a detailed view of a junction adjacent to the field oxide film of FIG. 3I.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

21 : 반도체기판 22 : 산화막21 semiconductor substrate 22 oxide film

23 : 질화막 24 : 오프닝 영역23 nitride film 24 opening area

25a : 필드이온주입영역 26 : 필드산화막25a: field ion implantation region 26: field oxide film

27 : 채널이온 28 : 게이트 산화막27: channel ion 28: gate oxide film

29 : 게이트 전극 30 : 캡 게이트 산화막29 gate electrode 30 cap gate oxide film

31a : 측벽 스페이서 32 : 저농도 불순물 영역31a: sidewall spacer 32: low concentration impurity region

33 : 소오스/드레인 영역33 source / drain regions

본 발명에 따른 반도체소자의 제조방법은 반도체기판을 준비하는 단계, 상기 반도체기판을 활성영역 및 격리영역으로 정의하는 단계, 상기 격리영역의 상기 반도체기판에 필드이온을 주입하는 단계, 상기 격리영역의 상기 반도체기판에 필드산화막을 형성하는 단계, 상기 활성영역의 상기 반도체기판에 게이트 전극을 형성하는 단계, 상기 게이트 전극 양측면에는 측벽 스페이서를 형성하고, 상기 필드산화막 및 필드산화막에 인접한 상기 반도체기판은 마스킹하는 단계, 상기 반도체기판 전면에 고농도 불순물 이온을 주입하는 단계, 상기 측벽 스페이서 및 마스킹 물질을 제거하는 단계, 상기 반도체기판 전면에 저농도 불순물 이온을 주입하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor substrate, defining the semiconductor substrate as an active region and an isolation region, injecting field ions into the semiconductor substrate of the isolation region, Forming a field oxide film on the semiconductor substrate, forming a gate electrode on the semiconductor substrate in the active region, forming sidewall spacers on both sides of the gate electrode, and masking the semiconductor substrate adjacent to the field oxide film and the field oxide film And implanting high concentration impurity ions into the front surface of the semiconductor substrate, removing the sidewall spacers and masking material, and implanting low concentration impurity ions into the front surface of the semiconductor substrate.

이와 같은 본 발명 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3j는 본 발명 반도체소자의 제조공정 단면도이다.3A to 3J are cross-sectional views illustrating a process of manufacturing the semiconductor device of the present invention.

먼저, 도 3a에 나타낸 바와 같이, 반도체기판(21)상에 산화막(22)과 질화막(23)을 차례로 형성한다. 이어서, 격리영역 및 활성영역을 정의하여 격리영역의 상기 산화막(22) 및 질화막(23)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 격리영역으로 정의된 반도체기판(21)을 노출시키는 오프닝(opening) 영역(24)을 형성한다. 그다음, 상기 오프닝 영역(24)을 통해 반도체기판(21)에 임계전압값 조절을 위한 필드이온(25)을 주입한다.First, as shown in FIG. 3A, an oxide film 22 and a nitride film 23 are sequentially formed on the semiconductor substrate 21. Next, an opening for defining the isolation region and the active region to selectively pattern the oxide layer 22 and the nitride layer 23 in the isolation region (photolithography process + etching process) to expose the semiconductor substrate 21 defined as the isolation region. (opening) region 24 is formed. Then, the field ion 25 for controlling the threshold voltage value is implanted into the semiconductor substrate 21 through the opening region 24.

도 3b에 나타낸 바와 같이, 통상의 로코스(LOCOS : LOCal Oxidation of Silicon)공정을 사용하여 필드산화막(26)을 형성한다. 그다음, 상기 질화막(23)과 산화막(22)을 제거한다. 이때, 필드산화막(26)아래에 필드이온주입영역(25a)이 형성된다.As shown in FIG. 3B, the field oxide film 26 is formed using a conventional LOCOS (LOCal Oxidation of Silicon) process. Then, the nitride film 23 and the oxide film 22 are removed. At this time, the field ion implantation region 25a is formed under the field oxide film 26.

도 3c에 나타낸 바와 같이, 상기 반도체기판(21) 전면에 채널 이온(27)을 주입한다.As shown in FIG. 3C, channel ions 27 are implanted into the entire surface of the semiconductor substrate 21.

도 3d에 나타낸 바와 같이, 상기 반도체기판(21) 전면에 게이트 절연막(28), 폴리실리콘층 및 캡 게이트 절연막(30)을 형성한후 활성영역으로 정의된 반도체기판(21)의 소정영역에만 남도록 상기 캡 게이트 절연막(30), 폴리실리콘층 및 게이트 절연막(28)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 게이트 전극(29)을 형성한다.As shown in FIG. 3D, the gate insulating film 28, the polysilicon layer, and the cap gate insulating film 30 are formed on the entire surface of the semiconductor substrate 21, and then remain only in a predetermined region of the semiconductor substrate 21 defined as an active region. The cap gate insulating layer 30, the polysilicon layer, and the gate insulating layer 28 are selectively patterned (photolithography process + etching process) to form a gate electrode 29.

도 3e에 나타낸 바와 같이, 상기 게이트 전극(29) 및 필드산화막(26)을 포함한 상기 반도체기판(21) 전면에 절연막(31)을 형성한다. 그다음, 상기 절연막(31)상에 감광막(PR21)을 도포한다음 노광 및 현상공정으로 저농도 불순물 이온주입 영역이외의 영역을 마스킹한다. 이때, 상기 필드산화막(26)상측뿐만 아니라 필드산화막(26)에 인접한 반도체기판(21) 상측의 절연막(31)상에도 상기 감광막(PR21)이 남도록 한다.As shown in FIG. 3E, an insulating film 31 is formed over the entire surface of the semiconductor substrate 21 including the gate electrode 29 and the field oxide film 26. Subsequently, the photoresist film PR 21 is coated on the insulating film 31 and then masked a region other than the low concentration impurity ion implantation region by an exposure and development process. In this case, the photoresist film PR 21 remains on the insulating film 31 on the semiconductor substrate 21 adjacent to the field oxide film 26 as well as on the field oxide film 26.

도 3f에 나타낸 바와 같이, 상기 감광막(PR21)을 마스크로 이용한 에치백공정으로 상기 게이트 전극(29)의 측면에 측벽 스페이서(31a)를 형성한다. 이때, 상기 필드산화막(26) 및 그에 인접한 영역에 형성된 감광막(PR21)하부의 절연막(31)은 식각되지 않는다.As shown in FIG. 3F, sidewall spacers 31a are formed on the side surfaces of the gate electrode 29 by an etch back process using the photoresist film PR 21 as a mask. In this case, the field oxide layer 26 and the insulating layer 31 under the photoresist layer PR 21 formed in the region adjacent thereto are not etched.

도 3g에 나타낸 바와 같이, 상기 감광막(PR21) 및 감광막(PR21)하부의 절연막(31)을 마스크로 이용한 이온주입공정으로 상기 반도체기판(21)에 상기 반도체기판(21)과 반대도전형의 고농도 불순물 이온을 주입하고 열처리하여 소오스/드레인 영역(32)을 형성한다. 이때, 상기 소오스/드레인 영역(32)이 상기 감광막(PR21)과 감광막(PR21)하부의 절연막(31)과 측벽 스페이서(31a) 때문에 필드산화막(26)하부 및 게이트 전극(29)의 아래로는 확산되지 못함을 알 수 있다.As shown in FIG. 3G, an ion implantation process using the photoresist film PR 21 and the insulating film 31 under the photoresist film PR 21 as a mask is performed on the semiconductor substrate 21, in contrast to the semiconductor substrate 21. Source / drain regions 32 are formed by implanting and conducting a high concentration of impurity ions. At this time, the bottom of the source / drain region 32 that the photoresist (PR 21) and the photoresist (PR 21) of the lower insulating film 31 and the sidewall spacer (31a), because the field oxide film 26, the lower and the gate electrode 29 It can be seen that the furnace does not diffuse.

도 3h에 나타낸 바와 같이, 상기 감광막(PR21)을 제거한다.As shown in FIG. 3H, the photosensitive film PR 21 is removed.

도 3i에 나타낸 바와 같이, 상기 게이트 전극(29) 및 필드산화막(26)을 포함한 반도체기판(21) 전면에 감광막(PR22)을 도포한다. 이어서, 저농도 불순물 이온 주입영역을 제외한 영역만 마스킹하도록 패터닝한다. 이때, 상기 게이트 전극(29) 양측면 하부의 활성영역으로 정의된 반도체기판(21)은 완전히 노출되도록 패터닝한다. 그다음, 상기 패터닝된 감광막(PR22)을 마스크로 이용한 이온주입공정으로 상기 반도체기판(21)에 상기 반도체기판(21)과 반대도전형의 저농도 불순물 이온을 주입하여 저농도 불순물 영역(33)을 형성한다. 이때, 상기 저농도 불순물 영역(33)은 상기 게이트 전극(29) 하부 및 필드산화막(26)하부로 소정거리 확산됨을 알 수 있다. 그리고, 상기한 바와 같은 저농도 불순물 영역(33)은 LDD(Lightly Doped Drain)영역이다.As shown in FIG. 3I, a photosensitive film PR 22 is coated on the entire surface of the semiconductor substrate 21 including the gate electrode 29 and the field oxide film 26. Subsequently, patterning is performed so as to mask only the region except the low concentration impurity ion implantation region. In this case, the semiconductor substrate 21 defined as an active region under both sides of the gate electrode 29 is patterned to be completely exposed. Next, a low concentration impurity region 33 is formed by implanting low concentration impurity ions opposite to the semiconductor substrate 21 into the semiconductor substrate 21 by an ion implantation process using the patterned photoresist film PR 22 as a mask. do. In this case, it can be seen that the low concentration impurity region 33 is diffused a predetermined distance under the gate electrode 29 and under the field oxide layer 26. The low concentration impurity region 33 as described above is an LDD (Lightly Doped Drain) region.

도 3j에 나타낸 바와 같이, 상기 감광막(PR22)을 제거한다.As shown in FIG. 3J, the photosensitive film PR 22 is removed.

본 발명에 따른 반도체소자의 제조방법에 있어서는 다음과 같은 효과가 있다.The manufacturing method of the semiconductor device according to the present invention has the following effects.

첫째, 소오스/드레인 영역을 형성하기 위하여 고농도로 주입하는 불순물 영역과 임계전압값을 조절하기 위하여 주입한 필드이온주입영역이 서로 겹치는 부분없이 일정한 거리를 두고 형성되므로 필드산화막과 인접 접합부에서의 PN접합 농도가 낮아 소오스/드레인과 반도체기판간에 역방향 전압 인가시 필드산화막 일측의 접합부(A)에서의 전기장이 작으므로 누설전류가 적어진다.First, since the impurity region implanted at a high concentration to form the source / drain region and the field ion implantation region implanted to control the threshold voltage value are formed at a constant distance without overlapping with each other, the PN junction at the field oxide film and the adjacent junction is formed. When the concentration is low, when the reverse voltage is applied between the source / drain and the semiconductor substrate, the electric field at the junction A of one side of the field oxide film is small, so the leakage current is small.

둘째, 게이트 전극의 양측면에 측벽 스페이서를 형성하기 위한 에치백 공정시 필드산화막상측에 절연막과 감광막이 형성되어 있으므로 에치백과 같은 식각공정시 필드산화막의 손실이 적어 활성영역간의 절연특성 저하를 방지할 수 있어 반도체소자의 신뢰성을 유지할 수 있다.Second, since the insulating film and the photosensitive film are formed on the field oxide film in the etch back process to form sidewall spacers on both sides of the gate electrode, the loss of the field oxide film during the etching process such as etch back is small, thereby preventing the deterioration of the insulating properties between the active regions. Therefore, the reliability of the semiconductor device can be maintained.

Claims (1)

반도체 기판의 격리 영역에 필드 이온을 주입하는 단계;Implanting field ions into an isolation region of the semiconductor substrate; 상기 격리 영역에 필드 산화막을 형성하고 활성 영역에 게이트 전극을 형성하는 단계;Forming a field oxide film in said isolation region and forming a gate electrode in an active region; 전면에 절연막을 형성하고 감광막을 형성하는 단계;Forming an insulating film on the entire surface and forming a photosensitive film; 상기 필드 산화막 상측에 그보다 넓은 너비로 남도록 감광막을 패터닝하고 절연막을 에치백하여 게이트 측면에 측벽을 형성하는 단계;Patterning the photoresist film so as to have a wider width above the field oxide film and etching back the insulating film to form sidewalls on the gate side; 상기 필드 이온 주입 영역 및 게이트 전극 하측의 채널 영역과 일정 거리 이격되는 고농도 불순물 영역을 형성하는 단계;Forming a high concentration impurity region spaced a predetermined distance from the field ion implantation region and the channel region under the gate electrode; 상기 고농도 불순물이 주입되지 않은 부분을 포함하는 게이트 전극의 양측기판내에 저농도 불순물을 주입하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.And injecting low-concentration impurities into both substrates of the gate electrode including a portion where the high-concentration impurities are not implanted.
KR1019970065617A 1997-12-03 1997-12-03 method for manufacturing semiconductor device KR100268924B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970065617A KR100268924B1 (en) 1997-12-03 1997-12-03 method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970065617A KR100268924B1 (en) 1997-12-03 1997-12-03 method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR19990047274A KR19990047274A (en) 1999-07-05
KR100268924B1 true KR100268924B1 (en) 2000-10-16

Family

ID=19526342

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970065617A KR100268924B1 (en) 1997-12-03 1997-12-03 method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100268924B1 (en)

Also Published As

Publication number Publication date
KR19990047274A (en) 1999-07-05

Similar Documents

Publication Publication Date Title
KR100234700B1 (en) Manufacturing method of semiconductor device
KR19980029024A (en) MOSFET and manufacturing method
KR100244967B1 (en) Semiconductor device manufacture method of dual gate
JP5220970B2 (en) Manufacturing method of high voltage transistor
KR20010016838A (en) Method of forming impurity doped region of MOS transistor
KR100257074B1 (en) Mosfet and method for manufacturing the same
KR100295914B1 (en) Method for fabricating mos transistor and structure of cmos transistor
KR100873356B1 (en) Method for forming the high voltage transistor
KR100268924B1 (en) method for manufacturing semiconductor device
KR100390907B1 (en) Method for manufacturing of semiconductor device
KR100304974B1 (en) Method for manufacturing mos transistor
KR100226770B1 (en) Manufacturing method of a semiconductor device
KR20020002012A (en) Transistor and method for manufacturing transistor
KR100304975B1 (en) Semiconductor device and method for fabricating the same
KR0167664B1 (en) Method of fabricating semiconductor device
KR0186019B1 (en) Method of processing trench capacitor cell
KR100327419B1 (en) Method for fabricating semiconductor device
KR970006219B1 (en) Fabrication method of semiconductor device
KR100192536B1 (en) Method of manufacturing mosfet
KR100261171B1 (en) Method for fabricating transistor
KR100365750B1 (en) Method for forming self aligned contact in semiconductor device
KR100487503B1 (en) A semiconductor device and method of fabricating the same
KR100214077B1 (en) Mosfet and method for fabricating the same
KR100252902B1 (en) method for fabricvating complementary metal oxide semiconductor device
KR100205342B1 (en) Coding method of rom

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080619

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee