KR100214077B1 - Mosfet and method for fabricating the same - Google Patents
Mosfet and method for fabricating the same Download PDFInfo
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- KR100214077B1 KR100214077B1 KR1019960067609A KR19960067609A KR100214077B1 KR 100214077 B1 KR100214077 B1 KR 100214077B1 KR 1019960067609 A KR1019960067609 A KR 1019960067609A KR 19960067609 A KR19960067609 A KR 19960067609A KR 100214077 B1 KR100214077 B1 KR 100214077B1
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- 238000000034 method Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- -1 oxygen ions Chemical class 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 235000012431 wafers Nutrition 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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Abstract
1. 청구범위에 기재된 발명이 속한 분야1. Fields to which the invention described in the claims belong
반도체 소자 제조.Semiconductor device manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
SOI형 MOSFET에 있어서 얇은 SOI층위에 게이트와 소오스 및 드레인이 형성되기 때문에 소오스와 드레인간의 직렬저항이 매우 크게 되고, 또한 짧은 채널 효과를 억제할 수 있는 얇은 채널영역을 형성할 수 없는 문제점을 해결하기 위함.In the SOI type MOSFET, since the gate, the source, and the drain are formed on the thin SOI layer, the series resistance between the source and the drain becomes very large, and the thin channel region capable of suppressing the short channel effect cannot be solved. To.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
기판내에 이온주입에 의해 절연층을 형성함으로써 소오스 및 드레인영역을 두껍게 하여 소오스와 드레인간의 직렬저항을 낮추고, 채널영역은 그 두께를 얇게 하여 짧은 채널 효과를 효과적으로 억제할 수 있다.By forming an insulating layer by ion implantation in the substrate, the source and drain regions can be thickened to reduce the series resistance between the source and drain, and the channel regions can be made thin so that the short channel effect can be effectively suppressed.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 제조에 이용됨.Used in the manufacture of semiconductor devices.
Description
본 발명은 모스트랜지스터 및 그 제조방법에 관한 것으로, 특히 소오스와 드레인간의 직렬저항(series resistance)을 감소시킬 수 있는 SOI(silicon on insulator)형 MOSFET 및 이의 제조방법에 관한 것이다.The present invention relates to a MOS transistor and a method for manufacturing the same, and more particularly, to a silicon on insulator (SOI) type MOSFET capable of reducing series resistance between a source and a drain, and a method for manufacturing the same.
종래의 벌크실리콘 웨이퍼를 사용한 MOSFET에 비해 SOI웨이퍼를 사용한 MOSFET는 낮은 동작전압, 낮은 문턱전압 조절 및 낮은 소비전력의 장점을 가지고 있다.MOSFETs using SOI wafers have the advantages of low operating voltage, low threshold voltage regulation and low power consumption compared to conventional bulk silicon wafer MOSFETs.
종래의 SOI웨이퍼를 사용한 MOSFET 제조방법을 도 1A 내지 도 1C를 참조하여 설명하면 다음과 같다.Referring to FIGS. 1A to 1C, a MOSFET manufacturing method using a conventional SOI wafer is as follows.
먼저, 도 1A에 나타낸 바와 같이 반도체웨이퍼(1)상에 2000-5000Å 두께의 매몰산화막(2)과 1000-3000Å 두께의 SOI층(3)을 형성하여 SOI웨이퍼를 형성한 후, 도 1B에 나타낸 바와 같이 소자분리공정을 통해 소정영역에 필드산화막(4)을 형성한다.First, as shown in FIG. 1A, a buried oxide film 2 having a thickness of 2000-5000 kPa and an SOI layer 3 having a thickness of 1000-3000 kPa are formed on the semiconductor wafer 1, and then the SOI wafer is formed in FIG. 1B. As described above, the field oxide film 4 is formed in the predetermined region through the device isolation process.
이어서 도 1C에 나타낸 바와 같이 상기 SOI층(3)상에 게이트산화막(5)과 게이트전극(6)을 차례로 형성한 후, 이온주입을 행하여 상기 게이트전극 양단의 SOI층 부위에 소오스 및 드레인(7)을 형성한다.Subsequently, as shown in FIG. 1C, the gate oxide film 5 and the gate electrode 6 are sequentially formed on the SOI layer 3, and ion implantation is performed to source and drain the portions of the SOI layer across the gate electrode. ).
상기한 종래기술에 의해 제조되는 SOI형 MOSFET는 얇은 SOI층위에 게이트와 소오스 및 드레인이 형성되기 때문에 소오스와 드레인간의 직렬저항이 매우 크게 되고, 또한 짧은 채널 효과(short channel effect)를 억제할 수 있는 얇은 채널영역을 형성할 수 없는 문제점이 있다.In the SOI type MOSFET manufactured by the above-described conventional technology, since the gate, the source, and the drain are formed on the thin SOI layer, the series resistance between the source and the drain is very large, and the short channel effect can be suppressed. There is a problem that a thin channel region cannot be formed.
본 발명은 소오스와 드레인간의 직렬저항을 낮출수 있고, 짧은 채널 효과를 억제시킬 수 있도록 얇은 채널영역을 가지는 SOI형 MOSFET 및 이의 제조방법을 제공하는 것을 그 목적으로 한다.It is an object of the present invention to provide an SOI type MOSFET having a thin channel region and a method of manufacturing the same, which can lower the series resistance between the source and the drain and suppress a short channel effect.
상기 목적을 달성하기 위한 모스트랜지스터는 제1도전형의 반도체기판과, 상기 반도체기판상에 형성된 산화막, 상기 산화막상에 위치하며 소정두께의 채널영역과 이 채널영역 양측에 형성된 채널영역보다 두꺼운 두께를 갖는 제2도전형의 소오스 및 드레인영역으로 이루어진 활성층, 및 상기 활성층의 채널영역상부에 게이트산화막을 개재하여 형성된 게이트전극을 포함하여 구성된다.In order to achieve the above object, a MOS transistor has a semiconductor substrate of a first conductivity type, an oxide film formed on the semiconductor substrate, a channel region having a predetermined thickness, and a thickness thicker than a channel region formed on both sides of the channel region. And a gate electrode formed on the channel region of the active layer via a gate oxide film.
상기 목적을 달성하기 위한 모스트랜지스터 제조방법은 제1도전형 반도체웨이퍼와 그 상부에 형성된 산화막과 SOI층으로 이루어진 SOI웨이퍼에 산소이온을 주입하는 단계와, 어닐링에 의해 상기 주입된 산소이온을 산화시켜 상기 산화막과 인접한 상기 SOI층하부에 산화층을 형성하는 단계, 상기 SOI층상에 게이트산화막과 게이트전극을 차례로 형성하는 단계, 소오스 및 드레인 형성을 위한 제2도전형 불순물의 이온주입을 행하는 단계, 및 샐리사이드공정을 행하는 단계를 포함하여 구성된다.In order to achieve the above object, a method of manufacturing a morph transistor includes injecting oxygen ions into an SOI wafer including a first conductive semiconductor wafer, an oxide film formed on an upper portion thereof, and an SOI layer, and oxidizing the injected oxygen ions by annealing. Forming an oxide layer under the SOI layer adjacent to the oxide film, sequentially forming a gate oxide film and a gate electrode on the SOI layer, performing ion implantation of a second conductive impurity for source and drain formation, and sally It comprises a step of performing a side process.
도 1A 내지 도 1C는 종래기술에 의한 SOI형 MOSFET 제조방법을 도시한 공정순서도,1A to 1C are process flowcharts showing a method for manufacturing a SOI type MOSFET according to the prior art;
도 2는 본 발명에 의한 SOI형 MOSFET의 단면구조도,2 is a cross-sectional structure diagram of an SOI type MOSFET according to the present invention;
도 3A 내지 도 3E는 본 발명에 의한 SOI형 MOSFET 제조방법을 도시한 공정순서도.3A to 3E are process flowcharts showing a method for fabricating an SOI type MOSFET according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11:p형 반도체기판 12:산화막11: p-type semiconductor substrate 12: oxide film
13:채널영역,SOI층 17:산화층13: channel region, SOI layer 17: oxide layer
18:게이트산화막 19:게이트전극18: gate oxide film 19: gate electrode
21:산화막 스페이서 24:n+ 소오스 및 드레인영역21: oxide spacer 24: n + source and drain region
25:샐리사이드층25: salicide layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2에 본 발명의 일실시예에 의한 SOI형 NMOS트랜지스터의 단면구조를 나타내었다.2 shows a cross-sectional structure of an SOI type NMOS transistor according to an embodiment of the present invention.
본 발명에 의한 SOI형 NMOS트랜지스터는 p형 반도체기판(11)과, 상기 반도체기판(11)상에 형성된 산화막(12), 상기 산화막(12)상에 위치하며 소정두께의 채널영역(13)과 이 채널영역 양측에 형성된 채널영역보다 두꺼운 두께를 갖는 n+ 소오스 및 드레인영역(24)으로 이루어진 활성층, 및 상기 활성층의 채널영역상부에 게이트산화막(18)을 개재하여 형성된 게이트전극(19)으로 구성된다.The SOI type NMOS transistor according to the present invention includes a p-type semiconductor substrate 11, an oxide film 12 formed on the semiconductor substrate 11, a channel region 13 having a predetermined thickness, and a channel region 13 having a predetermined thickness. An active layer having a thicker n + source and drain region 24 than the channel region formed on both sides of the channel region, and a gate electrode 19 formed on the channel region of the active layer with a gate oxide film 18 interposed therebetween. .
상기 활성층의 채널영역의 두께는 500-1000Å 정도로 얇으며, 소오스 및 드레인영역(24)은 3000-5000Å 정도의 두께를 가진다. 상기 활성층은 SOI웨이퍼의 SOI층에 형성된다.The thickness of the channel region of the active layer is as thin as 500-1000Å, and the source and drain region 24 has a thickness of about 3000-5000Å. The active layer is formed on the SOI layer of the SOI wafer.
상기 게이트전극(19)과 소오스 및 드레인(24) 상부에는 샐리사이드층(25)이 형성된다.The salicide layer 25 is formed on the gate electrode 19 and the source and drain 24.
이와 같이 본 발명의 SOI형 MOSFET는 소오스 및 드레인영역이 종래에 비해 두껍게 형성되므로 소오스와 드레인간의 직렬저항을 낮출 수 있으며, 채널영역은 그 두께가 얇아 짧은 채널 효과를 효과적으로 억제할 수 있다.As described above, in the SOI type MOSFET of the present invention, since the source and drain regions are formed thicker than in the related art, the series resistance between the source and the drain can be lowered, and the channel region is thin, so that the short channel effect can be effectively suppressed.
도 3A 내지 도 3E를 참조하여 본 발명의 일실시예에 의한 SOI형 NMOS 제조방법을 설명하면 다음과 같다.Referring to FIGS. 3A to 3E, a method of manufacturing an SOI NMOS according to an embodiment of the present invention is as follows.
먼저, 도 3A에 나타낸 바와 같이 p형 반도체웨이퍼(11)와 그 상부에 형성된 매몰산화막(12)과 SOI층(13)으로 이루어진 SOI웨이퍼상의 소정영역에 소자분리공정을 통해 필드산화막(도시하지 않음)을 형성한다. 상기 매몰산화막(12)과 SOI층(13)은 각각 3000-5000Å정도의 두께로 형성한다. 이어서 상기 SOI층(13)상에 패드산화막(14)을 형성하고, 그위에 포토레지스트를 도포하고 이를 선택적으로 노광 및 현상하여 기판의 소정부분을 선택적으로 노출시키는 포토레지스트 마스크패턴(15)을 형성한다. 상기 노출되는 기판 부위는 후속공정에서 게이트전극이 형성될 영역에 해당한다. 그런 다음, O2이온주입(16)을 실시한 후, 상기 포토레지스트 마스크패턴을 제거하고 어닐링에 의해 상기 주입된 O2이온을 산화시켜 도 3B에 나타낸 바와 같이 SOI층(3)의 매몰산화막(12)과 인접한 부분에 산화층(17)을 형성한다. 이때, 상기 산화층(17)은 SOI층(13)의 표면으로부터 500-1000Å 깊이에 형성되도록 이온주입 에너지를 조절하여 이온주입을 행한다. 이어서 상기 패드산화막을 제거한다. 이와 같이 산화층(17)을 형성함으로써 이 산화층이 형성된 부위의 SOI층(13)은 산화층의 두께만큼 그 두께가 얇아지게 된다. 즉, 500-1000Å 정도의 두께를 가지게 된다.First, as shown in FIG. 3A, a field oxide film (not shown) is formed through a device isolation process in a predetermined region on the SOI wafer including the p-type semiconductor wafer 11, the buried oxide film 12 and the SOI layer 13 formed thereon. ). The buried oxide film 12 and the SOI layer 13 are each formed to a thickness of about 3000-5000 kPa. Subsequently, a pad oxide layer 14 is formed on the SOI layer 13, a photoresist is applied thereon, and a photoresist mask pattern 15 is formed to selectively expose a predetermined portion of the substrate by selectively exposing and developing the photoresist. do. The exposed substrate portion corresponds to a region where a gate electrode is to be formed in a subsequent process. Then, after performing the O 2 ion implantation 16, the photoresist mask pattern is removed, and the implanted O 2 ions are oxidized by annealing to bury the buried oxide film 12 of the SOI layer 3 as shown in FIG. 3B. The oxide layer 17 is formed in the part adjacent to the (). At this time, the oxide layer 17 is implanted by adjusting the ion implantation energy to be formed at a depth of 500-1000 Å from the surface of the SOI layer (13). Subsequently, the pad oxide film is removed. By forming the oxide layer 17 in this manner, the thickness of the SOI layer 13 in the portion where the oxide layer is formed is reduced by the thickness of the oxide layer. That is, it has a thickness of about 500-1000Å.
다음에 도 3C에 나타낸 바와 같이 상기 SOI층(13)상에 게이트산화막(18)을 형성하고, 그위에 게이트전극 형성용 폴리실리콘을 증착하고 이를 도핑한 다음 소정의 게이트전극 마스크(도시하지 않음)를 이용한 사진식각공정을 통해 상기 폴리실리콘층 및 게이트산화막을 패터닝하여 상기 산화층(17) 상부에 게이트전극(19)을 형성한다. 이어서 소오스 및 드레인 형성을 위하여 n형 불순물을 고농도로 이온주입한다.Next, as shown in FIG. 3C, a gate oxide film 18 is formed on the SOI layer 13, a polysilicon for forming a gate electrode is deposited thereon, and doped thereon, followed by a predetermined gate electrode mask (not shown). The polysilicon layer and the gate oxide layer are patterned through a photolithography process to form a gate electrode 19 on the oxide layer 17. Next, n-type impurities are implanted at high concentration to form a source and a drain.
이어서 도 3D에 나타낸 바와 같이 절연층으로서, 예컨대 산화막을 상기 기판 전면에 형성한 후, 블랭킷 에치(blanket etch)하여 상기 게이트전극(19) 양측면에 200-500Å두께의 얇은 산화막 스페이서(21)를 형성한다. 이 산화막 스페이서는 게이트전극과 소오스 및 드레인을 분리시켜 후속공정에서 샐리사이드(salicide;self-align silicide)를 게이트전극과 소오스 및 드레인영역 상부에 형성할수 있도록 하기 위한 것이다.Subsequently, as shown in FIG. 3D, an oxide film is formed on the entire surface of the substrate, for example, and then blanket etched to form a thin oxide spacer 21 having a thickness of 200-500 에 on both sides of the gate electrode 19. do. The oxide spacer is to separate the gate electrode, the source and the drain so that a salicide (self-aligned silicide) can be formed on the gate electrode, the source and the drain region in a subsequent process.
다음에 샐리사이드 공정을 수행하면, 도 3E에 나타낸 바와 같이 게이트전극(19) 상부에 샐리사이드층(25)이 형성되고, 상기 이온주입된 n형 불순물이 활성화되어 SOI층(13)에 n+소오스 및 드레인영역(24)이 형성됨과 동시에 소오스 및 드레인영역(24) 상부에도 샐리사이드층(25)이 형성되게 된다.Next, when the salicide process is performed, as shown in FIG. 3E, the salicide layer 25 is formed on the gate electrode 19, and the ion implanted n-type impurity is activated to n + source in the SOI layer 13. The drain region 24 is formed, and the salicide layer 25 is formed on the source and drain regions 24.
상술한 바와 같이 본 발명에 의하면, 종래보다 2배정도 두꺼운 SOI층(3000-5000Å)을 가진 SOI웨이퍼를 사용하여 MOSFET를 형성하므로 소오스와 드레인간의 직렬저항을 낮출 수 있으며, 채널영역에 해당하는 SOI층(13)은 그 하부에 이온주입에 의해 형성된 산화층(17)에 의해 그 두께가 얇아지므로(500-1000Å) 짧은 채널 효과를 효과적으로 억제할 수 있게 된다.As described above, according to the present invention, since the MOSFET is formed by using an SOI wafer having a SOI layer (3000-5000 Å) that is about twice as thick as before, the series resistance between the source and the drain can be lowered, and the SOI layer corresponding to the channel region can be reduced. (13) becomes thinner (500-1000 kPa) by the oxide layer 17 formed by ion implantation in the lower portion thereof, so that the short channel effect can be effectively suppressed.
한편, 상기 실시예에서는 NMOS의 경우를 설명하였으나, PMOS에도 본 발명을 적용할 수 있음은 물론이며, 이 경우에는 이온주입시의 불순물의 도전형을 반대로 하면 된다.On the other hand, in the above embodiment, the case of the NMOS has been described, but the present invention can be applied to the PMOS as well. In this case, the conductivity type of the impurity at the time of ion implantation can be reversed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, SOI형 MOSFET에 있어서 소오스와 드레인간의 직렬저항을 낮출 수 있고, 채널영역을 얇게 형성함으로써 짧은 채널 효과를 효과적으로 억제할 수 있게 되므로 결과적으로 향상된 특성을 가지는 SOI형 MOSFET를 구현할 수 있다.According to the present invention, it is possible to reduce the series resistance between the source and the drain in the SOI-type MOSFET, and to effectively suppress the short channel effect by forming the channel region thin, thereby realizing the SOI-type MOSFET having improved characteristics. .
Claims (10)
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