KR100304974B1 - Method for manufacturing mos transistor - Google Patents

Method for manufacturing mos transistor Download PDF

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KR100304974B1
KR100304974B1 KR1019930003646A KR930003646A KR100304974B1 KR 100304974 B1 KR100304974 B1 KR 100304974B1 KR 1019930003646 A KR1019930003646 A KR 1019930003646A KR 930003646 A KR930003646 A KR 930003646A KR 100304974 B1 KR100304974 B1 KR 100304974B1
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insulating film
forming
gate
mos transistor
region
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KR1019930003646A
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KR940022829A (en
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김영기
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김영환
현대반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A fabrication method of MOS(Metal Oxide Semiconductor) transistors is provided to prevent a GILD(Gate Induced Drain Leakage), a punch-through and a hot carrier by forming dual insulating spacers. CONSTITUTION: After forming a field oxide on a semiconductor substrate, a step-shaped active region is formed by selectively removing the field oxide. A first insulating layer is formed on the gate formation region. A first insulating spacer(6) is formed at both sidewalls of the first insulating layer. After removing the first insulating layer, a gate insulating layer(7) and a gate electrode(8a) are sequentially formed on the gate formation region and the first insulating spacer(6). After forming an LDD(Lightly Doped Drain) region in the semiconductor substrate, a second insulating spacer is formed at both sidewalls of the gate insulating layer(7) and the gate electrode(8a). Then, heavily doped source and drain regions are formed by using the gate electrode(8a) and the second insulating spacer as a mask.

Description

모스 트랜지스터의 제조방법Manufacturing method of MOS transistor

제1도는 종래의 트랜지스터 제조 공정 단면도.1 is a cross-sectional view of a conventional transistor manufacturing process.

제2도는 본 발명의 트랜지스터 제조 공정 단면도.2 is a cross-sectional view of a transistor manufacturing process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 제1도전형 반도체 기판 2 : 필드산화막DESCRIPTION OF SYMBOLS 1 First conductive semiconductor substrate 2 Field oxide film

3 : 채널스톱층 4, 9 : 포토레지스트3: channel stop layer 4, 9: photoresist

5 : 제1절연막 6, 10 : 제1, 2측벽절연막5: first insulating film 6, 10: first and second side wall insulating film

7 : 제2절연막 8 : 제1도전체7: second insulating film 8: first conductor

8a : 게이트 11 : 저농도 소오스/드레인 영역8a: Gate 11: low concentration source / drain region

11a : LDD 12 : 고농도 소오스/드레인 영역11a: LDD 12: high concentration source / drain region

본 발명은 금속-산화물-반도체(MOS) 트랜지스터 제조에 관한 것으로 특히, LDD(Lightly Doped Drain) 구조를 갖는 MOS 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of metal-oxide-semiconductor (MOS) transistors, and more particularly, to a method of manufacturing a MOS transistor having a lightly doped drain (LDD) structure.

제1도는 종래의 MOS(Metal Oxide Semiconductor)트랜지스터 제조방법을 설명하기 위한 공정 단면도로서, 제1(a)도와 같이 제1도전형 반도체 기판(P형 반도체 기판)(1)상에 필드산화막(2)을 형성하여 활성 영역을 정의하고, 상기 필드산화막(2)의 하단 제1도전형 반도체 기판(1)에 고농도의 불순물 이온(P+)(제1도전형 불순물)을 주입하여 채널 스톱층(Channel Stop Layer)(3)을 형성한 다음, 전표면에 제1절연막(예로서 Si3N4)(5)을 증착하고 포토-에칭 공정으로 선택된 제1도전형 반도체 기판(1)의 게이트 영역이 노출되도록 제1절연막(5)을 패터닝한후, 상기 게이트 영역에 문턱전압(Threshold Voltage)조절을 위한 저농도의 불순물 이온(N-)(제2도전형 불순물)을 주입한다.FIG. 1 is a cross-sectional view illustrating a conventional method of manufacturing a metal oxide semiconductor (MOS) transistor. As shown in FIG. 1A, a field oxide film 2 is formed on a first conductive semiconductor substrate (P type semiconductor substrate) 1. ) To define an active region, and implant a high concentration of impurity ions P + (first conductive impurity) into the first conductive semiconductor substrate 1 at the bottom of the field oxide film 2 to stop the channel stop layer ( After forming a channel stop layer (3), the gate region of the first conductive semiconductor substrate 1 selected by the photo-etching process is deposited by depositing a first insulating film (for example, Si 3 N 4 ) 5 on the entire surface. After patterning the first insulating layer 5 to expose the light, a low concentration of impurity ions N − (second conductive impurity) is implanted into the gate region to control a threshold voltage.

그 다음 제1(b)도와 같이 전표면에 절연막을 증착하고, 에치 백(Etch Back)하여 제1절연막(5)의 식각된 측면에 제1측벽절연막(예로서 SiO2)(6)을 형성한다.Then, an insulating film is deposited on the entire surface as shown in FIG. 1 (b) and etched back to form a first side wall insulating film (for example, SiO 2 ) 6 on the etched side of the first insulating film 5. do.

이어, 전표면에 제2절연막(SiO2)(7)을 형성하고, 제2절연막(7)상에 게이트 형성 물질로서 제1도전체(폴리실리콘)(8)을 증착한다.Next, a second insulating film (SiO 2 ) 7 is formed on the entire surface, and a first conductor (polysilicon) 8 is deposited on the second insulating film 7 as a gate forming material.

그 다음, 제1(c)도와 같이 포토-에칭 공정을 수행하여 제1도전체(8)와 제2절연막(7)중 게이트 형성 영역을 제외한 나머지 부분을 제거하여, 게이트(폴리실리콘)(8a)를 형성한후, 상기 게이트(8a)를 마스크로 하여, 제1도전형 반도체 기판(1)상에 고농도의 불순물 이온(N+)을 주입하여 소오스/드레인 영역(10)을 형성한다.Then, a photo-etching process is performed as shown in FIG. 1 (c) to remove the remaining portions of the first conductor 8 and the second insulating film 7 except for the gate forming region, thereby removing the gate (polysilicon) 8a. ), And then the source / drain region 10 is formed by implanting a high concentration of impurity ions N + on the first conductive semiconductor substrate 1 using the gate 8a as a mask.

이와같이 제조되는 종래의 트랜지스터는 게이트의 양측 하단 모서리에 두꺼운 측벽 절연막을 형성시킨 것으로, 이 측벽 절연막을 이용하여 채널길이를 조절함으로써 숏 채널(Short channel)소자를 제조한다.Conventional transistors manufactured as described above have thick sidewall insulating films formed on both bottom edges of gates, and short channel devices are manufactured by controlling channel lengths using the sidewall insulating films.

그러나 상기와 같은 종래의 기술은 게이트에 전압을 인가했을 때 드레인과 게이트간에 누설전류가 흐르는 GIDL(Gate Induced Drain Leakage)현상을 방지하는 효과는 있으나, 숏 채널 효과(Short Channel Effect)로 인한 펀치-드루(punch-through) 및 핫 캐리어(Hot carrier)의 발생을 방지하는데에는 문제가 있다.However, the conventional technique described above has an effect of preventing a gate induced drain leakage (GIDL) phenomenon in which a leakage current flows between the drain and the gate when a voltage is applied to the gate, but the punch due to the short channel effect There is a problem in preventing the occurrence of punch-through and hot carriers.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로, 게이트 측벽 절연막을 두껍게 형성시켜, 펀치-드루(punch-through) 및 핫 캐리어(Hot Carrier)발생을 방지하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to form a thick gate sidewall insulating film to prevent punch-through and hot carrier generation.

이와같은 목적을 달성하기 위한 본 기술은 필드산화막의 일부를 제거하여, 제1도전형 반도체 기판상의 평면과, 필드산화막 제거로 생긴 오목한 부분을 활성 영역으로 이용함과 게이트 측벽 절연막을 이중으로 형성하는 것이 특징이다.The present technology for achieving the above object is to remove a part of the field oxide film, to use a plane on the first conductive semiconductor substrate, a concave portion resulting from the field oxide film removal as an active region, and to form a double gate sidewall insulating film. It is characteristic.

제2도는 본 발명의 트랜지스터 제조 방법을 설명하기 위한 공정 단면도로서, N채널 MOS를 예로들어 설명하면 다음과 같다.2 is a cross-sectional view illustrating a method of manufacturing a transistor of the present invention, which will be described below using an N-channel MOS as an example.

제2(a)도와 같이 제1도전형 반도체 기판(1)(P형 반도체 기판)위에 필드산화막(2)을 4000~7500Å 정도의 두께로 형성한후, 상기 필드산화막(2)의 하단 제1도전형 반도체기판(1)에 채널스톱층(3)을 형성하기 위해 고농도의 불순물 이온(P+)(제1도전형 불순물)을 주입한다.As shown in FIG. 2A, after forming the field oxide film 2 on the first conductive semiconductor substrate 1 (P type semiconductor substrate) to a thickness of about 4000 to 7500 kPa, the first lower end of the field oxide film 2 is formed. In order to form the channel stop layer 3 on the conductive semiconductor substrate 1, a high concentration of impurity ions P + (first conductive impurity) is implanted.

그리고 제2(b)도와 같이 전표면에 포토 레지스트(4)를 도포하고, 포토-에칭 공정을 수행하여 선택된 필드산화막(2) 영역을 제거하여 계단형으로 활성 영역을 형성한다.Then, as shown in FIG. 2 (b), the photoresist 4 is applied to the entire surface and a photo-etching process is performed to remove the selected field oxide film 2 region to form an active region stepwise.

그 다음 제2(c)도와 같이 전표면에 제1절연막(5)(예로서 Si3N4)을 증착한 다음, 상기 제1절연막(5)의 선택 영역을 포토-에칭 공정으로 제거하여 게이트 영역을 형성하고, 상기 노출된 영역에 문턱 전압 조절을 위한 저농도의 불순물 이온(n_)(제2도전형 불순물)을 주입하고, 제2(d)도와 같이 노출된 전표면에 산화막을 형성한후, 에치 백(Etch back)하여 상기 제1절연막(5)의 식각된 측면 및 계단 부위에 제1측벽절연막(6)(예로서 SiO2)을 2000~4000Å 정도의 두께로 형성한다.Next, as shown in FIG. 2 (c), the first insulating film 5 (for example, Si 3 N 4 ) is deposited on the entire surface, and then the selected region of the first insulating film 5 is removed by a photo-etching process. Forming a region, implanting a low concentration of impurity ions (n _ ) (second conductive impurity) for adjusting the threshold voltage into the exposed region, and forming an oxide film on the exposed entire surface as shown in FIG. After etching, the first side wall insulating film 6 (for example, SiO 2 ) is formed on the etched side surface and the stepped portion of the first insulating film 5 to a thickness of about 2000 to 4000 Å.

이때 생성된 계단 부위의 산화막은 포토-에칭 공정으로 제거한다.At this time, the oxide film of the stepped portion is removed by a photo-etching process.

그 다음 제2(e)도와 같이 활성 영역에 제2절연막(예로서 SiO2)(7)을 800~1000Å의 온도범위에서 100~500Å 정도의 두께로 열산화시킨 다음, 상기 제2절연막(7)위에 게이트 전극용 제1도전체(폴리실리콘)(8)을 2000~5000Å 정도의 두께로 증착한다.Next, as shown in FIG. 2 (e), the second insulating film (for example, SiO 2 ) 7 is thermally oxidized to a thickness of about 100 to 500 kPa in the temperature range of 800 to 1000 kPa, and then the second insulating film 7 ), A first conductor (polysilicon) 8 for the gate electrode is deposited to a thickness of about 2000 to 5000 mW.

그 다음, 제2(f)도와 같이 게이트 영역을 정의하기 위해 제1도전체(8) 상측에 포토 레지스트(9)를 도포하고, 게이트 영역을 마스킹하도록 패턴을 형성한후, 제1도전체(8)와 제2절연막(7)과 제1절연막(5)을 선택적으로 식각하여 게이트(8a)(폴리실리콘)을 형성한다.Next, as shown in FIG. 2 (f), a photoresist 9 is applied on the upper side of the first conductor 8 to define the gate region, and a pattern is formed to mask the gate region. 8), the second insulating film 7 and the first insulating film 5 are selectively etched to form a gate 8a (polysilicon).

그 다음 LDD 구조를 형성하기 위해 선택 영역에 저농도(0.5~3×1013atom/㎠)의 불순물 이온(n-)(경사지게)을 주입한 다음, 제2(g)도와 같이 다시 게이트 측벽을 형성하기 위해 노출된 전표면에 절연막을 형성하고, 에치 백(Etch back)하여 제2측벽 절연막(10)(예로서 SiO2)을 형성한 다음, 소오스/드레인 영역에 고농도(2~6×1015atom/㎠)의 불순물 이온(n+)을 주입하여 제2(h)도와 같이 고농도의 소오스/드레인영역(12)을 형성한다.Next, to form an LDD structure, a low concentration (0.5-3 × 10 13 atom / cm 2) of impurity ions (n − ) (beveled) is implanted into the selected region, and then the gate sidewall is formed again as shown in FIG. 2 (g). In order to form an insulating film on the exposed entire surface, the film is etched back to form a second sidewall insulating film 10 (for example, SiO 2 ), and then a high concentration (2 to 6 x 10 15 ) is applied to the source / drain regions. atom / cm 2) impurity ions (n + ) are implanted to form a high concentration source / drain region 12 as shown in FIG. 2 (h).

이때, 게이츠 양측면 하단에는 소오스/드레인 이온 주입시 제2측벽절연막(10)의 마스킹 작용에 의해 저농도 접합층이 보호되어 LDD(11a) 구조가 형성된다.At this time, the low concentration bonding layer is protected by the masking action of the second side wall insulating film 10 at the source / drain ion implantation at the lower ends of both gates, thereby forming the LDD 11a structure.

상기 n채널 MOS 트랜지스터 제조방법은 P채널 MOS에도 적용되며, 주입 불순물의 종류만 반대형으로 바꾸어주면 되고, P형 불순물은 제1도전형 n형 불순물 제2도전형 불순물이다.The n-channel MOS transistor manufacturing method is also applied to P-channel MOS, and only the type of implanted impurities needs to be changed to the opposite type, and the P-type impurity is the first conductive n-type impurity and the second conductive impurity.

이와같은 본 발명은, 게이트 에지의 산화막 두께가 두꺼워 게이트(8a)에 전압 인가시, 드레인과 게이트간에 발생하는 누설전류[GIDL(Gate Induced Drain Leakage)]를 방지할 수 있고, LDD 구조를 형성하고 있기 때문에 핫 캐리어(Hot Carrier) 효과를 방지할 수 있고 필드산화막 하단에 채널 스톱 이온 주입으로 채널영역과 반대형의-불순물의 고농도 접합층이 형성되어 있어 소자의 고집적화에 따른 펀치-드루(punch through)현상을 막을수 있는 효과가 있다.The present invention can prevent the leakage current (GIDL (Gate Induced Drain Leakage)) generated between the drain and the gate when the voltage is applied to the gate 8a due to the thick oxide film thickness at the gate edge, thereby forming an LDD structure. Therefore, hot carrier effect can be prevented and channel stop ion implantation is formed at the bottom of the field oxide layer to form a high-concentration bonding layer of -impurity opposite to the channel region, resulting in punch-through due to high integration of the device. There is an effect that can prevent the phenomenon.

Claims (10)

제1도전형 반도체 기판(1)상에 필드산화막(2)을 형성하고, 상기 필드산화막(2)을 선택적으로 제거하여, 계단 형상의 활성영역을 형성하는 공정과, 전표면에 제1절연막(5)을 형성하고, 활성 영역중 게이트 영역으로 선택된 단차를 갖는 부분의 상측 제1절연막(5)을 제거하는 공정과, 상기 전표면에 절연막을 형성하고, 에치백하여 제1측벽절연막(6)을 형성하는 공정과, 노출된 전표면상에 제2절연막(7)과 제1도전체(8)를 차례로 형성하고 이들중 게이트 전극과 게이트 절연막으로 사용하기 위한 게이트 영역내의 부분을 제외한 나머지 부분을 제거하는 공정과, 잔존하는 제1도전체(8)를 마스크로 하여, 제2도전형 불순물을 제1도전형 반도체 기판(1)에 주입하여 저농도의 소오스/드레인 영역(11)을 형성하는 공정과, 잔존하는 제1도전체(8)와 제2절연막(7)의 측벽에 제2측벽절연막(10)을 형성하는 공정과, 제2측벽절연막(10)과 잔존하는 제1도전체(8)를 마스크로 하여 제2도전형 불순물을 제1도전형 반도체 기판(1)에 주입하여 고농도의 소오스/드레인 영역(12)을 형성하고, LDD(11a)를 형성하는 공정을 구비함을 특징으로 하는 MOS 트랜지스터 제조방법.Forming a field oxide film 2 on the first conductive semiconductor substrate 1, selectively removing the field oxide film 2 to form a stepped active region, and forming a first insulating film on the entire surface thereof. 5) and removing the upper first insulating film 5 of the portion having the step selected in the gate region of the active region; forming an insulating film on the entire surface and etching back to form the first side wall insulating film 6; Forming the second insulating film 7 and the first conductor 8 on the exposed entire surface, and removing the remaining portions except for the portion in the gate region for use as the gate electrode and the gate insulating film. Forming a low concentration source / drain region 11 by injecting the second conductive impurity into the first conductive semiconductor substrate 1 using the remaining first conductive material 8 as a mask; On the sidewalls of the remaining first conductor 8 and the second insulating film 7, The second conductive impurity is implanted into the first conductive semiconductor substrate 1 using the process of forming the second side insulating film 10 and the first conductive material 8 remaining with the second side insulating film 10 as a mask. Forming a high concentration source / drain region (12) and forming an LDD (11a). 제1항에 있어서, 필드산화막(2)은 4000~7500Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the field oxide film (2) is formed to a thickness of 4000 to 7500 kPa. 제1항에 있어서, 제1측벽산화막(6)은 2000~4000Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the first sidewall oxide film (6) is formed to a thickness of 2000 to 4000 GPa. 제1항에 있어서, 제2절연막(7)은 800~1000℃의 온도범위에서 100~500Å의 두께로 열산화하여 형성하는 것을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the second insulating film (7) is formed by thermal oxidation to a thickness of 100 to 500 kPa in a temperature range of 800 to 1000 ° C. 제1항에 있어서, 제1도전체(8)는 2000~5000Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.2. The method of claim 1 wherein the first conductor (8) is formed to a thickness of 2000 to 5000 microns. 제1항에 있어서, LDD(11a)을 형성하기 위한 저농도의 소오스/드레인 영역의 제2도전형 불순물 주입농도는 0.5×3×1013atom/㎠으로 함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the second conductivity type impurity implantation concentration of the low concentration source / drain region for forming the LDD (11a) is 0.5x3x10 13 atom / cm2. 제1항에 있어서, 고농도 소오스/드레인 영역(12)의 농도는 2~6×1015atom/㎠으로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of claim 1, wherein the concentration of the high concentration source / drain region (12) is 2 to 6 x 10 15 atoms / cm 2. 제1항에 있어서, 게이트(8a)의 측벽절연막(6, 10)을 이중으로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.A method according to claim 1, wherein the sidewall insulating films (6, 10) of the gate (8a) are formed in duplicate. 제1항에 있어서, 활성 영역을 필드산화막(2)의 일부분에 까지 확장하여 단차를 갖는 부분을 포함하여 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the active region is extended to a part of the field oxide film (2) to include a step having a step. 제1항에 있어서, LDD(11a)형성을 위해 소오스/드레인 영역(11)에 불순물 이온 주입시 주입 각도를 경사지게 하여 주입함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the implant angle is inclined when implanting impurity ions into the source / drain region (11) to form the LDD (11a).
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KR100787015B1 (en) 2005-04-20 2007-12-18 엔이씨 일렉트로닉스 가부시키가이샤 Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics

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KR100248200B1 (en) * 1996-12-30 2000-03-15 김영환 Soi semiconductor device

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JPS6366967A (en) * 1986-09-08 1988-03-25 Hitachi Ltd Semiconductor device and manufacture thereof
KR920013700A (en) * 1990-12-18 1992-07-29 문정환 Soy structure transistor manufacturing method

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Publication number Priority date Publication date Assignee Title
JPS6366967A (en) * 1986-09-08 1988-03-25 Hitachi Ltd Semiconductor device and manufacture thereof
KR920013700A (en) * 1990-12-18 1992-07-29 문정환 Soy structure transistor manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787015B1 (en) 2005-04-20 2007-12-18 엔이씨 일렉트로닉스 가부시키가이샤 Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics

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