KR940002778B1 - Manufacturing method for ldd-strucutred tr - Google Patents

Manufacturing method for ldd-strucutred tr Download PDF

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KR940002778B1
KR940002778B1 KR1019910000561A KR910000561A KR940002778B1 KR 940002778 B1 KR940002778 B1 KR 940002778B1 KR 1019910000561 A KR1019910000561 A KR 1019910000561A KR 910000561 A KR910000561 A KR 910000561A KR 940002778 B1 KR940002778 B1 KR 940002778B1
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oxide film
nitride film
oxide layer
forming
film
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KR1019910000561A
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Korean (ko)
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KR920015592A (en
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김영기
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

The LDD-structured transistor manufacturing method includes the steps of: sequentially forming a buffer oxide layer and first nitride layer, and removing the first nitride layer on a field area to form a field oxide layer by a thermal oxidation; removing the buffer oxide layer and first nitride layer, sequentially forming a base oxide layer and second nitride layer on an active area, patterning the second nitride layer, and implanting n-type ions on the substrate; thermally oxidating the base oxide layer to form a selective oxide layer; removing the second nitride layer, depositing and selectively removing polysilicon to form a gate electrode; and forming a sidewall oxide layer on the sidewalls of the gate electrode, and implanting n-type ions in a high concentration, thereby reducing hot carriers.

Description

LDD 구조의 트랜지스터 제조방법LDD structure transistor manufacturing method

제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.

제2도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 버퍼산화막1 substrate 2 buffer oxide film

3 : 제1질화막 4 : 필드산화막3: first nitride film 4: field oxide film

5 : 베이스산화막 6 : 제2질화막5: base oxide film 6: second nitride film

7 : 선택적산화막 8 : 다결정실리콘7: selective oxide film 8: polycrystalline silicon

9 : 산화막9: oxide film

본 발명은 LDD(Lightly Doped Drain) 구조의 트랜지스터 제조방법에 관한 것으로, 특히 핫 캐리어(Hot Carrier)의 발생을 방지하여 소자의 특성을 향상시킬 수 있도록 한 것이다.The present invention relates to a method of manufacturing a transistor having a lightly doped drain (LDD) structure, in particular to prevent the occurrence of hot carriers (hot carriers) to improve the characteristics of the device.

종래의 LDD 구조의 트랜지스터 제조방법을 제1a도와 같이 기판(11)위에 버퍼산화막(12), 질화막(13)을 차례로 형성한 후 액티브영역과 필드영역을 정의하여 필드영역의 질화막(14)을 선택적으로 제거한 다음 노출된 필드영역을 선택적 산화를 이용하여 필드산화막(14)을 형성한다.In the conventional LDD structure transistor manufacturing method, as shown in FIG. 1A, the buffer oxide film 12 and the nitride film 13 are sequentially formed on the substrate 11, and then, the active region and the field region are defined to selectively select the nitride layer 14 of the field region. After the removal, the exposed field region is formed using the selective oxidation to form the field oxide film 14.

다음에 질화막(13)과 버퍼산화막(12)을 제거하고 제1b도와 같이 액티브영역에 베이스 산화막(15)을 형성하여 문턱전압 조절을 위한 이온주입후 전면에 다결정 실리콘을 형성하고 게이트 마스크를 이용한 패터닝(Patterning)하여 게이트 전극(16)을 형성한다.Next, the nitride film 13 and the buffer oxide film 12 are removed, and the base oxide film 15 is formed in the active region as shown in FIG. 1b. After ion implantation for controlling the threshold voltage, polycrystalline silicon is formed on the entire surface and patterned using a gate mask. Patterning is performed to form the gate electrode 16.

그리고 자기정합(Self-Align) 방법으로 LDD 구조를 위한 N-이온을 주입한다.In addition, N-ions for LDD structures are injected by a self-aligning method.

또한, 제1c도와 같이 산화막(17)을 형성하고 마스킹없이 산화막(17)을 식각하여 게이트 측벽에 산화막(17)이 남게 한다.In addition, as shown in FIG. 1C, the oxide film 17 is formed and the oxide film 17 is etched without masking so that the oxide film 17 remains on the gate sidewall.

그리고 N+이온주입후 열처리하고 절연막(예를들어 BPSG나 PSG)을 증착후 콘택을 형성하며 이어서 금속막을 증착하고 패터닝한다.After the N + ion implantation, heat treatment is performed, and an insulating film (for example, BPSG or PSG) is deposited, and then a contact is formed. Then, a metal film is deposited and patterned.

이와 같이 제조되는 종래 LDD 구조의 트랜지스터는 소오스나 드레인 에지(Edge) 부분의 산화막이 채널부분의 산화막과 두께가 동일하기 때문에 트랜지스터 동작시 드레인 에지와 게이트가 오버랩(Over lap)되는 부분에 전계(Electric Field)가 집중적으로 형성되어 핫 캐리어가 발생하기 쉬우며 이 핫 캐리어는 트랜지스터가 반복동작시 그 양이 많아져 결국 문턱전압을 변화시키므로 소자의 신뢰성을 저하시키게 된다.In the conventional LDD transistor fabricated as described above, since the oxide film of the source or drain edge portion has the same thickness as the oxide film of the channel portion, the transistor has an electric field at a portion where the drain edge and the gate overlap. It is easy to generate hot carriers because the field is concentrated, and this hot carrier decreases the reliability of the device because the amount of the transistor increases when the transistor is repeatedly operated.

또한, 종래에는 게이트 측벽에 산화막을 형성하기가 어려우며 이러한 측벽 스페이서에 따라 N+소오스 및 드레인 영역이 달라지게 될 뿐만 아니라 베이스산화막이 너무 얇아 측벽식각시 기판(11)이 손상되기 쉬운 결점이 있다.In addition, in the related art, it is difficult to form an oxide film on the gate sidewall, and the N + source and drain regions are different according to the sidewall spacers, and the base oxide film is too thin, which causes the substrate 11 to be damaged during sidewall etching.

본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로, 채널의 에지(Edge)에서의 케이트 산화막을 채널 중앙 부분보다 두껍게 형성하여 게이트 산화막에 인가되는 전계를 줄여서 핫 캐리어의 발생을 감소시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and the gate oxide film is formed thicker than the center portion of the channel to reduce the electric field applied to the gate oxide to reduce the occurrence of hot carriers. have.

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상술하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings of FIG. 2.

먼저 제2a도와 같이 기판(1)위에 버퍼산화막(2)과 제1질화막(3)을 형성한 뒤 액티브영역과 필드영역을 정의하고, 필드영역의 제1질화막(3)을 선택적으로 제거한 다음 선택적 열산화를 이용하여 필드영역에 필드산화막(4)을 형성한다.First, as shown in FIG. 2A, the buffer oxide film 2 and the first nitride film 3 are formed on the substrate 1, the active region and the field region are defined, and the first nitride film 3 of the field region is selectively removed. The field oxide film 4 is formed in the field region by thermal oxidation.

다음에 제2b도와 같이 제1질화막(3) 및 산화막(2)을 제거하고 베이스 산화막(5) 및 제2질화막(6)을 차례로 증착한 후 게이트 마스크를 이용하여 제2질화막(6)을 패터닝한다.Next, as shown in FIG. 2B, the first nitride film 3 and the oxide film 2 are removed, the base oxide film 5 and the second nitride film 6 are sequentially deposited, and the second nitride film 6 is patterned using a gate mask. do.

이어서, 제2질화막(6)을 제거된 기판(1)에 LDD 구조를 위한 N-이온을 주입하고 제2c도와 같이 제2질화막(6)을 마스크로 이용하여 상기 베이스산화막(5)을 열적산화(Thermal Oxidation)시켜 선택적 산화막(7)을 500-1500Å 형성한다.Subsequently, N − ions for the LDD structure are implanted into the substrate 1 from which the second nitride film 6 has been removed, and the base oxide film 5 is thermally oxidized using the second nitride film 6 as a mask as shown in FIG. 2C. (Thermal Oxidation) to form a 500-1500 500 selective oxide film (7).

이때, 제2질화막(6)이 있는 부분은 없는 부분보다 산화막(7)이 얇게 형성된다.At this time, the oxide film 7 is formed thinner than the portion without the second nitride film 6.

또한, 제2d도와 같이 제2질화막(6)을 제거하고 다결정 실리콘(8)을 증착한다.In addition, as shown in FIG. 2D, the second nitride film 6 is removed and the polycrystalline silicon 8 is deposited.

그리고 게이트 마스크를 이용하여 다결정실리콘(8)을 식각하여 게이트 전극을 형성하고 제2e도와 같이 전면에 산화막(9)을 증착하고 에치백하여 게이트 전극 측벽에 측벽산화막(9)을 형성한다.The polysilicon 8 is etched using a gate mask to form a gate electrode, and as shown in FIG. 2e, an oxide film 9 is deposited on the entire surface and etched back to form a sidewall oxide film 9 on the sidewall of the gate electrode.

이후 게이트에 의한 자기정합 방법으로 N+이온주입 및 열처리를 하여 LDD 구조의 소오스 및 드레인 영역을 형성하고 이어서 통상의 공정을 실시한다.Subsequently, the source and drain regions of the LDD structure are formed by performing N + ion implantation and heat treatment by a self-aligning method using a gate, followed by a conventional process.

이와 같은 본 발명은 핫 캐리어가 발생하는 부분인 게이트와 드레인 오버랩(Overlap) 되는 부분의 게이트 산화막(8)을 채널 부분보다 두껍게 형성함으로 이 부분의 게이트 산화막에 인가되는 전계를 둘여서 핫 캐리어의 발생을 감소시킬 수 있다.The present invention forms the gate oxide film 8 of the gate overlapping portion and the gate overlapping portion thicker than the channel portion by creating a thicker electric field applied to the gate oxide film of the hot carrier. Can be reduced.

또한, 질화막(3)을 이용하여 필드산화막(4)을 새부리 모양의 원하는 형태와 두께로 형성할 수 있어 채널의 에지에서의 게이트 산화막(8)을 채널 중앙부분 보다 두껍게 하는데 이상적이다.Further, the nitride film 3 can be used to form the field oxide film 4 in a desired shape and thickness in the shape of a beak, which is ideal for making the gate oxide film 8 at the edge of the channel thicker than the center portion of the channel.

특히, N+소오스 및 드레인 이온주입이 게이트에 자기정합되어 레터럴 디퓨젼(Lateral Diffusion)이 일정하게 유지될 수 있는 효과가 있다.In particular, N + source and drain ion implantation is self-aligned to the gate has the effect that the lateral diffusion (Lateral Diffusion) can be kept constant.

Claims (1)

기판위에 버퍼산화막과 제1질화막을 차례로 형성하고 필드영역의 제1질화막을 제거하여 열산화 공정으로 필드산화막을 형성하는 공정과, 상기 버퍼산화막과 제1질화막을 제거하고 액티브영역에 베이스 산화막 및 제2질화막을 차례로 형성하고 게이트 영역에만 남도록 제2질화막을 패터닝하고 제2질화막이 제거된 기판에 저농도 n형 이온을 주입하는 공정과, 상기 제2질화막을 마스크로 이용 베이스 산화막을 열산화하여 선택적 산화막을 500-1500Å 형성하는 공정과, 상기 제2질화막을 제거하고 다결정 실리콘을 증착하고 선택적으로 제거하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극 측벽에 측벽산화막을 형성하고 고농도 n형 이온을 주입하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 LDD 구조의 트랜지스터 제조방법.Forming a field oxide film by a thermal oxidation process by sequentially forming a buffer oxide film and a first nitride film on the substrate, and removing the first nitride film of the field region, and removing the buffer oxide film and the first nitride film, and removing the base oxide film and the first oxide film in the active region. Forming a second nitride film sequentially and patterning the second nitride film so as to remain only in the gate region, and implanting low concentration n-type ions into the substrate from which the second nitride film has been removed; Forming a gate electrode by removing the second nitride film and depositing and selectively removing polycrystalline silicon; forming a sidewall oxide film on the sidewall of the gate electrode and implanting high concentration n-type ions; A transistor manufacturing method of an LDD structure, characterized in that the step is performed in sequence.
KR1019910000561A 1991-01-15 1991-01-15 Manufacturing method for ldd-strucutred tr KR940002778B1 (en)

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