KR0156158B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR0156158B1 KR0156158B1 KR1019950043302A KR19950043302A KR0156158B1 KR 0156158 B1 KR0156158 B1 KR 0156158B1 KR 1019950043302 A KR1019950043302 A KR 1019950043302A KR 19950043302 A KR19950043302 A KR 19950043302A KR 0156158 B1 KR0156158 B1 KR 0156158B1
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- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract 2
- 230000010354 integration Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
Abstract
본 발명은 반도체 소자에 관한 것으로, 특히 MOS 트랜지스터의 소오스/드레인 영역을 필드산화막의 일부를 제거하여 소자격리영역상에 형성하여 고집적화에 적당하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a source / drain region of a MOS transistor is formed on a device isolation region by removing a part of a field oxide film so as to be suitable for high integration.
상기와 같은 본발명의 반도체 소자의 제조방법은 제1도전형의 반도체 기판상에 액티브 마스크를 사용하여 활성영역을 패터닝하고 소자격리영역에 필드산화막을 형성하는 공정과, 상기 활성영역에 문턱전압을 조절하기 위한 불순물 이온주입공정을 실시하고 전면에 폴리실리콘층과 캡산화막을 차례로 형성하는 공정과, 상기 폴리실리콘층과 캡산화막을 채널영역과 필드산화막의 일부영역에만 남도록 제거하여 게이트전극을 형성하는 공정과, 상기 게이트전극을 마스크로 저농도의 제2도전형 불순물을 이온주입하고 필드산화막의 일부를 제거하는 공정과, 상기 게이트전극과 남아 있는 필드산화막의 측면에 측벽을 형성하고 전면에 제2도전형의 불순물이 도핑된 폴리실리콘층을 증착하는 공정과, 상기 불순물이 도핑된 폴리실리콘층을 에치백하여 필드산화막이 제거된 영역에만 남도록하여 소오스/드레인영역을 형성하는 공정으로 이루어진다.The method of manufacturing a semiconductor device of the present invention as described above comprises the steps of patterning an active region using an active mask on a semiconductor substrate of a first conductivity type, forming a field oxide film in the device isolation region, and applying a threshold voltage to the active region. Performing an impurity ion implantation step to control and sequentially forming a polysilicon layer and a cap oxide film on the entire surface, and removing the polysilicon layer and the cap oxide film so as to remain only in a partial region of the channel region and the field oxide film to form a gate electrode And ion implanting a low concentration of the second conductive impurity into the mask using the gate electrode as a mask, and removing a part of the field oxide film; forming a sidewall on the side of the gate electrode and the remaining field oxide film, and forming a second conductive film on the entire surface. A process of depositing a polysilicon layer doped with an impurity of a type, and etching back the polysilicon layer doped with the impurity A process of forming a source / drain region by leaving only the region where the deoxidation film is removed is performed.
Description
제1도 (a) 내지 (g)는 종래의 반도체 소자의 공정단면도.1 (a) to (g) are process cross-sectional views of a conventional semiconductor device.
제2도 (a) 내지 (i)는 본 발명의 반도체 소자의 공정단면도.2 (a) to (i) are process cross-sectional views of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 반도체기판 21 : 버퍼산화막20: semiconductor substrate 21: buffer oxide film
22 : 액티브 마스크 23 : 필드산화막22: active mask 23: field oxide film
24, 24a, 24b : 게이트전극 25 : 측벽24, 24a, 24b: gate electrode 25: side wall
26 : 불순물이 도핑된 폴리실리콘 27a, 27b : 소오스/드레인영역26: polysilicon doped with impurities 27a, 27b: source / drain regions
본 발명은 반도체 소자에 관한 것으로, 특히 MOS 트랜지스터의 소오스/드레인영역을 필드산화막의 일부를 제거하여 소자격리영역상에 형성하여 고집적화에 적당하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a source / drain region of a MOS transistor is formed on a device isolation region by removing a part of a field oxide film, so as to be suitable for high integration.
일반적으로 MOS 소자에 있어서, 고집적화에 따른 게이트폭의 축소로 인하여 드레인으로 전계집중이 일어나는 것을 막기위하여 게이트 측벽의 하측에 저농도의 접합을 형성하는 LDD(Lightly Doped Drain)구조를 채택하고 있다.In general, in the MOS device, a lightly doped drain (LDD) structure is formed in which a low concentration junction is formed under the gate sidewall to prevent electric concentration from occurring due to a reduction in gate width due to high integration.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
제1도(a) 내지 (g)는 종래의 반도체 소자의 공정단면도이다.1 (a) to (g) are process cross-sectional views of a conventional semiconductor device.
LDD구조의 MOS소자는 먼저, 제1도(a)에서와 같이, 버퍼산화막(2)이 형성된 반도체기판(1)에 액티브 마스크(3)(통상적으로 질화막)를 이용하여 활성영역을 패터닝하고 제1도(b)에서와 같이 소자격리영역에 필드산화막(4)을 형성한다.In the MOS device of the LDD structure, first, as shown in FIG. 1 (a), the active region 3 is patterned on the semiconductor substrate 1 on which the buffer oxide film 2 is formed by using an active mask 3 (usually a nitride film). A field oxide film 4 is formed in the device isolation region as shown in FIG. 1 (b).
이어, 제1도(c)에서와 같이, 상기 LOCOS 공정에서 마스크로 사용되어진 액티브 마스크(3)를 제거하고 활성영역에 소자의 문턱전압(Vth)를 조절하기 위한 불순물 이온주입공정을 실시한다.Next, as shown in FIG. 1C, an impurity ion implantation process for removing the active mask 3 used as a mask in the LOCOS process and adjusting the threshold voltage V th of the device in the active region is performed. .
그리고, 제1도(d)에서와 같이 채널영역상에 폴리실리콘층(5a) 및 캡산화막(5b)으로 이루어진 게이트전극(5)을 형성한다.As shown in FIG. 1D, the gate electrode 5 including the polysilicon layer 5a and the cap oxide film 5b is formed on the channel region.
이어, 제1도(e)에서와 같이, 상기 게이트전극(5)을 마스크로 하여 활성영역에 LDD구조를 형성하기 위한 저농도의 불순물을 이온 주입한다.Subsequently, as shown in FIG. 1E, a low concentration of impurities for forming an LDD structure in the active region is implanted using the gate electrode 5 as a mask.
그리고 제1도(f)에서와 같이, 상기 게이트전극(5)의 측면에 측벽(side wall) (6)을 형성하고 소오스/드레인영역을 형성하기 위한 불순물 이온주입공정을 실시하여 제1도(g)에서와 같이 반도체기판(1)의 채널영역을 제외한 활성영역에 소오스/드레인 영역(7a)(7b)을 형성한다.As shown in FIG. 1 (f), an impurity ion implantation process for forming sidewalls 6 and forming source / drain regions on the side of the gate electrode 5 is performed. As in g), the source / drain regions 7a and 7b are formed in the active region except for the channel region of the semiconductor substrate 1.
상기와 같은 LDD구조의 MOS소자는 드레인영역과 채널사이에 저농도의 완만한 프로파일을 가진 불순물층을 형성하여, 드레인영역 부근의 핀치오프영역에서 발생하는 고전계에 의한 핫 캐리어효과를 감소시킨다.The MOS device of the LDD structure as described above forms an impurity layer having a low concentration and gentle profile between the drain region and the channel, thereby reducing the hot carrier effect due to the high field generated in the pinch-off region near the drain region.
그러나 상기와 같은 종래의 LDD 구조의 MOS 소자에 있어서는 LDD구조의 MOS 소자를 레이 아웃상에서 활성영역내에만 형성하기 때문에 고집적화에는 한계가 있는 문제점이 있었다.However, in the conventional MOS device of the LDD structure as described above, since the MOS device of the LDD structure is formed only in the active region on the layout, there is a problem that there is a limit in the high integration.
본 발명은 상기와 같은 종래의 반도체 소자의 문제점을 해결하기 위하여 안출한 것으로 LDD 구조의 MOS 소자 형성시에 소오스/드레인영역을 필드산화막의 일부를 제거하여 소자격리영역상에 형성하여 고집적화에 적당하도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional semiconductor device as described above. When forming a MOS device having an LDD structure, a source / drain region is formed on the device isolation region by removing a part of the field oxide film so as to be suitable for high integration. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 제1도전형의 반도체기판상에 액티브 마스크를 사용하여 활성영역을 패너팅하고 소자격리영역에 필드산화막을 형성하는 공정과, 상기 활성영역에 문턱전압을 조절하기 위한 불순물 이온주입공정을 실시하고 전면에 폴리실리콘층과 캡산화막을 차례로 형성하는 공정과, 상기 폴리실리콘층과 캡산화막을 채널영역과 필드산화막상의 일부 영역에만 남도록 제거하여 게이트전극을 형성하는 공정과, 상기 게이트전극을 마스크로 저농도의 제2도전형 불순물을 이온 주입하고 필드산화막의 일부를 제거하는 공정과, 상기 게이트전극과 남아있는 필드산화막의 측면에 측벽을 형성하고 전면에 제2도전형의 불순물이 도핑된 폴리실리콘을 증착하는 공정과, 상기 불순물이 도핑된 폴리실리콘 층을 에치백하여 필드산화막이 제거된 영역에만 남도록하여 소오스/드레인영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming an active region on the first conductive semiconductor substrate using an active mask and forming a field oxide film in the device isolation region, and the active Performing impurity ion implantation to control the threshold voltage in the region, and forming a polysilicon layer and a cap oxide layer on the front side in turn, and removing the polysilicon layer and the cap oxide layer so that only a portion of the channel region and the field oxide layer remain Forming a gate electrode, ion implanting a low concentration of a second conductive impurity with the gate electrode as a mask, removing a portion of the field oxide film, and forming sidewalls on the side of the gate electrode and the remaining field oxide film; Depositing polysilicon doped with a second conductivity type impurity on the entire surface, and polysilicon doped with the impurity And etching back to leave only the area of the field oxide film is removed by yirueojim characterized by including the step of forming the source / drain regions.
이하, 첨부된 도면을 참고하여 본발명의 반도체소자의 제조방법에 대하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
제2도 (a) 내지 (i)는 본 발명의 반도체 소자의 공정단면도이다.2 (a) to (i) are process cross-sectional views of the semiconductor device of the present invention.
먼저, 제2도(a)에서와 같이 버퍼산화막(21)이 형성된 반도체기판(20)에서 액티브 마스크(22)를 이용하여 활성영역을 패터닝하고, 제2도(b)에서와 같이, 소자격리영역에 LOCOS 공정으로 필드산화막(23)을 형성한다.First, as shown in FIG. 2 (a), the active region is patterned using the active mask 22 on the semiconductor substrate 20 on which the buffer oxide film 21 is formed. As shown in FIG. The field oxide film 23 is formed in the region by the LOCOS process.
이어, 제2도(c)에서와 같이, 상기 LOCOS 공정에서 마스크로 사용되어진 액티브 마스크(22)를 제거하고 활성영역에 소자의 문턱전압(Vth)를 조절하기 위한 불순물 이온주입공정을 실시한다.Next, as shown in FIG. 2C, an impurity ion implantation process for removing the active mask 22 used as a mask in the LOCOS process and adjusting the threshold voltage Vth of the device in the active region is performed.
그리고 제2도(d)에서와 같이, 전면에 폴리실리콘층(24a) 및 캡산화막(24b)을 차례로 형성한 후 채널영역과 필드산화막(23)상의 일부영역에만 남도록 제거하여 게이트전극(24)을 형성한다.As shown in FIG. 2D, the polysilicon layer 24a and the cap oxide film 24b are sequentially formed on the entire surface thereof, and then removed to remain only in a partial region on the channel region and the field oxide film 23. To form.
이어, 제2도(e)에서와 같이, 상기 게이트전극(24)을 마스크로 하여 LDD 구조를 만들기 위한 저농도의 불순물 이온주입공정을 실시한다.Subsequently, as shown in FIG. 2E, a low concentration impurity ion implantation process is performed to form an LDD structure using the gate electrode 24 as a mask.
그리고 제2도(f)에서와 같이, 상기 필드산화막(23)상의 일부 영역에 남아있는 폴리실리콘층(24a) 및 캡산화막(24b)을 마스크로 필드산화막(23)의 일부분을 제거한다.As shown in FIG. 2 (f), a part of the field oxide film 23 is removed using the polysilicon layer 24a and the cap oxide film 24b remaining in the partial region on the field oxide film 23 as a mask.
그리고 마스크로 사용된 필드산화막(23)상의 폴리실리콘층(24a) 및 캡산화막(24b)을 제거한다.Then, the polysilicon layer 24a and the cap oxide film 24b on the field oxide film 23 used as a mask are removed.
이어, 제2도(g)에서와 같이, 남아있는 필드산화막(23)과 게이트전극(24)의 측면에 측벽(side wall)을 형성한다.Subsequently, sidewalls are formed on the side surfaces of the remaining field oxide film 23 and the gate electrode 24, as shown in FIG.
그리고, 제2도(h)에서와 같이, 전면에 불순물이 도핑된 폴리실리콘(26)을 증착하고 제2도(i)에서와 같이, 불순물이 도핑된 폴리실리콘(26)층을 에치백(Etch back)하여 필드산화막(23)이 제거된 부분에만 남도록 하여 소오스/드레인영역(27a)(27b)을 형성한다(이때, 어닐링 공정을 포함하므로 제2도 (i)의영역에서와 같이 기판으로 불순물의 확산이 일어나게 된다).Then, as shown in FIG. 2 (h), the polysilicon 26 doped with impurities is deposited on the entire surface, and as shown in FIG. 2 (i), the impurity doped polysilicon 26 layer is etched back ( The source / drain regions 27a and 27b are formed by etching back so that the field oxide film 23 remains only in the removed portion (in this case, since the annealing process is included, As in the region, diffusion of impurities into the substrate occurs).
상기와 같은 본 발명의 반도체 소자의 제조방법에 있어서는 MOS 소자의 소오스/드레인영역을 필드산화막의 일부를 제거하여 소자격리영역에 형성하므로 소자의 집적도를 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention as described above, the source / drain regions of the MOS devices are formed in the device isolation region by removing a part of the field oxide film, thereby improving the integration degree of the device.
또한, 소오스/드레인영역을 형성하기 위한 공정을 이온주입공정이 아닌 불순물이 도핑된 폴리실리콘의 증착(Peposition)공정으로 하여 이온 주입공정에서 발생하는 손상(Damage)으로 인한 역방향 쇼트 채널 효과(Reverce Short Channel Effect)를 줄일 수 있다.In addition, the process of forming the source / drain regions is a process of depositing polysilicon doped with impurities, not an ion implantation process, so that a reverse short channel effect due to damage generated in the ion implantation process is achieved. Channel Effect) can be reduced.
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| KR1019950043302A KR0156158B1 (en) | 1995-11-23 | 1995-11-23 | Method of fabricating semiconductor device |
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