KR100198676B1 - Transistor of semiconductor device and method of manufacturing the same - Google Patents
Transistor of semiconductor device and method of manufacturing the same Download PDFInfo
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- KR100198676B1 KR100198676B1 KR1019960052738A KR19960052738A KR100198676B1 KR 100198676 B1 KR100198676 B1 KR 100198676B1 KR 1019960052738 A KR1019960052738 A KR 1019960052738A KR 19960052738 A KR19960052738 A KR 19960052738A KR 100198676 B1 KR100198676 B1 KR 100198676B1
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- transistor
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 125000006850 spacer group Chemical group 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
본 발명은 반도체 소자의 트랜지스터(Transtor)에 관한 것으로 특히, 숏 채널 효과(Short Channal Effect)인 펀치쓰로우(Punchthrough) 현상을 방지하도록 한 반도체 소자의 트랜지스터의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device, and more particularly, to a structure and a manufacturing method of a transistor of a semiconductor device designed to prevent a punch through phenomenon, which is a short channel effect.
이와같은 본 발명의 반도체 소자의 트랜지스터의 구조는 표면으로부터 소정 깊이로 트랜치가 형성된 기판; 상기 트랜치가 형성된 부분의 기판상에 일정한 폭으로 형성되는 절연막; 상기 절연막을 포함하고 전면에 형성되는 도전층; 상기 도전층상에 형성되는 게이트 절연막 및 게이트 전극, 상기 게이트 전극 양측의 기판내에 형성되는 소오스/드레인 불순물 영역을 포함하여 구성됨에 그 특징이 있다.Such a structure of the transistor of the semiconductor device of the present invention comprises a substrate having a trench formed in a predetermined depth from the surface; An insulating film formed on the substrate at the portion where the trench is formed to have a predetermined width; A conductive layer including the insulating film and formed on an entire surface thereof; A gate insulating film and a gate electrode formed on the conductive layer, and source / drain impurity regions formed in the substrate on both sides of the gate electrode are characterized in that it comprises.
Description
본 발명은 반도체 소자의 트랜지스터(Transtor)에 관한 것으로 특히, 숏 채널 효과(Short Channal Effect)인 펀치쓰로우(Punchthrough) 현상을 방지하도록 한 반도체 소자의 트랜지스터의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device, and more particularly, to a structure and a manufacturing method of a transistor of a semiconductor device designed to prevent a punch through phenomenon, which is a short channel effect.
일반적으로 반도체 소자의 집적화에 따라 점차 미세화하여 서브 마이크론급의 반도체 소자들이 개발되어 지고 있다. 이와같은 추세에 따라 트랜지스터에서도 소오스 영역과 드레인 영역 사이의 채널 길이가 짧아지므로 해서 숏채널 효과(Short Channel Effect)인 핫 캐리어(Hot Carrier), 펀치쓰로우(PunchThrough)현상등이 발생되었다.In general, with the integration of semiconductor devices, submicron class semiconductor devices have been developed. As a result, the channel length between the source region and the drain region is shortened in the transistor, resulting in a hot channel, a short carrier effect, a hot carrier, and a punch through phenomenon.
참고문헌[Chenming Huet al, Hot Electron-Induced MOSFET Degradatidn Mo del, Monitor and Improvement, IEEE Transatctions on Electron Devies, Vol, ED 32. NO.2. 1985.pp. 375 - 385]에 의하면 핫 캐리어로 인한 불안정성은 짧은 채널 길이와 높은 인가전압에서 기인한 드레인 접합 근처에서의 매우 높은 전계가 그 원인이다.References: Chenming Hu et al, Hot Electron-Induced MOSFET Degradatidn Module, Monitor and Improvement, IEEE Transatctions on Electron Devies, Vol, ED 32. NO.2. 1985.pp. 375-385] The instability due to hot carriers is due to very high electric fields near the drain junction due to short channel lengths and high applied voltages.
따라서, 숏채널 효과인 핫 캐리어에 취약한 기존의 트랜지스터 소자 구조를 개선한 LDD구조가 제안되었다.Accordingly, an LDD structure has been proposed that improves the structure of a conventional transistor device that is vulnerable to hot carriers, which is a short channel effect.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 트랜지스터의 구조 및 제조방법을 설명하면 다음과 같다.Hereinafter, a structure and a manufacturing method of a transistor of a conventional semiconductor device will be described with reference to the accompanying drawings.
제1도는 종래의 반도체 소자의 트랜지스터의 구조를 나타낸 구조단면도이고, 제2a도 - 제2d도는 종래의 반도체 소자의 트랜지스터의 제조방법을 나타낸 공정단면도이다.1 is a structural sectional view showing the structure of a transistor of a conventional semiconductor device, and FIGS. 2A to 2D are process sectional views showing a method of manufacturing a transistor of a conventional semiconductor device.
종래의 반도체 소자의 트랜지스터의 구조는 제1도에 도시된 바와같이 실리콘 기판(11)상에 게이트 절연막(12)이 형성되고, 상기 게이트 절연막(12)상에 게이트 전극(15)이 형성된다.In the structure of a transistor of a conventional semiconductor device, as shown in FIG. 1, a gate insulating film 12 is formed on a silicon substrate 11, and a gate electrode 15 is formed on the gate insulating film 12.
그리고 상기 게이트 전극(15)의 양측면에 측벽 스페이서(17)가 형성되고, 상기 게이트 전극(15) 및 측벽 스페이서(17) 양측의 반도체 기판(11)에 LDD 구조를 갖는 소오스/드레인 불순물 확산영역(18)이 형성된다.The sidewall spacers 17 may be formed on both side surfaces of the gate electrode 15, and source / drain impurity diffusion regions having LDD structures may be formed in the semiconductor substrate 11 on both sides of the gate electrode 15 and the sidewall spacers 17. 18) is formed.
상기와 같은 구조를 갖는 종래의 반도체 소자의 트랜지스터의 제조방법은 제2a도에 도시된 바와같이 반도체 기판(11)위에 게이트 절연막(12) 및 게이트 전극용 다결정 실리콘층(13)을 차례로 형성한다. 이어, 상기 게이트 전극용 다결정 실리콘층(13)상에 감광막(14)을 도포한 후, 상기 감광막(14)을 노광 및 현상공정으로 패터닝(Patterning) 한다.In the conventional method of manufacturing a transistor of a semiconductor device having the above structure, as shown in FIG. 2A, the gate insulating film 12 and the polycrystalline silicon layer 13 for the gate electrode are sequentially formed on the semiconductor substrate 11. Subsequently, after the photosensitive film 14 is coated on the polycrystalline silicon layer 13 for the gate electrode, the photosensitive film 14 is patterned by exposure and development processes.
제2b도에 도시된 바와같이 상기 패터닝된 감광막(14)을 마스크로 사용하여 상기 게이트 전극용 다결정 실리콘층(1)) 및 게이트 절연막(12)을 선택적으로 제거하여 게이트 전극(15)을 형성한다.As shown in FIG. 2B, the patterned photosensitive film 14 is used as a mask to selectively remove the gate polycrystalline silicon layer 1 and the gate insulating film 12 to form a gate electrode 15. As shown in FIG. .
그리고 상기 감광막(14)을 제거하고, 상기 게이트 전극(15)을 마스크로 하여 저농도 불순물 이온을 주입을 하여 저농도 불순물 영역(16)을 형성한다.Then, the photoresist film 14 is removed, and low concentration impurity ions are implanted using the gate electrode 15 as a mask to form the low concentration impurity region 16.
제2c도에 도시된 바와같이 전면에 측벽 스페이서용 절연막(도면에 도시하지 않음)을 증착하여 상기 게이트 전극(15) 및 게이트 절연막(12)의 양측면에 남도록 에치백(Etch Back)공정을 실시하여 측벽 스페이서(17)를 형성한다.As shown in FIG. 2C, an insulating film for sidewall spacers (not shown) is deposited on the entire surface, and an etch back process is performed to remain on both sides of the gate electrode 15 and the gate insulating film 12. The sidewall spacers 17 are formed.
그리고 제1d도에 도시된 바와같이 상기 측벽 스페이서(17)와 게이트 전극(15)을 마스크로 하여 전면에 고농도 불순물 이온을 주입함으로써 LDD 구조를 갖는 소오스/드레인 불순물 확산영역(18)을 형성한다.As shown in FIG. 1D, a source / drain impurity diffusion region 18 having an LDD structure is formed by implanting high concentration impurity ions into the entire surface using the sidewall spacer 17 and the gate electrode 15 as a mask.
그러나 이와같은 종래의 반도체 소자의 트랜지스터의 구조 및 제조방법에 있어서 다음과 같은 문제점이 있었다.However, there are the following problems in the structure and manufacturing method of the transistor of the conventional semiconductor device.
즉, 고집적 소자로 갈수록 숏 채널(Short Channel)형성이 불가피하기 때문에 이로 인하여 펀치쓰로우(Punchthrough) 현상에 취약하다.In other words, short channel formation is inevitable toward high integration devices, and therefore, it is vulnerable to punchthrough.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 펀치쓰로우 현상 방지용 절연막을 형성하도록 한 반도체 소자의 트랜지스터의 구조 및 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a structure and a manufacturing method of a transistor of a semiconductor device, which is made to solve the above problems and to form an insulating film for preventing the punch-through phenomenon.
제1도는 종래의 반도체 소자의 트랜지스터의 구조를 나타낸 구조단면도.1 is a structural cross-sectional view showing the structure of a transistor of a conventional semiconductor device.
제2a도 - 제2d도는 종래의 반도체 소자의 트랜지스터의 제조방법을 나타낸 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a transistor of a conventional semiconductor device.
제3도는 본 발명의 반도체 소자의 트랜지스터의 구조를 나타낸 구조단면도.3 is a structural cross-sectional view showing the structure of a transistor of a semiconductor device of the present invention.
제4a도 - 제4g도는 본 발명의 반도체 소자의 트랜지스터의 제조방법을 나타낸 공정단면도.4A to 4G are process cross-sectional views showing a method of manufacturing a transistor of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 트랜치21 silicon substrate 22 trench
23 : 제1산화막 24 : 제1질화막23: first oxide film 24: first nitride film
25 : 제2감광막 26 : 제2질화막 측벽25: second photosensitive film 26: second nitride film sidewall
27 : 제2산화막 28 : 실리콘 에피택셜층27: second oxide film 28: silicon epitaxial layer
29. 게이트 절연막 30 : 폴리 실리콘층29. Gate insulating film 30: polysilicon layer
31 : 제3감광막 32 : 게이트 전극31: third photosensitive film 32: gate electrode
33 : LDD영역 34 : 측벽 스페이서33: LDD region 34: side wall spacer
35 : 소오스/드레인 불순물 영역35 source / drain impurity region
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 트랜지스터의 구조는 표면으로부터 소정깊이로 트랜치가 형성된 기판; 상기 트랜치가 형성된 부분의 기판상에 일정한 폭으로 형성되는 절연막; 상기 절연막을 포함하고 전면에 형성되는 도전층; 상기 도전층상에 형성되는 게이트 절연막 및 게이트 전극; 상기 게이트 전극 양측의 기판내에 형성되는 소오스/드레인 불순물 영역을 포함하여 구성되며, 상기와 같은 구조를 갖는 본 발명의 반도체 소자의 트랜지스터의 제조방법은 기판내에 소정 깊이로 트랜치를 형성하는 단계; 상기 트랜치 부분에 절연막을 형성하는 단계; 상기 절연막을 포함한 트랜치내부에 기판의 표면과 동일하게 도전층을 형성하는 단계; 상기 도전층상에 게이트 절연막 및 게이트 전극을 형성하는 단계; 상기 게이트 전극 양측의 기판내에 소오스/드레인 불순물 확산영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The structure of the transistor of the semiconductor device of the present invention for achieving the above object is a substrate formed with a trench to a predetermined depth from the surface; An insulating film formed on the substrate at the portion where the trench is formed to have a predetermined width; A conductive layer including the insulating film and formed on an entire surface thereof; A gate insulating film and a gate electrode formed on the conductive layer; A method of manufacturing a transistor of a semiconductor device of the present invention comprising a source / drain impurity region formed in a substrate on both sides of the gate electrode, the method comprising: forming a trench in a substrate to a predetermined depth; Forming an insulating film on the trench portion; Forming a conductive layer in the trench including the insulating layer in the same manner as the surface of the substrate; Forming a gate insulating film and a gate electrode on the conductive layer; And forming a source / drain impurity diffusion region in the substrate on both sides of the gate electrode.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 트랜지스터의 구조 및 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a structure and a manufacturing method of a transistor of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명의 반도체 소자의 트랜지스터의 구조를 나타낸 구조단면도이고, 제4a도 - 제4g도는 본 발명의 반도체 소자의 트랜지스터의 제조방법을 나타낸 공정단면도이다.3 is a structural sectional view showing the structure of the transistor of the semiconductor device of the present invention, and FIGS. 4A to 4G are process sectional views showing the method of manufacturing the transistor of the semiconductor device of the present invention.
본 발명의 반도체 소자의 트랜지스터의 구조는 제3도에 도시된 바와같이 실리콘 기판(21)의 표면으로부터 소정깊이로 트랜치(22)가 형성되고, 상기 트랜치(22)상기 소정의 폭을 갖는 제2산화막(27)이 형성된다. 이어, 상기 실리콘 기판(21)의 표면과 동일높이로 상기 제2산화막(21)을 포함하면서 실리콘 에피택셜층(28)이 형성된다.In the structure of the transistor of the semiconductor device of the present invention, as shown in FIG. 3, a trench 22 is formed to a predetermined depth from the surface of the silicon substrate 21, and the trench 22 has a second width having a predetermined width. An oxide film 27 is formed. Subsequently, the silicon epitaxial layer 28 is formed while including the second oxide film 21 at the same height as the surface of the silicon substrate 21.
그리고 상기 제2산화막(27)과 대응하게 상기 실리콘 에피택셜층(28)상에 게이트 절연막(29) 및 게이트 전극(32)이 형성되고, 상기 게이트 전극(32) 및 게이트 절연막(29)의 양측면에 측벽 스페이서(34)가 형성된다.A gate insulating layer 29 and a gate electrode 32 are formed on the silicon epitaxial layer 28 to correspond to the second oxide layer 27, and both side surfaces of the gate electrode 32 and the gate insulating layer 29 are formed. Sidewall spacers 34 are formed on the sidewalls.
또한, 상기 게이트 전극(32) 양측의 실리콘 기판(21)에 LDD 구조를 갖는 소오스/드레인 불순물 영역(35)이 형성된다.In addition, a source / drain impurity region 35 having an LDD structure is formed in the silicon substrate 21 on both sides of the gate electrode 32.
상기와 같은 구조를 갖는 본 발명의 반도체 소자의 트랜지스터의 제조방법은 제4a도에 도시된 바와같이 실리콘 기판(21)상에 제1감광막(도면에 도시하지 않음)을 도포한 후, 사진석판술 및 식각공정으로 상기 실리콘 기판(21)을 선택적으로 표면으로부터 소정 깊이의 트랜치(Trench)(22)를 형성한다.In the method of manufacturing a transistor of a semiconductor device of the present invention having the structure as described above, as shown in FIG. And a trench 22 having a predetermined depth from the surface of the silicon substrate 21 by an etching process.
제4b도에 도시된 바와같이 상기 트랜치(22)를 포함한 실리콘 기판(21)의 전면에 제1산화막(23)과 제1질화막(24)을 차례로 형성한다. 이어, 상기 제1질화막(24)상에 제2감광막(25)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)한다.As shown in FIG. 4B, the first oxide film 23 and the first nitride film 24 are sequentially formed on the entire surface of the silicon substrate 21 including the trench 22. Subsequently, the second photoresist film 25 is coated on the first nitride film 24, and then patterned by exposure and development processes.
제4c도에 도시된 바와같이 상기 패터닝된 제2감광막(25)을 마스크로 하여 상기 제1질화막(24)과 제1산화막(23)을 선택적으로 제거한다. 이어, 상기 제2감광막(25)을 제거하고, 전면에 제2질화막을 형성하고, 상기 제2질화막을 에치백(Etch Back)공정을 실시하여 상기 트랜치(22)의 양측면과 상기 선택적으로 제거된 제1질화막(24) 및 제1산화막(23)의 양측면에 제2질화막 측벽(26)을 형성한다.As shown in FIG. 4C, the first nitride film 24 and the first oxide film 23 are selectively removed using the patterned second photosensitive film 25 as a mask. Subsequently, the second photoresist film 25 is removed, a second nitride film is formed on the entire surface, and the second nitride film is subjected to an etch back process to remove both sides of the trench 22 and the selectively removed. The second nitride film sidewalls 26 are formed on both sides of the first nitride film 24 and the first oxide film 23.
그리고 상기 전면에 산화(Oxidation)를 실시하여 상기 트랜치(22)가 형성된 실리콘기판(21)의 소정부분에 제2산화막(27)을 형성한다.Oxidation is performed on the entire surface to form a second oxide layer 27 on a predetermined portion of the silicon substrate 21 on which the trench 22 is formed.
제4d도에 도시된 바와같이 습식식각(Wet Etch)을 통하여 상기 제1질화막(24)과 제2질화막 측벽(26)을 제거한다. 이어, 상기 트랜치(22)가 형성된 실리콘 기판(21)의 전면에 에피택셜(Epitaxial)성장에 의해 실리콘 에피택셜층(28)을 형성하고, 상기 실리콘 기판(21)의 표면과 동일높이로 상기 실리콘 에피택셜층(28)을 선택적으로 제거한다.As shown in FIG. 4D, the first nitride layer 24 and the second nitride layer sidewall 26 are removed by wet etching. Subsequently, a silicon epitaxial layer 28 is formed on the entire surface of the silicon substrate 21 on which the trench 22 is formed by epitaxial growth, and the silicon is flush with the surface of the silicon substrate 21. The epitaxial layer 28 is selectively removed.
제4e도에 도시된 바와같이 상기 제1산화막(23)을 제거하고, 전면에 게이트 절연막(29) 및 게이트 전극용 폴리 실리콘층(30)을 형성하고, 상기 폴리 실리콘층(30)상에 제3감광막(31)을 도포한 후, 상기 실리콘 기판(21)내에 형성된 제2산화막(27)깃과 대응되도록 상기 제3 감광막(31)을 노광 및 현상공정으로 패터닝한다.As shown in FIG. 4E, the first oxide layer 23 is removed, the gate insulating layer 29 and the polysilicon layer 30 for the gate electrode 30 are formed on the entire surface, and the first oxide layer 23 is removed. After the third photosensitive film 31 is applied, the third photosensitive film 31 is patterned by an exposure and development process so as to correspond to the target of the second oxide film 27 formed in the silicon substrate 21.
제4f도에 도시된 바와같이 상기 패터닝된 제3감광막(31)을 마스크로 하여 상기 폴리 실리콘층(30)과 게이트 절연막(29)을 선택적으로 제거하여 게이트 전극(32)을 형성한다. 이어, 상기 게이트 전극()2)을 마스크로 하여 저농도 불순물 이온을 주입하여 양측의 실리콘 기판(21)내에 LDD(Lightiy Doped Drain) 영역(33)을 형성한다.As shown in FIG. 4F, the polysilicon layer 30 and the gate insulating layer 29 are selectively removed using the patterned third photoresist layer 31 as a mask to form a gate electrode 32. Subsequently, lightly doped drain (LDD) regions 33 are formed in both silicon substrates 21 by implanting low concentration impurity ions using the gate electrode 2 as a mask.
제4g도에 도시된 바와같이 상기 게이트 전극(32)을 포함한 전면에 절연막을 형성하고, 에치백 공정을 실시하여 상기 게이트 전극(32)의 양측면에 측벽 스페이서(34)를 형성한다. 이어, 상기 게이트 전극(32) 및 측벽 스페이서(34)를 마스크로 하여 고농도 불순물 이온을 주입하여 상기 양측의 실리콘 기판(21)내에 형성된 상기 LDD 영역(33)자 연결되는 소오스/드레인 불순물 영역(35)을 형성한다.As shown in FIG. 4G, an insulating film is formed on the entire surface including the gate electrode 32 and an etch back process is performed to form sidewall spacers 34 on both sides of the gate electrode 32. Subsequently, source / drain impurity regions 35 connected to the LDD regions 33 formed in the silicon substrate 21 on both sides by implanting high concentration impurity ions using the gate electrode 32 and the sidewall spacers 34 as masks. ).
이상에서 설명한 바와같이 본 발명의 반도체 소자의 트랜지스터의 구조 및 제조방법에 있어서 채널(Channel)영역 아래에 펀치쓰로우(Punchthrough) 방지용 절연막을 형성함으로써 고집적 디바이스를 형성하더라도 펀치쓰로우를 방지하는 효과가 있다.As described above, in the structure and manufacturing method of the transistor of the semiconductor device of the present invention, the punch-through prevention insulating film is formed under the channel region, thereby preventing punch-throw even when a highly integrated device is formed. have.
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| KR100593734B1 (en) | 2004-03-05 | 2006-06-28 | 삼성전자주식회사 | Transistors of a semiconductor device having a channel region in the channel portion hole and manufacturing methods thereof |
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