KR19990049060A - Transistors and manufacturing methods thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor for forming a trench in a substrate in a channel region and to increasing the channel length to improve the characteristics of the device and a method of manufacturing the same.

The transistor of the present invention and a method of manufacturing the same have a method of forming a substrate having a plurality of trenches in a channel region, a gate electrode having a gate insulating film on the substrate of the channel region, and forming impurity regions in the substrate surfaces on both sides of the gate electrode. It features.

Description

Transistors and manufacturing methods thereof

TECHNICAL FIELD The present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a transistor for improving the characteristics of a device and a method for manufacturing the same.

1 is a cross-sectional view illustrating a transistor according to the prior art, and FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the transistor according to the prior art.

As shown in FIG. 1, a transistor according to the related art has a gate electrode 13 formed on a gate region 13 and a gate electrode 13 formed in a channel region on a p-type semiconductor substrate 11. Cap gate oxide film 14 formed on the substrate, LDD regions 16 formed on the surface of the semiconductor substrate 11 on both sides of the gate electrode 13, and semiconductor substrates on both sides of the gate electrode 13 and the cap gate oxide film 14. A third oxide film sidewall 17 formed on (11) and a source / drain impurity region 18 formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode including the third oxide film sidewall 17. .

In the method of manufacturing a transistor according to the prior art, as shown in FIG. 2A, a first oxide film 12a is grown on a p-type semiconductor substrate 11 by a thermal oxidation process, and then polycrystalline silicon is formed on the first oxide film 12a. 13a and the second oxide film 14a are sequentially formed.

As shown in FIG. 2B, a first photosensitive film 15 is coated on the second oxide film 14a, and the first photosensitive film 15 is selectively exposed and developed so that only the portion where the gate electrode is to be formed remains.

Then, the second oxide film 14a, the polycrystalline silicon 13a, and the first oxide film 12a are selectively etched using the selectively exposed and developed first photosensitive film 15 as a mask. The gate electrode 13 and the cap gate oxide film 14 are formed.

As shown in FIG. 2C, after the first photosensitive film 15 is removed, a low concentration n-type impurity ion implantation process is performed on the entire surface using the gate electrode 13 and the cap gate oxide film 14 as a mask, and drive-in ( Drive-in diffusion forms lightly doped drain (LDD) regions 16 in the surface of the semiconductor substrate 11 on both sides of the gate electrode 13.

As shown in FIG. 2D, a third oxide film is formed on the entire surface including the gate electrode 13, and the third oxide film is etched back to both the gate electrode 13 and the cap gate oxide film 14. The third oxide film sidewall 17 is formed.

Then, a high concentration n-type impurity ion implantation process is performed using the cap gate oxide layer 14 and the third oxide layer sidewall 17 as a mask, and the source / drain impurity region 18 is formed in the semiconductor substrate 11 by driving in diffusion. To form.

However, in the conventional transistor and its manufacturing method, the channel length between the source region and the drain region is shortened according to the integration of semiconductor devices, so that a short channel, a hot carrier, and a punch-through are performed. The same phenomenon occurs, there is a problem in lowering the characteristics of the device.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a transistor and a method for manufacturing the same, which improve the characteristics of the device by increasing the channel length by forming a trench in the substrate of the channel region.

1 is a structural cross-sectional view showing a transistor according to the prior art

2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

3 is a structural cross-sectional view showing a transistor according to an embodiment of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 first photosensitive film

33: trench 34: gate oxide film

35 gate electrode 36 cap gate oxide film

37: second photosensitive film 38: LDD region

39: third oxide film sidewall 40: source / drain impurity region

The transistor of the present invention comprises a substrate having a plurality of trenches in a channel region, a gate electrode formed with a gate insulating film on the substrate of the channel region, and an impurity region formed in the substrate surface on both sides of the gate electrode. It features.

In the method of manufacturing a transistor of the present invention, the method includes preparing a substrate in which a channel region is defined, etching the substrate to form a plurality of trenches in the substrate of the channel region, and forming a gate insulating layer on the substrate of the channel region. And forming an impurity region in the surface of the substrate on both sides of the gate electrode.

When described in detail with reference to the accompanying drawings a preferred embodiment of the transistor according to the present invention and a manufacturing method thereof as follows.

3 is a cross-sectional view illustrating a transistor according to an exemplary embodiment of the present invention, and FIGS. 4A to 4F are cross-sectional views illustrating a method of manufacturing a transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a transistor according to an exemplary embodiment of the present invention has two trenches 33 having a 'w' shape in a channel region and a p-type semiconductor substrate 31 and a semiconductor substrate 31 in the channel region. A gate electrode 35 formed on the gate electrode 35, a cap gate oxide film 36 formed on the gate electrode 35, and a surface of the semiconductor substrate 31 on both sides of the gate electrode 35. A third oxide film sidewall 39 formed on the semiconductor substrate 31 on both sides of the LDD region 38, the gate electrode 35, and the cap gate oxide film 36, and the third oxide film sidewall 39. It is formed of the source / drain impurity region 40 formed in the surface of the semiconductor substrate 31 on both sides of the gate electrode.

In the method of manufacturing a transistor according to an embodiment of the present invention, as shown in FIG. 4A, a first photosensitive film 32 is coated on a semiconductor substrate 31 having a channel region defined therein and having a p-type.

As shown in FIG. 4B, the first photoresist layer 32 is selectively exposed and developed to be removed only at a portion where two trenches are to be formed in the channel region.

As shown in FIG. 4C, the semiconductor substrate 31 is selectively etched using the selectively exposed and developed first photoresist layer 32 to form two trenches 33 having a 'w' shape.

Here, the channel length is increased by the 'w'-shaped trench 33 formed in the semiconductor substrate 31 in the channel region than the flat channel region.

As shown in FIG. 4D, after the first photosensitive film 32 is removed, a first oxide film is grown on the semiconductor substrate 31 by a thermal oxidation process, and then polycrystalline silicon and a second oxide film are deposited on the first oxide film. Form in turn.

Then, a second photosensitive film 37 is coated on the second oxide film, and the second photosensitive film 37 is selectively exposed and developed so that only the portion where the gate electrode is to be formed remains.

Subsequently, the second oxide film, the polycrystalline silicon, and the first oxide film are selectively etched using the selectively exposed and developed second photosensitive film 37 as a mask to form a gate oxide film 34, a gate electrode 35, and a cap gate oxide film. Form 36.

As shown in FIG. 4E, after the second photosensitive film 37 is removed, a low concentration n-type impurity ion implantation process is performed on the entire surface using the gate electrode 35 and the cap gate oxide film 36 as a mask, and drive-in diffusion. Thus, the LDD region 38 is formed in the surface of the semiconductor substrate 31 on both sides of the gate electrode 35.

As shown in FIG. 4F, a third oxide film is formed on the entire surface including the gate electrode 35, and the third oxide film is etched back to form sidewalls of the third oxide film on both sides of the gate electrode 35 and the cap gate oxide film 36. Form 39.

A high concentration n-type impurity ion implantation process is performed using the cap gate oxide layer 36 and the third oxide layer sidewall 39 as a mask, and the source / drain impurity region 40 is formed in the semiconductor substrate 31 by driving in diffusion. To form.

Since the transistor of the present invention and its manufacturing method form two trenches of 'w' shape on the substrate of the channel region, the channel length is increased than the channel region between the flat source region and the drain region, so that the short channel, Since the occurrence of a phenomenon such as hot carriers and punch throws is prevented, there is an effect of improving device characteristics such as integration and reliability.

Claims (6)

A substrate having a plurality of trenches in the channel region; A gate electrode having a gate insulating film on the substrate of the channel region; And an impurity region formed in a surface of the substrate on both sides of the gate electrode. The method of claim 1, And the substrate has two trenches of 'w' shape in the channel region. The method of claim 1, And the impurity region has an LDD structure. The method according to claim 1 or 3, And an insulating film sidewall formed on the substrate on both sides of the gate electrode so that the impurity region has an LDD structure. Providing a substrate on which a channel region is defined; Etching the substrate such that a plurality of trenches are formed in the substrate in the channel region; Forming a gate electrode having a gate insulating film on the substrate in the channel region; And forming an impurity region in the surface of the substrate on both sides of the gate electrode. The method of claim 5, And forming two trenches of 'w' shape in the substrate of the channel region.