KR100701680B1 - Method for manufacturing transistor in semiconductor device - Google Patents
Method for manufacturing transistor in semiconductor device Download PDFInfo
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- KR100701680B1 KR100701680B1 KR1020000083229A KR20000083229A KR100701680B1 KR 100701680 B1 KR100701680 B1 KR 100701680B1 KR 1020000083229 A KR1020000083229 A KR 1020000083229A KR 20000083229 A KR20000083229 A KR 20000083229A KR 100701680 B1 KR100701680 B1 KR 100701680B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims 3
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- -1 spacer nitride Chemical class 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 소자분리막이 구비된 반도체 기판을 제공하는 단계; 상기 반도체 기판 내의 소오스/드레인 예비 영역에 저농도 불순물 이온주입을 실시하는 단계; 상기 반도체 기판 상에 게이트 형성용 절연막을 증착하는 단계; 상기 게이트 형성용 절연막을 식각하여 반도체 기판의 게이트 형성 영역을 노출시키는 단계; 상기 식각된 게이트 형성용 절연막 및 노출된 반도체 기판 부분 상에 질화막을 증착하는 단계; 상기 질화막을 등방성 과도 식각하여 식각된 게이트 형성용 절연막 측벽에 스페이서를 형성함과 동시에 노출된 반도체 기판 부분을 식각하는 단계; 상기 스페이서가 형성됨과 아울러 노출된 반도체 기판 부분이 식각된 결과물을 어닐링하는 단계; 상기 식각된 반도체 기판 부분 상에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막이 형성된 결과물 전면 상에 게이트용 도전막을 형성하는 단계; 상기 게이트 형성용 절연막이 노출될 때까지 게이트용 도전막을 식각하는 단계; 상기 게이트 형성용 절연막을 제거하는 단계; 및 상기 게이트 형성용 절연막이 제거된 결과물에 고농도 불순물 이온주입을 실시하여 소오스/드레인 영역을 형성하는 단계;를 포함하는 것을 특징으로 한다. 이에 의해, 채널길이를 확보할 수 있다.The present invention relates to a method of manufacturing a transistor of a semiconductor device, comprising the steps of: providing a semiconductor substrate provided with a device isolation film; Low concentration impurity ion implantation into a source / drain preliminary region in the semiconductor substrate; Depositing an insulating film for gate formation on the semiconductor substrate; Etching the gate forming insulating layer to expose a gate forming region of the semiconductor substrate; Depositing a nitride film on the etched gate forming insulating film and the exposed semiconductor substrate portion; Isotropically etching the nitride film to form a spacer on the sidewall of the etched gate forming insulating film and etching the exposed portion of the semiconductor substrate; Annealing a result of etching the exposed portion of the semiconductor substrate while the spacer is formed; Forming a gate insulating film on the etched semiconductor substrate portion; Forming a gate conductive film on an entire surface of the resultant product in which the gate insulating film is formed; Etching the gate conductive film until the gate forming insulating film is exposed; Removing the gate forming insulating film; And forming a source / drain region by implanting a high concentration of impurity ions into the resultant from which the gate forming insulating film is removed. As a result, the channel length can be secured.
Description
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 제조공정도.1A to 1D are manufacturing process diagrams for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
10 : 반도체 기판10: semiconductor substrate
11 : 소자분리막11: device isolation film
12 : 게이트 형성용 절연막12: insulating film for gate formation
13 : 스페이서13: spacer
14 : 게이트 절연막14: gate insulating film
15 : 폴리실리콘막15: polysilicon film
16 : 텅스텐 실리사이드막16: tungsten silicide film
17a, 17b : 소오스/드레인 영역17a, 17b: source / drain regions
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 보다 구체적 으로는, 채널 길이를 확보할 수 있는 반도체 소자의 트랜지스터 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device capable of securing a channel length.
최근 소비자의 요구와 원가절감으로 인하여, 초미세 선폭의 디바이스 개발이 불가피한 실정이다. 이에따라, 종래 디램(DRAM)의 트랜지스터 제조방법으로 트랜지스터를 형성할 경우 단채널 여유 부족(short channel margin)으로 단채널 효과가 크며, 또한 핫캐리어 효과(hot carrier effect) 특성이 열화되어 디바이스 특성이 나빠지는 효과를 가져온다.Recently, due to consumer demand and cost reduction, it is inevitable to develop ultra-fine devices. Accordingly, when the transistor is formed by a conventional transistor manufacturing method of DRAM, the short channel effect is large due to a short channel margin, and the hot carrier effect characteristic is deteriorated, thereby deteriorating device characteristics. Brings effect.
따라서, 상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 채널 길이를 확보할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는 것이다.Accordingly, an object of the present invention for solving the above problems is to provide a transistor manufacturing method of a semiconductor device capable of securing a channel length.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소자분리막이 구비된 반도체 기판을 제공하는 단계; 상기 반도체 기판 내의 소오스/드레인 예비 영역에 저농도 불순물 이온주입을 실시하는 단계; 상기 반도체 기판 상에 게이트 형성용 절연막을 증착하는 단계; 상기 게이트 형성용 절연막을 식각하여 반도체 기판의 게이트 형성 영역을 노출시키는 단계; 상기 식각된 게이트 형성용 절연막 및 노출된 반도체 기판 부분 상에 질화막을 증착하는 단계; 상기 질화막을 등방성 과도 식각하여 식각된 게이트 형성용 절연막 측벽에 스페이서를 형성함과 동시에 노출된 반도체 기판 부분을 식각하는 단계; 상기 스페이서가 형성됨과 아울러 노출된 반도체 기판 부분이 식각된 결과물을 어닐링하는 단계; 상기 식각된 반도체 기판 부분 상에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막이 형성된 결과물 전면 상에 게이트용 도전막을 형성하는 단계; 상기 게이트 형성용 절연막이 노출될 때까지 게이트용 도전막을 식각하는 단계; 상기 게이트 형성용 절연막을 제거하는 단계; 및 상기 게이트 형성용 절연막이 제거된 결과물에 고농도 불순물 이온주입을 실시하여 소오스/드레인 영역을 형성하는 단계;를 포함하는 반도체 소자의 트랜지스터 제조방법을 제공한다. In order to achieve the above object, the present invention provides a semiconductor substrate provided with a device isolation film; Low concentration impurity ion implantation into a source / drain preliminary region in the semiconductor substrate; Depositing an insulating film for gate formation on the semiconductor substrate; Etching the gate forming insulating layer to expose a gate forming region of the semiconductor substrate; Depositing a nitride film on the etched gate forming insulating film and the exposed semiconductor substrate portion; Isotropically etching the nitride film to form a spacer on the sidewall of the etched gate forming insulating film and etching the exposed portion of the semiconductor substrate; Annealing a result of etching the exposed portion of the semiconductor substrate while the spacer is formed; Forming a gate insulating film on the etched semiconductor substrate portion; Forming a gate conductive film on an entire surface of the resultant product in which the gate insulating film is formed; Etching the gate conductive film until the gate forming insulating film is exposed; Removing the gate forming insulating film; And forming a source / drain region by implanting a high concentration of impurity ions into the resultant from which the gate forming insulating film is removed.
(실시예)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. (Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 제조공정도이다.1A to 1D are manufacturing process diagrams for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
먼저, 도 1a에 도시된 바와같이, 소자형성 영역을 한정하는 소자분리막(11)을 구비하는 반도체 기판(10)을 제공한다. 이어서, 상기 반도체 기판(10)상에 소오스/드레인 예비영역상에 저농도 불순물 이온주입을 실시한다. 그 다음, 상기 반도체 기판(10)상에 게이트 형성용 절연막(12)을 증착한다. First, as shown in FIG. 1A, a
이어서, 도 1b에 도시된 바와같이, 상기 게이트 형성용 절연막(12) 상부에 게이트 형성 영역을 한정하는 감광막 패턴(미도시)을 형성하고, 상기 감광막 패턴을 식각장벽으로 상기 게이트 형성용 절연막(12)을 식각하여 반도체 기판(10)의 소정부분을 노출시킨다.Subsequently, as shown in FIG. 1B, a photoresist pattern (not shown) defining a gate formation region is formed on the gate
그 다음, 상기 결과물 전면상에 스페이서용 질화막을 증착한다. 이어서, 상기 스페이서용 질화막을 식각하는데 이 때, 등방성 과도식각을 수행하여 상기 식각된 게이트 형성용 절연막(12) 측벽에 스페이서(13)를 형성하면서 반도체 기판(10)의 소정부분을 식각한다. 이 때, 식각되는 반도체 기판의 형태는 바람직하게둥근 반구 형태로 식각된다. 그 다음, 상기 식각에 의한 데미지를 억제하기 위하여 일정 시간동안 어닐링을 실시한다.Then, a nitride film for spacers is deposited on the entire surface of the resultant product. Subsequently, the spacer nitride film is etched. At this time, an isotropic transient etching is performed to etch a predetermined portion of the
그 다음, 도 1c에 도시된 바와같이, 상기 둥근 반구 형태를 포함하는 반도체 기판(10)상에 게이트 절연막(14)을 형성한다. 이 때, 상기 게이트 절연막(14)으로 인하여 상기 둥근 반구 형태가 매립된다. 이어서, 상기 게이트 절연막(14)이 형성된 전체구조 상면에 게이트용 도전막, 예컨대, 폴리실리콘막(15)과 텅스텐 실리사이드막(16)의 적층된 구조를 증착한다.Next, as shown in FIG. 1C, the
그 다음, 도 1d에 도시된 바와같이, 상기 게이트 형성용 절연막(12)이 노출될때까지 상기 텅스텐 실리사이드막(16) 및 폴리실리콘막(15)을 제거하여 플러그 형태를 형성한다. 이어서, 상기 게이트 형성용 절연막(12)을 습식식각하여 제거한다. 그 다음, 상기 단계까지의 결과물상에 고농도 이온주입을 실시하여 소오스/드레인 영역(17a, 17b)을 형성하여 반도체 소자의 트랜지스터를 제조한다.Next, as shown in FIG. 1D, the
상기한 바와같은 본 발명에 따른 반도체 소자의 트랜지스터 제조방법은 다음과 같은 효과가 있다.The transistor manufacturing method of the semiconductor device according to the present invention as described above has the following effects.
상기 게이트의 하부면을 둥근 형태로 형성함에 따라, 상기 소오스/드레인 영역 간의 채널 길이가 확보된다. 이에, 초미세 선폭의 트랜지스터를 형성할 때, 단채널 여유(Short Channel Margin)를 확보하고, 핫캐리어 발생을 억제하여 반도체 소자의 신뢰성을 증대시킬 수 있다.As the bottom surface of the gate is formed in a round shape, a channel length between the source / drain regions is secured. Therefore, when forming a transistor having an ultra fine line width, short channel margin can be secured, hot carrier generation can be suppressed, and reliability of the semiconductor device can be increased.
한편, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, it can change and implement variously in the range which does not deviate from the summary of this invention.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000083229A KR100701680B1 (en) | 2000-12-27 | 2000-12-27 | Method for manufacturing transistor in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000083229A KR100701680B1 (en) | 2000-12-27 | 2000-12-27 | Method for manufacturing transistor in semiconductor device |
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| Publication Number | Publication Date |
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| KR20020053566A KR20020053566A (en) | 2002-07-05 |
| KR100701680B1 true KR100701680B1 (en) | 2007-03-29 |
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|---|---|---|---|
| KR1020000083229A KR100701680B1 (en) | 2000-12-27 | 2000-12-27 | Method for manufacturing transistor in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100701680B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970054083A (en) * | 1995-12-28 | 1997-07-31 | 김광호 | Complementary MOS transistor and its manufacturing method |
| KR19990049060A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Transistors and manufacturing methods thereof |
-
2000
- 2000-12-27 KR KR1020000083229A patent/KR100701680B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970054083A (en) * | 1995-12-28 | 1997-07-31 | 김광호 | Complementary MOS transistor and its manufacturing method |
| KR19990049060A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Transistors and manufacturing methods thereof |
Non-Patent Citations (2)
| Title |
|---|
| 1019970054083 |
| 1019990049060 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020053566A (en) | 2002-07-05 |
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