KR0161873B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR0161873B1 KR0161873B1 KR1019950051414A KR19950051414A KR0161873B1 KR 0161873 B1 KR0161873 B1 KR 0161873B1 KR 1019950051414 A KR1019950051414 A KR 1019950051414A KR 19950051414 A KR19950051414 A KR 19950051414A KR 0161873 B1 KR0161873 B1 KR 0161873B1
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- insulating film
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- impurity region
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 17
- 230000000694 effects Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로 특히, 유효한 채널길이(Effective Channel Length)를 증가시켜 짧은 채널(Short Channel)을 갖는 디바이스(Device)에 적합하도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an effective channel length is increased to be suitable for a device having a short channel.
이를 위한 본 발명의 반도체 소자 제조방법은 기판위에 필드영역과 활성영역으로 정의된 기판위의 필드영역에 필드 절연막을 형성하는 단계, 상기 필드 절연막이 형성된 기판위에 제1절연막을 형성하는 단계, 상기 제1절연막이 형성된 기판위에 불순물 이온을 주입하여 상기 기판에 불순물 영역에 형성하는 단계, 상기 제1절연막을 선택적으로 제거하여 상기 불순물 영역을 노출시키는 단계, 상기 제1절연막을 마스크로 상기 불순물 영역에 트랜치 하여 상기 기판을 노출시키는 단계, 상기 제1절연막을 제거하고 상기 불순물 영역에 라이트 에치와 어닐공정을 실시하는 단계, 상기 불순물 영역을 포함한 기판 전면에 제2절연막을 형성하는 단계, 상기 트랜치영역에 폴리 실리콘을 형성하는 단계, 상기 폴리 실리콘을 포함한 기판 전면 제3절연막을 형성하는 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention for this purpose is to form a field insulating film in the field region on the substrate defined as the field region and the active region on the substrate, forming a first insulating film on the substrate on which the field insulating film is formed, 1) implanting impurity ions onto a substrate on which an insulating film is formed to form an impurity region in the substrate, selectively removing the first insulating film to expose the impurity region, and trenching the first insulating film as a mask in the impurity region Exposing the substrate, removing the first insulating layer, performing a light etch and annealing process on the impurity region, forming a second insulating layer on the entire surface of the substrate including the impurity region, and forming a poly in the trench region. Forming silicon; forming a third insulating film over the substrate including the polysilicon; It comprises the steps:
따라서, 공정이 간단하고 유효 채널길이가 증가함으로써 짧은 채널을 갖는 디바이스에 적합하다.Thus, the process is simple and the effective channel length is increased, making it suitable for devices having short channels.
Description
제1도는 종래의 반도체 소자 제조공정 단면도.1 is a cross-sectional view of a conventional semiconductor device manufacturing process.
제2도는 본 발명의 반도체 소자 제조공정 단면도.2 is a cross-sectional view of a semiconductor device manufacturing process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형 반도체 기판 2 : 필드 산화막1: P-type semiconductor substrate 2: Field oxide film
3 : 제1 HLD층 4 : N형 불순물 영역3: first HLD layer 4: N-type impurity region
5 : 게이트 산화막 6 : 폴리 실리콘5: gate oxide film 6: polysilicon
7 : 제2 HLD층7: second HLD layer
본 발명은 반도체 소자 제조방법에 관한 것으로 특히, 유효한 채널길이(Effective Channel Length)를 증가시켜 짧은 채널(Short Channel)을 갖는 디바이스(Device)에 적합하도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an effective channel length is increased to be suitable for a device having a short channel.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자 제조방법을 설명하면 다음과 같다.Hereinafter, a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings.
제1도는 종래의 반도체 소자 제조공정 단면도이다.1 is a cross-sectional view of a conventional semiconductor device manufacturing process.
제1도(a)와 같이 필드 산화막(2)에 의해 필드영역과 활성영역으로 구분된 P형 반도체 기판(1)상에 제1절연막(3)과 다결정 실리콘 및 제2절연막(5)을 차례로 증착하고, 사진석판술(Photo Lithography) 및 식각공정으로 상기 제1절연막(3), 다결정 실리콘 및 제2절연막(5)을 선택적으로 제거하여 게이트 전극(4)을 형성한다.As shown in FIG. 1A, the first insulating layer 3, the polycrystalline silicon, and the second insulating layer 5 are sequentially formed on the P-type semiconductor substrate 1 divided into the field region and the active region by the field oxide film 2. The gate electrode 4 is formed by selectively removing the first insulating layer 3, the polycrystalline silicon, and the second insulating layer 5 by photolithography and etching.
그리고 저농도의 소오스 및 드레인 영역을 형성하기 위하여 게이트 전극(4)을 마스크로 이용한 셀프얼라인 기술로 활성영역의 상기 P형 반도체 기판(1)에 저농도 N형불순물 이온을 주입하여 게이트 전극(4) 양측의 상기 P형 반도체 기판(1)에 저농도N형 불순물 영역(6)을 형성한다.In order to form a low concentration source and drain region, a low concentration N-type impurity ion is implanted into the P-type semiconductor substrate 1 in the active region by a self-aligned technique using the gate electrode 4 as a mask to form a gate electrode 4. The low concentration N-type impurity region 6 is formed in the P-type semiconductor substrate 1 on both sides.
제1도(b)와 같이 상기 게이트 전극(4)을 포함한 P형 반도체 기판 전면에 제3절연막(7)을 형성한다.As shown in FIG. 1B, a third insulating layer 7 is formed on the entire surface of the P-type semiconductor substrate including the gate electrode 4.
제1도(c)와 같이 상기 제3절연막(7)을 이방성 식각하여 게이트 전극(4) 측면에 절연막 측벽(Side Wall)(7a)을 형성한다.As shown in FIG. 1C, the third insulating layer 7 is anisotropically etched to form sidewalls 7a of sidewalls of the gate electrode 4.
그리고, 상기 게이트 전극(4) 및 절연막 측벽(7a)을 마스크로 이용한 셀프얼라인 기술로 상기 활성영역의 P형 반도체 기판(1)에 고농도의 N형 불순물 이온을 주입하여 상기 절연막 측벽(7a) 양측의 P형 반도체 기판(1)에 고농도 N형 불순물 영역(8)을 형성한다.In addition, a high concentration of N-type impurity ions are implanted into the P-type semiconductor substrate 1 in the active region by a self-aligning technique using the gate electrode 4 and the insulating film sidewall 7a as a mask. High concentration N-type impurity regions 8 are formed in the P-type semiconductor substrates 1 on both sides.
제1도(d)와 같이, 층간 절연을 위해 상기 고농도 N형 불순물 영역(8)위에 HLD층(9)(High Temperature Low Pressure Dielectric)을 형성한다.As shown in FIG. 1D, an HLD layer 9 (High Temperature Low Pressure Dielectric) is formed on the high concentration N-type impurity region 8 for interlayer insulation.
그러나, 이와 같은 종래의 반도체 소자 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, such a conventional semiconductor device manufacturing method has the following problems.
첫째, 짧은 채널효과(Short Channel Effect)로 인해 DIBL(Drain Induced Barrier Lowering)현상이 나타난다.First, the DBL (Drain Induced Barrier Lowering) phenomenon occurs due to the short channel effect.
즉, 게이트와 공핍층 영역에 의한 소오스와 드레인 사이의 전기적 커플링(Coupling)의 상쇄가 완전하기 못하여 드레인에서의 전기력선이 소오스에 작용하여 소오스쪽 전위장벽이 낮아진다.That is, the offset of the electrical coupling between the source and the drain by the gate and the depletion layer region is not perfect, and the electric line of force in the drain acts on the source to lower the source side potential barrier.
둘째, 핫 캐리어 효과(Hot Carrier Effect)에 의한 소자의 신뢰성이 저하된다.Second, the reliability of the device due to the hot carrier effect is degraded.
셋째, GIDL(Gate Induced Darin Leakage) 현상이 나타난다.Third, GIDL (Gate Induced Darin Leakage) phenomenon appears.
넷째, 평탄화가 어려워 후공정에 문제가 있다.Fourth, there is a problem in the post-processing is difficult to flatten.
다섯째, 측벽형성 및 저농도 이온주입 등으로 공정이 복잡하다.Fifth, the process is complicated by sidewall formation and low concentration ion implantation.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써, 기판내에 게이트 전극을 형성함으로써 유효한 채널길이(Effective Channel Length)를 증가시키고 공정을 단순화 하고 평탄화를 개선하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has an object of increasing the effective channel length, simplifying the process, and improving planarization by forming a gate electrode in a substrate.
이와 같은 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 기판위에 필드영역과 활성영역으로 정의된 기판위의 필드영역에 필드 절연막을 형성하는 단계, 상기 필드 절연막이 형성된 기판위에 제1절연막을 형성하는 단계, 상기 제1절연막이 형성된 기판위에 불순물 이온을 주입하여 상기 기판에 불순물 영역을 형성하는 단계, 상기 제1절연막을 선택적으로 제거하여 상기 불순물 영역을 노출시키는 단계, 상기 제1절연막을 마스크로 상기 불순물 영역을 트랜치 하여 상기 기판을 노출시키는 단계, 상기 제1절연막을 제거하고 상기 불순물 영역에 라이트 에치와 어닐공정을 실시하는 단계, 상기 불순물 영역을 포함한 기판 전면에 제2절연막을 형성하는 단계, 상기 트랜치 영역에 폴리 실리콘을 형성하는 단계, 상기 폴리 실리콘을 포함한 기판 전면 제3절연막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is to form a field insulating film in the field region on the substrate defined as a field region and an active region on the substrate, a first insulating film is formed on the substrate on which the field insulating film is formed Forming an impurity region in the substrate by implanting impurity ions onto the substrate on which the first insulating film is formed, selectively removing the first insulating film to expose the impurity region, and using the first insulating film as a mask. Trenching the impurity region to expose the substrate, removing the first insulating layer, performing a light etch and annealing process on the impurity region, and forming a second insulating layer on the entire surface of the substrate including the impurity region; Forming polysilicon in the trench region, prior to the substrate including the polysilicon The yirueojim characterized by including the step of forming a third insulating film.
상기와 같은 본 발명의 반도체 소자 제조방법을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The semiconductor device manufacturing method of the present invention as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명의 반도체 소자 제조공정 단면도이다.2 is a cross-sectional view of the semiconductor device manufacturing process of the present invention.
제2도(a)와 같이, 필드 산화막(2)에 의해 필드영역과 활성영역으로 구분된 P형 반도체 기판(1) 전면에 소오스/드레인 이온주입의 손상을 줄이기 위해 제1 HLD(High Temperature Low Pressure Dielectric)층(3)을 증착하고, 상기 제1 HLD층(3)이 형성된 P형 반도체 기판(1)전면에 5가의 N형 불순물인 아세닉(As)이온을 주입하여 N형 불순물 영역(4)을 형성한다.As shown in FIG. 2A, in order to reduce damage of source / drain ion implantation on the entire surface of the P-type semiconductor substrate 1 divided into the field region and the active region by the field oxide film 2, the first HLD (High Temperature Low) A pressure dielectric layer 3 and implanting an ions of five valent N-type impurities into the entire surface of the P-type semiconductor substrate 1 on which the first HLD layer 3 is formed. 4) form.
이때, 아세닉(As) 이온에 가해지는 에너지는 약 80KeV이고 도즈(Dose)량은 약 4.5E15/㎠로 한다.In this case, the energy applied to the ascetic (As) ions is about 80 KeV and the dose is about 4.5E15 / cm 2.
제2도(b)와 같이, 사진석판술 및 식각공정으로 게이트 영역을 정의하고 상기 제1 HLD(3)을 선택적으로 제거하여 상기 N형 불순물 영역(4)이 노출되도록 한다. 제2도(c)와 같이, 상기 제1HLD층(3)을 마스크로 하여 상기 노출된 N형 불순물 영역(4)을 등방성 식각으로 트랜치 하여 상기 P형 반도체 기판(1)을 노출시킨다.As shown in FIG. 2 (b), the gate region is defined by photolithography and etching, and the first HLD 3 is selectively removed to expose the N-type impurity region 4. As illustrated in FIG. 2C, the exposed N-type impurity region 4 is isotropically etched using the first HLD layer 3 as a mask to expose the P-type semiconductor substrate 1.
즉, 상기 N형 불순물 영역(4)을 트랜치에 의해 소오스/드레인 영역으로 구분된다.That is, the N-type impurity region 4 is divided into source / drain regions by a trench.
이때, N형 불순물 영역(4)은 P형 반도체 기판(1) 보다 도우핑(Doping) 농도가 높기 때문에 측면 식각(Side Etching)량이 크다.At this time, since the doping concentration of the N-type impurity region 4 is higher than that of the P-type semiconductor substrate 1, the amount of side etching is greater.
그리고 트랜치에 의한 소오스/드레인의 접합 깊이(Junction Depth)는 이온주입시 이온의 농도와 에너지로 조절한다.The junction depth of the source / drain by the trench is controlled by the ion concentration and energy during ion implantation.
제2도(d)와 같이, 상기 제1 HLD층(3)을 제거하고 식각손상(Etch Damage)을 감소시키기 위해 라이트 에치(Light Etch) 및 소오스/드레인 어닐(Anneal)을 실시한다.As shown in FIG. 2 (d), the light etch and the source / drain annealing are performed to remove the first HLD layer 3 and reduce etching damage.
그리고 상기 트랜치된 N형 불순물 영역(4)을 포함한 P형 반도체 기판(1) 전면에 게이트 산화막(5)을 형성한다.A gate oxide film 5 is formed on the entire surface of the P-type semiconductor substrate 1 including the trenched N-type impurity region 4.
이때, 게이트 산화막(5)은 산화공정시 상기 N형 불순물 영역(4)인 소오스/드레인 영역이 상기 P형 반도체 기판(1)보다 도우핑 농도가 높기 때문에 산화율이 증가하여 상기 소오스/드레인 영역은 두껍게 형성되고, 상기 노출된 P형 반도체 기판(1)위에는 얇게 형성된다.At this time, since the source / drain region of the N-type impurity region 4 has a higher doping concentration than the P-type semiconductor substrate 1 in the oxidation process, the gate oxide film 5 increases the oxidation rate, so that the source / drain region It is formed thick, and is formed thin on the exposed P-type semiconductor substrate (1).
제2도(e)와 같이, 상기 게이트 산화막(5)위에 폴리 실리콘(6)을 증착하고 에치백(Etch Back)으로 상기 폴리 실리콘(6)을 식각하여, 상기 트랜치된 영역에만 남도록 하여 게이트를 형성한다.As shown in FIG. 2 (e), the polysilicon 6 is deposited on the gate oxide film 5, and the polysilicon 6 is etched with an etch back, so that the gate is left only in the trenched region. Form.
이상에서 설명한 바와 같이, 본 발명의 반도체 소자 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention has the following effects.
첫째, 유효한 채널길이(Effective Channel Length)를 증가시킴으로써 핫 캐리어 효과(Hot Carrier Effect)가 줄어든다.First, the Hot Carrier Effect is reduced by increasing the Effective Channel Length.
그러므로 짧은 채널을 갖는 디바이스에 적합하다.It is therefore suitable for devices with short channels.
둘째, 소오스/드레인 영역의 게이트 산화막이 두껍게 형성되므로 GIDL(Gate Induced Drain Leakage) 특성이 개선된다.Second, since the gate oxide layer of the source / drain region is formed thick, the gate induced drain leakage (GIDL) characteristics are improved.
셋째, 게이트의 일정한 일렉트릭 필드(Electric Field)에 의해 옥사이드 브레이크 다운(Oxide Break Down)이 개선된다.Third, the oxide break down is improved by a constant electric field of the gate.
넷째, 평탄화가 개선되어 후공정이 용이하고 특히 TET 셀 구조를 갖는 SRAM 공정이 용이하다.Fourth, the planarization is improved, so that the post-process is easy, and in particular, the SRAM process having the TET cell structure is easy.
다섯째, 측벽형성 및 저농도 불순물 이온주입 등을 하지 않으므로 공정이 간단하다.Fifth, the process is simple because sidewall formation and low concentration impurity ion implantation are not performed.
Claims (5)
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| KR1019950051414A KR0161873B1 (en) | 1995-12-18 | 1995-12-18 | Method of manufacturing semiconductor device |
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| KR1019950051414A KR0161873B1 (en) | 1995-12-18 | 1995-12-18 | Method of manufacturing semiconductor device |
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