KR100298874B1 - Method for forming transistor - Google Patents

Method for forming transistor Download PDF

Info

Publication number
KR100298874B1
KR100298874B1 KR1019970069071A KR19970069071A KR100298874B1 KR 100298874 B1 KR100298874 B1 KR 100298874B1 KR 1019970069071 A KR1019970069071 A KR 1019970069071A KR 19970069071 A KR19970069071 A KR 19970069071A KR 100298874 B1 KR100298874 B1 KR 100298874B1
Authority
KR
South Korea
Prior art keywords
semiconductor substrate
gate
forming
oxide film
impurities
Prior art date
Application number
KR1019970069071A
Other languages
Korean (ko)
Other versions
KR19990050035A (en
Inventor
김성진
Original Assignee
김영환
현대반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체 주식회사 filed Critical 김영환
Priority to KR1019970069071A priority Critical patent/KR100298874B1/en
Publication of KR19990050035A publication Critical patent/KR19990050035A/en
Application granted granted Critical
Publication of KR100298874B1 publication Critical patent/KR100298874B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for forming a transistor is provided to reduce GIDL(Gate Induced Drain Leakage) current by reducing a concentrating phenomenon of an electric field between a drain region and a gate to an edge portion of a gate. CONSTITUTION: A silicon nitride layer is formed on a p type semiconductor substrate(21). The semiconductor substrate(21) is patterned by using a photo-lithography method. The first oxide layer(25) is formed on the semiconductor substrate(21). The silicon nitride layer is removed. The second oxide layer(27) is formed on the semiconductor substrate(21). A polysilicon layer(29) is formed on the second oxide layer(27). A photo-resist is deposited on the polysilicon layer(29). A photoresist pattern is formed by performing an exposure process and a development process. A gate(29) is formed by etching the polysilicon layer(29), the second oxide layer(27), and the first oxide layer(25). A low density dopant region is formed by implanting low density dopant ions into the semiconductor substrate(21). A sidewall(33) is formed on a side of the gate(29). A high density dopant region(35) is formed on an exposed portion of the semiconductor substrate(21).

Description

트랜지스터의 형성 방법How to form a transistor

본 발명은 트랜지스터의 형성 방법에 관한 것으로서, 특히, GIDL(Gate Induced Drain Leakage) 전류를 감소시킬 수 있는 트랜지스터의 형성 방법에 관한 것이다.The present invention relates to a method of forming a transistor, and more particularly, to a method of forming a transistor capable of reducing a gate induced drain leakage (GIDL) current.

반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져 내부의 전계 강도가 증가된다. 이러한 전계 강도의 증가는 드레인 영역에서 웰쪽으로 전위장벽을 넘지않고도 밴드 투 밴드 터널링(band to band tunneling)에 의해 누설전류를 발생시키는 GIDL(Gate Induced Drain Leakage : 이하, GIDL이라 칭함) 전류를 발생시키게 된다. 그러므로, GIDL 전류에 의한 소자 특성의 저하를 감소시키기 위해 LDD(Lightly Doped Drain) 등과 같이 드레인 구조를 변화시킨 구조를 사용한다.As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a GIDL (Gate Induced Drain Leakage) current to generate leakage current by band to band tunneling without crossing the potential barrier toward the well in the drain region. do. Therefore, in order to reduce the deterioration of device characteristics due to the GIDL current, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like is used.

도 1a 내지 도 1c는 종래 기술에 따른 트랜지스터의 형성 방법을 도시하는 공정도이다.1A to 1C are process diagrams showing a method of forming a transistor according to the prior art.

종래에는 도 1a에 나타낸 바와 같이 p형의 반도체기판(11) 상에 열산화의 방법으로 게이트 산화막(13)을 형성하고, 이 게이트 산화막(13) 상에 불순물이 도핑된 다결정실리콘(Polysilicon)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 다결정실리콘층(15)을 형성하고, 상기 다결정실리콘층(15) 상에 포토레지스트(Photoresist : 16)를 도포하고, 노광 및 현상하여 상기 다결정실리콘층(15)의 소정 부분을 노출시키는 포토레지스트(16) 패턴을 형성한다.Conventionally, as shown in FIG. 1A, a gate oxide film 13 is formed on a p-type semiconductor substrate 11 by thermal oxidation, and polysilicon doped with impurities on the gate oxide film 13 is formed. Deposition by Chemical Vapor Deposition (hereinafter referred to as CVD) method to form a polysilicon layer 15, a photoresist (16) is applied on the polysilicon layer 15, exposure and The pattern is formed to form a photoresist 16 exposing a predetermined portion of the polysilicon layer 15.

그리고, 도 1b와 같이 상기 포토레지스트(16) 패턴을 마스크로 사용하여 상기 다결정실리콘층(15) 및 게이트산화막(13)을 순차적으로 이방성 식각하여 상기 p형의 반도체기판(11) 상에 게이트(15)를 형성한다. 그런 후에, 상기 게이트(15)를 마스크로 사용하여 p형의 반도체기판(11)에 상기 반도체기판(11)과 반대 도전형의 불순물, 즉, n형의 아세닉(As), 또는 인(P) 등의 불순물을 저농도로 이온주입하여 LDD 구조를 형성하는 저농도 불순물영역(17)을 형성한다.As shown in FIG. 1B, the polysilicon layer 15 and the gate oxide layer 13 are sequentially anisotropically etched using the photoresist 16 pattern as a mask to form a gate on the p-type semiconductor substrate 11. 15). Thereafter, using the gate 15 as a mask, an impurity of opposite conductivity type to the p-type semiconductor substrate 11 as opposed to the semiconductor substrate 11, that is, an n-type arsenic (As) or phosphorus (P) is used. Ion implantation at low concentration to form a low concentration impurity region 17 for forming an LDD structure.

다음에는, 도 1c에 나타낸 바와 같이, 상기 게이트(15)와 저농도 불순물영역(17)이 형성된 반도체기판(11) 상에 CVD 방법으로 두꺼운 산화막이나 질화막을 형성한 후 에치백(Etch-back) 공정을 행하여 게이트(15)의 측면에 측벽(Side-Wall : 19)을 형성한다. 그리고, 상기 게이트(15)와 측벽(19)을 마스크로 사용하여 상기 반도체기판(11)의 노출된 부분에 상기 저농도 불순물영역(17)과 동일한 도전형의 불순물, 즉, n형의 아세닉(As), 또는 인(P) 불순물을 고농도로 이온주입하여 소오스 및 드레인영역으로 이용되는 고농도 불순물영역(20)을 형성한다. 상기에서, 게이트(15) 하부의 불순물이 도핑되지 않은 부분은 채널 영역이 된다.Next, as shown in FIG. 1C, an etch-back process is performed after a thick oxide film or nitride film is formed on the semiconductor substrate 11 on which the gate 15 and the low concentration impurity region 17 are formed by a CVD method. To form sidewalls 19 on the side of the gate 15. Then, using the gate 15 and the sidewall 19 as a mask, the same conductivity type impurities as the low concentration impurity region 17 in the exposed portion of the semiconductor substrate 11, that is, n-type arsenic ( As) or phosphorus (P) impurities are implanted at high concentration to form a high concentration impurity region 20 used as a source and a drain region. In the above, a portion of the gate 15 that is not doped with impurities is a channel region.

상술한 바와 같이 종래의 트랜지스터의 제조는 반도체기판에 게이트를 형성하고, 반도체기판과는 다른 도전형의 불순물을 저농도로 이온주입하여 저농도 불순물영역을 형성한 후, 게이트의 측면에 측벽을 형성하고, 상기 게이트와 측벽을 마스크로 사용하여 소오스 및 드레인영역을 형성하기위해 저농도 불순물영역과 동일한 도전형의 불순물을 고농도로 이온주입하여 고농도 불순물영역을 형성한다.As described above, in the conventional transistor manufacturing, a gate is formed on a semiconductor substrate, a low concentration impurity region is formed by ion implanting impurities of a conductivity type different from that of the semiconductor substrate at low concentration, and then a sidewall is formed on the side of the gate. In order to form a source and a drain region using the gate and the sidewall as a mask, a high concentration impurity region is formed by ion implantation of impurities of the same conductivity type as the low concentration impurity region at a high concentration.

그러나, 상술한 바와 같이 종래의 기술은 게이트 산화막의 두께가 일정하여 반도체소자가 미세해지고, 상기 게이트산화막의 두께가 얇을 경우에는 드레인영역과 게이트 사이의 전계가 게이트의 모서리 부분에 집중되여 GIDL 전류가 흐를 뿐만 아니라, 소자의 신뢰성을 감소시키는 문제점이 있었다.However, as described above, in the conventional technology, the thickness of the gate oxide film is constant, so that the semiconductor device becomes fine. When the thickness of the gate oxide film is thin, the electric field between the drain region and the gate is concentrated at the edge of the gate, whereby the GIDL current is increased. In addition to the flow, there was a problem of reducing the reliability of the device.

따라서, 본 발명의 목적은 드레인영역과 게이트 사이의 전계가 게이트의 모서리 부분에 집중되는 것을 완화시켜 GIDL 전류를 감소시킬 수 있는 트랜지스터의 형성 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for forming a transistor that can reduce the GIDL current by alleviating the concentration of the electric field between the drain region and the gate in the corner portion of the gate.

상기 목적을 달성하기 위한 본 발명에 따른 트랜지스터의 형성 방법은 제 1 도전형을 갖는 반도체기판 상에 질화막을 형성하고 패터닝하여 상기 반도체기판의 소정 부분에만 잔류시키는 공정과, 상기 반도체기판 상에 제 1 산화막을 형성하고 상기 질화막을 제거하여 반도체기판의 소정 부분을 노출시키는 공정과, 상기 제 1 산화막 및 노출된 반도체기판 상에 제 2 산화막 및 불순물이 도핑된 다결정실리콘층을 형성하는 공정과, 상기 다결정실리콘층, 제 2 및 제 1 산화막을 패터닝하여 게이트를 형성하는 공정과, 상기 제 1 도전형의 반도체기판 상에 상기 게이트를 마스크로 제 2 도전형의 불순물을 저농도로 이온주입하는 공정과, 상기 게이트의 측면에 측벽을 형성하는 공정과, 상기 제 1 도전형의 반도체기판 상에 상기 게이트 및 측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 이온주입하여 고농도 불순물영역을 형성하는 공정을 구비한다.A method of forming a transistor according to the present invention for achieving the above object is a step of forming and patterning a nitride film on a semiconductor substrate having a first conductivity type to remain only in a predetermined portion of the semiconductor substrate, and a first on the semiconductor substrate Forming an oxide film and removing the nitride film to expose a predetermined portion of the semiconductor substrate, forming a second silicon film and a polycrystalline silicon layer doped with impurities on the first oxide film and the exposed semiconductor substrate, and the polycrystal Patterning a silicon layer, a second and a first oxide film to form a gate, implanting a second conductive impurity at low concentration onto the first conductive semiconductor substrate using the gate as a mask, and Forming a sidewall on the side of the gate, and using the gate and the sidewall as a mask on the first conductive semiconductor substrate And ion implantation of impurities of the second conductivity type at a high concentration to form a high concentration impurity region.

도 1a 내지 도 1c는 종래 기술에 따른 트랜지스터의 형성 방법을 도시하는 공정도.1A to 1C are process diagrams showing a method of forming a transistor according to the prior art.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 형성 방법을 도시하는 공정도.2A to 2D are process diagrams illustrating a method of forming a transistor according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>

21 : 반도체기판 25 : 제 1 산화막21 semiconductor substrate 25 first oxide film

27 : 제 2 산화막 29 : 게이트27: second oxide film 29: gate

33 : 측벽 35 : 불순물영역33 side wall 35 impurity region

이하, 첨부된 도면을 참조하여 본 발명을 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 형성 방법을 도시하는 공정도이다.2A to 2D are flowcharts illustrating a method of forming a transistor according to an embodiment of the present invention.

본 방법은 도 2a에 나타낸 바와 같이 p형의 반도체기판(31) 상에 질화실리콘(Si3N4)층을 형성하고, 포토리쏘그래피(Photolithograpy) 방법으로 패터닝하여 상기 반도체기판(31) 상의 소정 부분에만 상기 질화실리콘층(23)을 남긴다. 그리고, 상기 반도체기판(31) 상에 상기 잔존하는 질화실리콘층(23)과 같은 두께의 제 1 산화막(25)을 형성한다.As shown in FIG. 2A, a silicon nitride (Si 3 N 4 ) layer is formed on a p-type semiconductor substrate 31, and is patterned by a photolithograpy method to form a predetermined layer on the semiconductor substrate 31. Only the portion leaves the silicon nitride layer 23. A first oxide film 25 having the same thickness as the remaining silicon nitride layer 23 is formed on the semiconductor substrate 31.

그런 후에, 도 2b에 나타낸 바와 같이 상기 잔존하는 질화실리콘층(23)을 제거하고, 다시 상기 반도체기판(31) 상에 제 2 산화막(27)을 형성하고, 상기 제 2 산화막(27) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착하여 다결정실리콘층(29)을 형성한다. 그리고, 상기 다결정실리콘층(29) 상에 포토레지스트(30)를 도포하고, 노광 및 현상하여 상기 다결정실리콘층(29)의 소정 부분을 노출시키는 포토레지스트(30) 패턴을 형성한다.Thereafter, as shown in FIG. 2B, the remaining silicon nitride layer 23 is removed, and a second oxide film 27 is formed on the semiconductor substrate 31, and then on the second oxide film 27. The polysilicon doped with the impurity is deposited by CVD to form the polysilicon layer 29. Then, the photoresist 30 is coated on the polysilicon layer 29, exposed and developed to form a photoresist 30 pattern exposing a predetermined portion of the polysilicon layer 29.

그리고, 도 2c와 같이 상기 잔존하는 포토레지스트(30) 패턴을 마스크로 사용하여 상기 다결정실리콘층, 제 2, 제 1 산화막(29)(27)(25)을 순차적으로 식각하여 게이트(29)를 형성한다. 상기 게이트(29)가 형성된 p형의 반도체기판(21) 상에 상기 게이트(29)를 마스크로 사용하여 상기 반도체기판(21)과 도전형이 다른, 즉, n형의 아세닉(As), 또는, 인(P) 등과 같은 불순물을 저농도로 이온주입하여 LDD 구조를 형성하기 위한 저농도 불순물영역(31)을 형성한다.As illustrated in FIG. 2C, the polysilicon layer, the second and first oxide layers 29, 27, and 25 are sequentially etched using the remaining photoresist 30 pattern as a mask to form the gate 29. Form. By using the gate 29 as a mask on the p-type semiconductor substrate 21 on which the gate 29 is formed, the conductivity type is different from that of the semiconductor substrate 21, that is, an n-type arsenic (As), Alternatively, a low concentration impurity region 31 for forming an LDD structure is formed by ion implantation of impurities such as phosphorus (P) at a low concentration.

다음에는, 도 2d에 나타낸 바와 같이, 상기 게이트(29)와 저농도 불순물영역(31)이 형성된 반도체기판(21) 상에 CVD 방법으로 두꺼운 산화막이나 질화막을 형성한 후 에치백 공정을 행하여 게이트(29)의 측면에 측벽(33)을 형성한다. 그리고, 상기 게이트(29) 및 측벽(33)을 마스크로 사용하여 상기 반도체기판(21)의 노출된 부분에 상기 저농도 불순물영역(31)과 동일한 도전형의 불순물, 즉, n형의 아세닉(As), 또는, 인(P) 불순물을 고농도로 이온주입하여 소오스 및 드레인영역으로 이용되는 고농도 불순물영역(35)을 형성한다. 상기에서, 제 1 및 제 2 산화막(25)(27)이 게이트산화막이 되고, 게이트(29) 하부의 불순물이 도핑되지 않은 부분은 채널 영역이 된다.Next, as shown in FIG. 2D, a thick oxide film or a nitride film is formed on the semiconductor substrate 21 on which the gate 29 and the low concentration impurity region 31 are formed by a CVD method, followed by an etch back process to perform the gate 29. The side wall 33 is formed in the side of the (). Then, using the gate 29 and the sidewall 33 as a mask, an impurity of the same conductivity type as that of the low concentration impurity region 31 in the exposed portion of the semiconductor substrate 21, that is, an n-type arsenic ( As) or phosphorus (P) impurities are implanted at high concentration to form a high concentration impurity region 35 used as a source and a drain region. In the above description, the first and second oxide films 25 and 27 become gate oxide films, and portions of the gate 29 that are not doped with impurities are channel regions.

상술한 바와 같이 본 발명에서는 반도체기판 상에 질화막을 형성하고 패터닝하여 부분적으로 남기고, 질화막이 없는 부분에 제 1 산화막을 형성하고, 질화막을 제거한 후, 상기 제 1 산화막 상에 제 2 산화막을 형성하여 게이트와 불순물영역 사이의 게이트산화막을 제 1 산화막의 두께만큼 국부적으로 두껍게 형성하고, 상기 부분적으로 두께가 증가한 게이트산화막 상에 게이트를 형성하고 저농도 이온주입 후, 상기 게이트의 측벽을 형성하고, 고농도 이온주입을 하여 LDD 구조의 트랜지스터를 형성하였다.As described above, in the present invention, a nitride film is formed on the semiconductor substrate and partially patterned to leave the nitride film. A first oxide film is formed on a portion without the nitride film, and the nitride film is removed, and then a second oxide film is formed on the first oxide film. A gate oxide film between the gate and the impurity region is locally thickened by the thickness of the first oxide film, a gate is formed on the partially increased gate oxide film, and after implanting low concentration ions, a sidewall of the gate is formed, and high concentration ions are formed. Injection was performed to form an LDD structure transistor.

따라서 본 발명에 따른 트랜지스터는 게이트의 불순물영역쪽 하부의 게이트 산화막을 부분적으로 두껍게 형성하여 게이트와 드레인영역 사이의 전계를 완화시키므로 GIDL 전류를 감소시켜 소자의 신뢰성을 개선하는 잇점이 있다.Therefore, the transistor according to the present invention forms a partially thick gate oxide film under the impurity region of the gate to mitigate the electric field between the gate and the drain region, thereby reducing the GIDL current and improving the reliability of the device.

Claims (1)

제 1 도전형을 갖는 반도체기판 상에 질화막을 형성하고 패터닝하여 상기 반도체기판의 소정 부분에만 잔류시키는 공정과, 상기 반도체기판 상에 상기 질화막과 동일두께로 제 1산화막을 형성하고 상기 질화막을 제거하여 반도체기판의 소정 부분을 노출시키는 공정과, 상기 제 1 산화막 및 노출된 반도체기판 상에 제 2 산화막 및 불순물이 도핑된 다결정실리콘층을 순차적으로 형성하는 공정과, 상기 불순물이 도핑된 다결정실리콘층 상에 게이트 형성영역이 정의된 마스크패턴을 형성하는 공정과, 상기 마스크패턴을 마스크로 하여 상기 다결정실리콘층, 제 2 및 제 1 산화막을 제거하여 게이트전극과 상기 제 2산화막 및 하부양측에 제 1산화막이 잔류되어 이루어진 게이트절연막을 형성하는 공정과, 상기 반도체기판 상에 상기 게이트를 마스크로 제 2 도전형의 불순물을 저농도로 이온주입하는 공정과, 상기 게이트의 측면에 측벽을 형성하는 공정과, 상기 반도체기판 상에 상기 게이트 및 측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 이온주입하여 고농도 불순물영역을 헝성하는 공정을 구비하는 트랜지스터의 형성 방법.Forming and patterning a nitride film on a semiconductor substrate having a first conductivity type and leaving only a predetermined portion of the semiconductor substrate; forming a first oxide film on the semiconductor substrate with the same thickness as the nitride film and removing the nitride film. Exposing a predetermined portion of the semiconductor substrate, sequentially forming a second oxide film and a polycrystalline silicon layer doped with impurities on the first oxide film and the exposed semiconductor substrate, and on the polycrystalline silicon layer doped with the impurities Forming a mask pattern in which a gate formation region is defined, and removing the polysilicon layer, the second and first oxide films using the mask pattern as a mask, and removing the gate electrode, the second oxide film, and the first oxide film on both sides of the lower portion. Forming a gate insulating film comprising the remaining residues; and using the gate as a mask on the semiconductor substrate as a mask Ion implantation of conductive impurities at low concentration, forming sidewalls on the side surfaces of the gate, and ion implantation at high concentration using impurities of the second conductivity type using the gate and sidewalls as masks on the semiconductor substrate. And forming a high concentration impurity region.
KR1019970069071A 1997-12-16 1997-12-16 Method for forming transistor KR100298874B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970069071A KR100298874B1 (en) 1997-12-16 1997-12-16 Method for forming transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970069071A KR100298874B1 (en) 1997-12-16 1997-12-16 Method for forming transistor

Publications (2)

Publication Number Publication Date
KR19990050035A KR19990050035A (en) 1999-07-05
KR100298874B1 true KR100298874B1 (en) 2001-11-22

Family

ID=37528599

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970069071A KR100298874B1 (en) 1997-12-16 1997-12-16 Method for forming transistor

Country Status (1)

Country Link
KR (1) KR100298874B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444918B1 (en) * 2001-03-14 2004-08-18 미쓰비시덴키 가부시키가이샤 Method of manufacturing semiconductor device
CN103730343A (en) * 2012-10-10 2014-04-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699843B1 (en) * 2005-06-09 2007-03-27 삼성전자주식회사 MOS Field Effect Transistor Having Trench Isolation Region and Method of Fabricating the same
KR101131949B1 (en) * 2009-08-03 2012-04-04 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06181318A (en) * 1992-12-11 1994-06-28 Citizen Watch Co Ltd Semiconductor non-volatile memory device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06181318A (en) * 1992-12-11 1994-06-28 Citizen Watch Co Ltd Semiconductor non-volatile memory device and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444918B1 (en) * 2001-03-14 2004-08-18 미쓰비시덴키 가부시키가이샤 Method of manufacturing semiconductor device
CN103730343A (en) * 2012-10-10 2014-04-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and manufacturing method thereof
CN103730343B (en) * 2012-10-10 2016-08-03 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor device structure and preparation method thereof

Also Published As

Publication number Publication date
KR19990050035A (en) 1999-07-05

Similar Documents

Publication Publication Date Title
KR100272527B1 (en) Semiconductor device and method for fabricating the same
KR100298874B1 (en) Method for forming transistor
JPH0831602B2 (en) Method for manufacturing MIS field effect transistor
JP3049496B2 (en) Method of manufacturing MOSFET
KR100198676B1 (en) Transistor of semiconductor device and method of manufacturing the same
KR100247694B1 (en) Method for fabricating semiconductor device
KR100249015B1 (en) Method of fabricating transistor
KR100567047B1 (en) Menufacturing method for mos transistor
KR100305205B1 (en) Method for manufacturing semiconductor device
KR100261171B1 (en) Method for fabricating transistor
KR100236264B1 (en) Method of manufacturing semiconductor device
KR100422823B1 (en) Method for fabricating mos transistor
KR100226496B1 (en) Method of manufacturing semiconductor device
KR100231479B1 (en) Method of fabricating field transistor
KR100689677B1 (en) A semiconductor device and method for manufacturing the same
KR100784063B1 (en) structure of a thin film transistor and method for manufacturing the same
KR100231131B1 (en) Manufacturing method of semiconductor
KR100362933B1 (en) Metal oxide semiconductor field effect transistor and method for manufacturing the same
KR100280798B1 (en) Transistor manufacturing method of semiconductor device
KR0140811B1 (en) Fabrication method of transistor
KR20000032450A (en) Method for manufacturing semiconductor device
KR20000043826A (en) Fabrication method of semiconductor device
KR20020010965A (en) Method of manufacturing semiconductor device
JPH0897415A (en) Manufacture of semiconductor device
KR20020049934A (en) Method of manufacturing a transistor in a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee