KR100231131B1 - Manufacturing method of semiconductor - Google Patents

Manufacturing method of semiconductor Download PDF

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KR100231131B1
KR100231131B1 KR1019970038970A KR19970038970A KR100231131B1 KR 100231131 B1 KR100231131 B1 KR 100231131B1 KR 1019970038970 A KR1019970038970 A KR 1019970038970A KR 19970038970 A KR19970038970 A KR 19970038970A KR 100231131 B1 KR100231131 B1 KR 100231131B1
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forming
mask
semiconductor substrate
gate
mesa structure
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KR1019970038970A
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Korean (ko)
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KR19990016434A (en
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이동근
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로서 제1도전형의 반도체기판상의 소정 부분에 제1마스크를 형성하는 공정과, 상기 반도체기판의 노출된 부분을 식각하여 상기 제1마스크 하부에 경사면을 갖는 메사 구조를 형성하는 공정과, 상기 제1마스크를 제거하고 상기 메사 구조 상부 표면에 게이트절연막을 개재시켜 게이트를 형성하는 공정과, 상기 반도체기판 상에 상기 메사 구조의 경사면을 포함하여 게이트를 덮는 제2마스크를 형성하고 상기 반도체기판의 노출된 부분에 제2도전형의 고농도영역을 형성하는 공정과, 상기 제2마스크를 제거하고 상기 게이트를 마스크로 사용하여 상기 고농도영역이 형성되지 않은 상기 메사 구조의 경사면에 제2도전형의 저농도영역을 형성하는 공정을 구비한다. 따라서, 측벽을 형성하지 않으므로 제조 공정 수가 감소될 뿐만 아니라 측벽 형성시 발생되는 식각부산물에 의한 소자의 신뢰성이 저하되는 것을 감소시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a first mask on a predetermined portion of a first conductive semiconductor substrate; Forming a mesa structure; removing the first mask; and forming a gate by interposing a gate insulating film on an upper surface of the mesa structure; and forming an inclined surface of the mesa structure on the semiconductor substrate to cover the gate. Forming a second mask and forming a high concentration region of a second conductivity type in an exposed portion of the semiconductor substrate; and removing the second mask and using the gate as a mask, the mesa structure in which the high concentration region is not formed. And forming a low concentration region of the second conductivity type on the inclined surface of the substrate. Therefore, since the sidewalls are not formed, the number of manufacturing processes may be reduced, and the deterioration of the reliability of the device due to the etching by-products generated during the formation of the sidewalls may be reduced.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히 측벽을 형성하지 않고 LDD(Lightly Doped Drain)를 갖는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a lightly doped drain (LDD) without forming sidewalls.

반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져 내부의 전계 강도가 증가된다. 이러한 전계 강도의 증가는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜 게이트산화막으로 주입시키는 핫-캐리어 효과(hot-carrier effect)를 일으킨다. 게이트산화막에 주입된 캐리어는 반도체기판과 게이트산화막의 계면에 준위를 생성시켜 드레쉬홀드전압(thres-hold voltage : VTH)을 변화시키거나 상호 컨덕턴스를 저하시켜 소자 특성을 저하시킨다. 그러므로, LDD 등과 같이 드레인 구조를 변화시켜 핫-캐리어 효과에 의한 소자 특성의 저하를 감소시켰다.As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V TH ) or decreasing mutual conductance, thereby degrading device characteristics. Therefore, the drain structure is changed, such as LDD, to reduce the deterioration of device characteristics due to the hot-carrier effect.

제1a도 내지 제1c도는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

제1a도를 참조하면, P형의 반도체기판(11) 표면의 소정 부분에 LOCOS(Local Oxidation of Silicon) 등의 통상적인 선택산화방법에 의해 필드산화막(13)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 1A, a field oxide film 13 is formed on a predetermined portion of a surface of a P-type semiconductor substrate 11 by a conventional selective oxidation method such as LOCOS (Local Oxidation of Silicon) to form an active region and a field of a device. Define the area.

제1b도를 참조하면, 반도체기판(11)의 표면을 열산화하여 게이트산화막(15)을 형성한다. 그리고, 필드산화막(13) 및 게이트산화막(15)의 상부에 다결정실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하고 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트(17)를 한정한다. 게이트(17)을 마스크로 사용하여 반도체기판(11)의 노출된 부분에 N형의 불순물을 저농도로 이온 주입하여 LDD 구조를 형성하기 위한 저농도영역(19)을 형성한다.Referring to FIG. 1B, a gate oxide film 15 is formed by thermally oxidizing the surface of the semiconductor substrate 11. Then, polycrystalline silicon is deposited on the field oxide film 13 and the gate oxide film 15 by chemical vapor deposition (hereinafter, referred to as CVD), and patterned by photolithography to form the gate 17. ). N-type impurities are implanted at low concentration into the exposed portion of the semiconductor substrate 11 using the gate 17 as a mask to form a low concentration region 19 for forming an LDD structure.

제1c도를 참조하면, 게이트(17)의 측면에 측벽(21)을 형성한다. 상기에서 측벽(21)은 산화실리콘을 증착한 후 게이트(17) 및 반도체기판(11)이 노출되도록 에치백(etchback)하므로써 형성된다. 그리고, 게이트(17)와 측벽(21)을 마스크로 사용하여 반도체기판(11)에 N형의 불순물을 고농도로 이온 주입하여 소오스 및 드레인 영역으로 이용되는 고농도영역(23)을 형성한다. 이 때, 고농도영역(23)은 저농도영역(19)과 중첩되게 형성된다.Referring to FIG. 1C, the sidewall 21 is formed on the side of the gate 17. In this case, the sidewall 21 is formed by etching back the silicon oxide and the gate 17 and the semiconductor substrate 11 after deposition. N-type impurities are implanted at high concentration into the semiconductor substrate 11 using the gate 17 and the sidewall 21 as a mask to form a high concentration region 23 used as a source and a drain region. At this time, the high concentration region 23 is formed to overlap with the low concentration region 19.

그러나, 상술한 바와 같이 종래 기술은 LDD 구조를 형성하기 위해 게이트의 측면에 측벽을 형성하여야 하므로 제조 공정이 복잡할 뿐만 아니라 측벽 형성시 발생되는 식각부산물에 의해 소자의 신뢰성이 저하되는 문제점이 있었다.However, as described above, since the sidewalls are formed on the side surfaces of the gates to form the LDD structure, the manufacturing process is complicated and the reliability of the device is degraded by the etching by-products generated during sidewall formation.

따라서, 본 발명의 목적은 제조 공정 수와 식각부산물에 의한 소자의 신뢰성이 저하되는 것을 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the deterioration of the reliability of the device due to the number of manufacturing steps and etching byproducts.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 제1도전형의 반도체기판 상의 소정 부분에 제1마스크를 형성하는 공정과, 상기 반도체기판의 노출된 부분을 등방성으로 식각하여 상기 제1 마스크 하부에 경사면을 갖는 메사 구조를 형성하는 공정과, 상기 제1마스크를 제거하고 상기 반도체기판의 상기 메사 구조 상부 표면에 게이트절연막을 개재시켜 게이트를 형성하는 공정과, 상기 반도체기판 상에 상기 메사 구조의 경사면을 포함하여 상기 게이트를 덮는 제2마스크를 형성하고 상기 반도체기판의 노출된 부분에 제2도전형의 고농도영역을 형성하는 공정과, 상기 제2마스크를 제거하고 상기 게이트를 마스크로 사용하여 상기 고농도영역이 형성되지 않은 상기 메사 구조의 경사면에 제2도전형의 저농도영역을 형성하는 공정을 구비한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming a first mask on a predetermined portion of a first conductive semiconductor substrate, and isotropically etching the exposed portion of the semiconductor substrate. 1) forming a mesa structure having an inclined surface under the mask; forming a gate by removing the first mask and interposing a gate insulating film on an upper surface of the mesa structure of the semiconductor substrate; Forming a second mask covering the gate including an inclined surface of the mesa structure and forming a high concentration region of a second conductivity type on an exposed portion of the semiconductor substrate; removing the second mask and using the gate as a mask. Forming a low concentration region of the second conductivity type on the inclined surface of the mesa structure in which the high concentration region is not formed. Equipped.

제1a도 내지 1c도는 종래 기술에 따른 반도체장치의 제조 공정도.1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

제2a도 내지 2d도는 본 발명에 따른 반도체장치의 제조 공정도.2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2a도 내지 2d도는 본 발명에 따른 반도체장치의 제조 공정도이다.2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

제2a도를 참조하면, (100)면을 갖는 P형의 반도체기판(31) 상에 제1감광막(33)을 도포한 후 반도체기판(31) 상의 소정 부분에만 잔류하도록 노광 및 현상하여 패터닝한다.Referring to FIG. 2A, the first photosensitive film 33 is coated on the P-type semiconductor substrate 31 having the (100) plane, and then exposed and developed so as to remain only in a predetermined portion on the semiconductor substrate 31. .

패터닝된 제1감광막(33)을 마스크로 사용하여 반도체기판(31)의 노출된 부분을 KOH 등의 식각 용액을 식각한다. 이 때, 반도체기판(31)은 등방성식각되므로 패턴닝된 제1감광막(33)의 하부의 일부도 식각되어 식각되지 않은 부분에 메사 구조(35)가 형성된다. 상기에서 메사 구조(35)는 (111)면의 경사면을 갖는다. 이는 (100)면을 갖는 반도체기판(31)을 등방성식각할 때 제1감광막(33)의 하부 소정 부분에서 (111)면이 노출되는데, 이 (111)면은 단위 면적당 원자의 밀도가 조밀하여 다른 부분의 노출면 보다 식각 속도가 늦어지므로 메사 구조(35)의 경사면은 (111)면을 갖게 된다.The patterned first photoresist layer 33 is used as a mask to etch an exposed solution of the KOH or the like on the exposed portion of the semiconductor substrate 31. At this time, since the semiconductor substrate 31 is isotropically etched, a portion of the lower portion of the patterned first photoresist layer 33 is also etched to form the mesa structure 35 in the unetched portion. The mesa structure 35 has an inclined surface of the (111) plane in the above. When the semiconductor substrate 31 having the (100) plane is isotropically etched, the (111) plane is exposed at a lower predetermined portion of the first photoresist layer 33, and the (111) plane has a dense density of atoms per unit area. Since the etching speed is slower than that of the other portions of the exposed surface, the inclined surface of the mesa structure 35 has a (111) plane.

제2b도를 참조하면, 패터닝된 제1감광막(33)을 제거하여 메사 구조(35)의 상부 표면을 노출시킨다. 그리고, 반도체기판(31)의 소정 부분에 LOCOS(Local Oxidation of Silicon) 또는 트렌치 소자분리 등의 방법으로 필드산화막(37)을 형성하여 소자의 활성영역(A) 및 필드영역(F)을 한정한다. 이 때, 활성영역(A)은 메사 구조(35)가 중심에 위치되도록 한정된다.Referring to FIG. 2B, the patterned first photoresist layer 33 is removed to expose the upper surface of the mesa structure 35. A field oxide film 37 is formed on a predetermined portion of the semiconductor substrate 31 by LOCOS (local oxide of silicon) or trench isolation to define the active region A and the field region F of the device. . At this time, the active region A is defined such that the mesa structure 35 is located at the center.

반도체기판(31)의 활성영역(A)상에 열산화 방법에 의해 산화막을 형성하고, 이 산화막 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착한다. 그리고, 불순물이 도핑된 다결정실리콘과 산화막을 메사 구조(35)의 상부 표면에만 잔류하도록 포토리쏘그래피 방법으로 순차적으로 패터닝하여 게이트절연막(39) 및 게이트(41)를 형성한다.An oxide film is formed on the active region A of the semiconductor substrate 31 by a thermal oxidation method, and polycrystalline silicon doped with impurities on the oxide film is deposited by a CVD method. Then, the polysilicon and the oxide film doped with impurities are sequentially patterned by a photolithography method so as to remain only on the upper surface of the mesa structure 35 to form the gate insulating film 39 and the gate 41.

제2c도를 참조하면, 반도체기판(31) 상에 필드산화막(37) 및 게이트(41)을 덮도록 제2감광막(43)을 도포한다. 그리고, 제2감광막(43)을 반도체기판(31)의 게이트(41) 뿐만 아니라 메사 구조(35)의 경사면을 포함하는 부분을 제외하는 부분이 노출되도록 노광 및 현상하여 패터닝한다.Referring to FIG. 2C, a second photosensitive film 43 is coated on the semiconductor substrate 31 to cover the field oxide film 37 and the gate 41. Then, the second photoresist film 43 is exposed and developed so as to expose not only the gate 41 of the semiconductor substrate 31 but also a portion including the inclined surface of the mesa structure 35.

패터닝된 제2감광막(43)을 마스크로 사용하여 반도체기판(31)의 활성영역(A)의 노출된 부분에 인(P) 또는 아세닉(As)등의 N형의 불순물을 고농도로 이온 주입하여 트랜지스터의 소오스 및 드레인 영역으로 이용되는 고농도영역(45)을 형성한다. 이때, 메사 구조(35)의 경사면은 제2감광막(43)에 의해 불순물이 주입되지 않으므로 고농도영역(45)이 형성되지 않는다.By using the patterned second photoresist layer 43 as a mask, ion implantation with high concentration of N-type impurities such as phosphorus (P) or arsenic (As) in the exposed portion of the active region A of the semiconductor substrate 31 is performed. As a result, the high concentration region 45 used as the source and drain regions of the transistor is formed. At this time, since the impurity is not injected into the inclined surface of the mesa structure 35 by the second photosensitive film 43, the high concentration region 45 is not formed.

제2d도를 참조하면, 패터닝된 제2감광막(43)을 제거하여 게이트(41)를 노출시킨다. 그리고, 게이트(41)를 마스크로 사용하여 반도체기판(31)의 활성영역(A)의 노출된 부분에 인(P) 또는 아세닉(As) 등의 N형의 불순물을 저농도로 이온 주입한다. 이때, 고농도영역(45)이 형성되지 않은 메사 구조(35)의 경사면 하부에는 저농도로 주입된 N형의 불순물에 의해 LDD 구조를 형성하기 위한 저농도영역(47)이 형성된다.Referring to FIG. 2D, the patterned second photoresist layer 43 is removed to expose the gate 41. N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted at low concentration in the exposed portion of the active region A of the semiconductor substrate 31 using the gate 41 as a mask. At this time, a low concentration region 47 is formed below the inclined surface of the mesa structure 35 in which the high concentration region 45 is not formed by the N-type impurities injected at low concentration.

상술한 바와 같이 본 발명에 따른 반도체장치의 제조방법은 반도체기판을 활성 영역의 소정 부분이 메사 구조를 이루도록 나머지 부분을 식각하여 활성영역의 메사 구조를 제외한 나머지 부분에 불순물을 고농도로 이온 주입하여 트랜지스터의 소오스 및 드레인 영역으로 이용되는 고농도영역을 형성한 후, 이 고농도영역이 형성되지 않은 메사 구조의 경사면 하부에 불순물을 저농도로 주입하여 LDD 구조를 형성하기 위한 저농도영역을 형성하므로써 게이트의 측면에 측벽을 형성하지 않고 LDD 구조를 형성한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a transistor is etched from a semiconductor substrate such that a predetermined portion of an active region forms a mesa structure, and ion is implanted at a high concentration into the remaining portions except for the mesa structure of the active region. After forming a high concentration region to be used as a source and drain region of the sidewall, sidewalls of the sidewalls of the gate are formed by forming a low concentration region for forming an LDD structure by injecting impurities at a low concentration under the mesa structure where the high concentration region is not formed. An LDD structure is formed without forming a film.

따라서, 본 발명은 측벽을 형성하지 않으므로 제조 공정 수가 감소될 뿐만 아니라 측벽 형성시 발생되는 식각부산물에 의한 소자의 신뢰성이 저하되는 것을 감소시킬 수 있는 잇점이 있다.Therefore, since the present invention does not form sidewalls, the number of manufacturing processes is reduced, and the reliability of the device due to etching by-products generated during sidewall formation may be reduced.

Claims (5)

제1도전형의 반도체기판 상의 소정 부분에 제1마스크를 형성하는 공정과, 상기 반도체기판의 노출된 부분을 등방성으로 식각하여 상기 제1마스크 하부에 경사면을 갖는 메사 구조를 형성하는 공정과, 상기 제1마스크를 제거하고 상기 반도체기판의 상기 메사 상부 표면에 게이트절연막을 개재시켜 게이트를 형성하는 공정과, 상기 반도체기판 상에 상기 메사 구조의 경사면을 포함하여 상기 게이트를 덮는 제2마스크를 형성하고 상기 반도체기판의 노출된 부분에 제2도전형의 고농도영역을 형성하는 공정과, 상기 제2마스크를 제거하고 상기 게이트를 마스크로 사용하여 상기 고농도영역이 형성되지 않은 상기 메사 구조의 경사면에 제2도전형의 저농도영역을 형성하는 공정을 구비하는 반도체장치의 제조방법.Forming a first mask on a predetermined portion of the first conductive semiconductor substrate, isotropically etching the exposed portion of the semiconductor substrate to form a mesa structure having an inclined surface under the first mask, and Removing a first mask and forming a gate by interposing a gate insulating film on the upper surface of the mesa of the semiconductor substrate, and forming a second mask on the semiconductor substrate including the inclined surface of the mesa structure to cover the gate; Forming a high concentration region of a second conductivity type on an exposed portion of the semiconductor substrate, and removing the second mask and using the gate as a mask to a second inclined surface of the mesa structure in which the high concentration region is not formed. A method of manufacturing a semiconductor device, comprising the step of forming a conductive low concentration region. 제1항에 있어서, 상기 제1 및 제2마스크를 감광막으로 형성하는 반도체장치의 제조방법.The method of claim 1, wherein the first and second masks are formed of a photosensitive film. 제1항에 있어서, 상기 반도체기판의 노출된 부분을 KOH 용액으로 식각하여 메사 구조를 형성하는 반도체장치의 제조방법.The method of claim 1, wherein the exposed portion of the semiconductor substrate is etched with a KOH solution to form a mesa structure. 제1항에 있어서, 상기 제1마스크 제거 후 상기 반도체기판의 소정 부분에 소자의 활성영역 및 필드영역을 한정하는 필드산화막을 형성하는 공정을 더 구비하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a field oxide film defining an active region and a field region of a device in a predetermined portion of the semiconductor substrate after removing the first mask. 제4항에 있어서, 상기 필드산화막을 상기 메사 구조가 상기 소자의 활성영역의 중심에 위치되도록 형성하는 반도체장치의 제조방법.The method of claim 4, wherein the field oxide film is formed such that the mesa structure is located at the center of an active region of the device.
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