KR100247694B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100247694B1
KR100247694B1 KR1019970059933A KR19970059933A KR100247694B1 KR 100247694 B1 KR100247694 B1 KR 100247694B1 KR 1019970059933 A KR1019970059933 A KR 1019970059933A KR 19970059933 A KR19970059933 A KR 19970059933A KR 100247694 B1 KR100247694 B1 KR 100247694B1
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insulating film
forming
gate
sidewalls
conductivity type
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KR1019970059933A
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Korean (ko)
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KR19990039738A (en
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김진호
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

본 발명에 따른 반도체소자의 제조 방법은 제 1 도전형을 갖는 반도체기판에 필드산화막을 형성하여 활성영역을 한정하는 공정과, 상기 활성영역 상에 게이트산화막, 다결정실리콘, 그리고 캡절연막을 위한 산화물을 순차적으로 형성하고 패터닝하여 게이트를 형성하는 공정과, 상기 캡절연막을 마스크로 사용하여 상기 반도체기판과 다른 제 2 도전형의 불순물을 저농도로 이온주입하여 제 1 불순물영역을 형성하는 공정과, 상기 게이트의 측면에 측벽을 형성하고 상기 캡절연막 및 측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 이온주입하여 제 2 불순물영역을 형성하는 공정과, 상기 게이트의 측면의 측벽을 습식식각하여 제거하는 공정과, 상기 게이트를 덮도록 절연물질을 증착하여 제 1 절연막을 형성하는 공정과, 상기 제 1 절연막을 덮도록 두꺼운 제 2 절연막을 형성하는 공정과, 상기 제 2 절연막을 패터닝하여 콘택홀을 형성하는 공정을 구비한다. 따라서, 본 발명에 따라 형성된 반도체소자는 게이트의 측벽을 제거하므로서 상대적으로 게이트간의 종횡비가 커져 이후에 형성한 층간절연막내에 보이드의 발생이 억제된다. 때문에 상기 층간절연막에 형성할 콘택홀의 이방성식각이 용이한 잇점이 있다.A method of manufacturing a semiconductor device according to the present invention includes forming a field oxide film on a semiconductor substrate having a first conductivity type to define an active region, and forming an oxide for a gate oxide film, a polycrystalline silicon, and a cap insulating film on the active region. Forming a gate by sequentially forming and patterning the gate; forming a first impurity region by implanting impurities of a second conductivity type different from the semiconductor substrate at low concentration using the cap insulating film as a mask; Forming a second impurity region by ion implanting impurities of a second conductivity type at a high concentration using sidewalls of the cap insulating film and sidewalls as a mask, and wet etching sidewalls of the sidewalls of the gate. Forming a first insulating film by depositing an insulating material to cover the gate; And forming a thick second insulating film so as to cover it, and forming a contact hole by patterning the second insulating film. Therefore, in the semiconductor device formed according to the present invention, the aspect ratio between the gates is relatively increased by eliminating the sidewalls of the gate, thereby suppressing the generation of voids in the subsequently formed interlayer insulating film. Therefore, the anisotropic etching of the contact holes to be formed in the interlayer insulating film is easy.

Description

반도체소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체소자의 제조 방법에 관한 것으로서, 특히, 저도핑 드레인 형성 후에 층간절연막의 보이드 발생을 억제하는 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that suppresses the generation of voids in an interlayer insulating film after low doping drain formation.

일반적으로 반도체소자가 고집적화 됨에 따라, 단위 소자의 크기 특히, 트랜지스터(Transistor) 소자의 크기가 미세해져서 반도체소자의 집적도를 높이고 또한 동작 속도를 빠르게 하기 위해 트랜지스터의 채널을 줄여 매우 적게 제조하고 있다. 그러나, 이 때 내부에 강전계가 형성된다. 이러한 강전계는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜서 게이트 산화막으로 주입시키는 핫 캐리어 효과(Hot-carrier effect)를 일으킨다. 그러므로, 소자의 크기가 작을 때 드레인에 강전계가 형성되는 것을 감소시키기 위해 채널 부근의 소오스와 드레인 영역에는 전계를 감소시키고, 열전자효과를 감소시키기 위하여 저농도의 도핑을 하는 저도핑 드레인(Lightly Doped Drain : LDD) 구조를 사용한다.In general, as semiconductor devices have been highly integrated, the size of unit devices, in particular, the size of transistor devices has become smaller, so that the number of transistor channels is reduced to increase the degree of integration of semiconductor devices and to increase the operation speed. However, a strong electric field is formed inside at this time. Such a strong electric field causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. Therefore, in order to reduce the formation of a strong electric field in the drain when the device size is small, a lightly doped drain having a low concentration of doping to reduce the electric field in the source and drain region near the channel, and to reduce the thermoelectric effect. LDD) structure is used.

도 1a 내지 도 1d는 종래 기술에 따른 반도체소자의 제조 방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.

종래에는 도 1a에 나타낸 바와 같이 제 1 도전형을 갖는 반도체기판(11), 예를 들어 P형의 반도체기판(11)에 STI(Shallow Trench Isolation : 이하, STI라 칭함) 방법 등과 같은 통상적인 소자 격리 방법으로 필드산화막(13)을 형성하여 활성영역을 한정한다. 그리고, 상기 P형의 반도체기판(11) 상에 열산화 방법으로 게이트산화막(15)을 형성하고, 상기 게이트산화막(15) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 불순물이 도핑된 다결정실리콘(Polysilicon)을 증착하여 다결정실리콘층을 형성하고, 상기 다결정실리콘층 상에 산화실리콘 또는 질화실리콘을 CVD 방법으로 증착하여 캡절연막(19)을 형성한다. 그런 후에 포토리쏘그래피(Photolithograpy)의 방법으로 상기 캡절연막(19), 다결정실리콘층 및 게이트절연막(15)을 순차적으로 이방성식각하여 게이트(17)를 한정한다.1A, a conventional device such as an STI (Shallow Trench Isolation) method or the like is applied to a semiconductor substrate 11 having a first conductivity type, for example, a P-type semiconductor substrate 11, as shown in FIG. The field oxide film 13 is formed by the isolation method to define the active region. A gate oxide film 15 is formed on the P-type semiconductor substrate 11 by thermal oxidation, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the gate oxide film 15. Impurity doped polysilicon is deposited to form a polysilicon layer, and silicon oxide or silicon nitride is deposited on the polysilicon layer by CVD to form a cap insulating film 19. Thereafter, the cap insulation layer 19, the polysilicon layer, and the gate insulation layer 15 are sequentially anisotropically etched by photolithography to define the gate 17.

그리고, 도 1b와 같이 상기 게이트(17)가 형성된 P형의 반도체기판(11)에 상기 캡절연막(19)을 마스크로 사용하여 상기 P형의 반도체기판(11)과 도전형이 다른 N형의 불순물, 예를 들면 아세닉(As), 또는 인(P)을 저농도로 이온주입하여 저농도의 제 1 불순물영역(21)을 형성한다.As shown in FIG. 1B, the cap insulating film 19 is used as a mask for the P-type semiconductor substrate 11 having the gate 17 formed thereon, and the N-type different from the P-type semiconductor substrate 11 is formed. An impurity, for example, Asonic or Phosphorus, is implanted at low concentration to form the first impurity region 21 at low concentration.

그런 후에 도 1c에 나타낸 바와 같이 저농도의 제 1 불순물영역(21)이 형성된 반도체기판(11) 상에 상기 게이트(17)를 덮도록 질화실리콘을 CVD 방법으로 증착하여 제 1 절연막(23)을 형성한다. 상기 제 1 절연막(23)과 식각선택비가 다른, 예를 들면 산화실리콘을 CVD 방법으로 증착하여 두껍게 제 2 절연막을 형성한 후, 상기 제 2 절연막을 에치백(Etch back)하여 상기 게이트(17)의 측면에 측벽(Side Wall : 25)을 형성한다.Thereafter, as shown in FIG. 1C, silicon nitride is deposited on the semiconductor substrate 11 having the low concentration of the first impurity region 21 by the CVD method to form the first insulating film 23. do. For example, silicon oxide having a different etching selectivity from the first insulating layer 23 is deposited by CVD to form a second insulating layer, and then the second insulating layer is etched back to the gate 17. Side wall (Side Wall: 25) is formed on the side.

이후에, 도 1d에 나타낸 바와 같이 상기 캡절연막(19) 상의 제 1 절연막(23) 및 측벽(25)을 마스크로 사용하여 상기 반도체기판(11)과 다른 도전형의 불순물, 즉 저농도의 제 1 불순물영역(21)을 형성하기 위해 주입한 불순물을 고농도로 이온주입하여 소오스/드레인으로 사용되는 고농도의 제 2 불순물영역(27)을 형성한다.Subsequently, as shown in FIG. 1D, the first insulating layer 23 and the sidewall 25 on the cap insulating layer 19 are used as masks to form impurities of a different conductivity type from the semiconductor substrate 11, that is, a first concentration having a low concentration. Impurities implanted to form the impurity region 21 are ion implanted at a high concentration to form a high concentration of the second impurity region 27 used as a source / drain.

다음 공정으로 도시하지 않았지만 상기 게이트를 덮도록 두꺼운 층간절연막을 형성하고 상기 층간절연막을 포토리쏘그래피(Photolithograpy)의 방법으로 패터닝하여 자기 정렬을 위한 콘택홀(Self Align Contact Hole)을 형성한다.Although not shown in the following process, a thick interlayer insulating film is formed to cover the gate, and the interlayer insulating film is patterned by a photolithograpy method to form a self alignment contact hole.

상술한 바와 같이 종래의 방법으로 반도체소자를 제조하면 상기 측벽으로 인한 게이트간의 종횡비(Aspect ratio)가 커지므로 이후 공정을 진행하기 위해 층간절연막을 형성할 때, 상기 층간절연막의 내부에 보이드(Void)가 발생하게 된다. 상기 층간절연막에 형성된 보이드는 추후에 자기 정렬을 위한 콘택홀을 형성하기 위해 이방성식각할 때 측면의 식각을 방지하기 위해 발생하는 폴리머(Polymer)가 식각진행 중에 보이드가 노출되면 보이드의 하부면에 적층되어 상기 보이드 이후의 식각이 진행되지 않는 문제가 발생한다.As described above, when the semiconductor device is manufactured by the conventional method, the aspect ratio between the gates due to the sidewalls increases, so that voids are formed inside the interlayer insulating film when the interlayer insulating film is formed for the subsequent process. Will occur. The voids formed on the interlayer insulating layer are laminated on the lower surface of the voids when a void is exposed during the etching process of a polymer generated to prevent side etching during anisotropic etching to form contact holes for self alignment later. There is a problem that the etching after the void does not proceed.

따라서, 본 발명의 목적은 저도핑 드레인 구조를 형성한 이후 공정으로 층간절연막을 형성할 때 보이드가 발생하지 않는 반도체소자의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which no voids are generated when the interlayer insulating film is formed by a process after forming the low doping drain structure.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조 방법은 제 1 도전형을 갖는 반도체기판에 필드산화막을 형성하여 활성영역을 한정하는 공정과, 상기 활성영역 상에 게이트산화막, 다결정실리콘, 그리고 캡절연막을 위한 산화물을 순차적으로 형성하고 패터닝하여 게이트를 형성하는 공정과, 상기 캡절연막을 마스크로 사용하여 상기 반도체기판과 다른 제 2 도전형의 불순물을 저농도로 이온주입하여 제 1 불순물영역을 형성하는 공정과, 상기 게이트의 측면에 측벽을 형성하고 상기 캡절연막 및 측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 이온주입하여 제 2 불순물영역을 형성하는 공정과, 상기 게이트의 측면의 측벽을 습식식각하여 제거하는 공정과, 상기 게이트를 덮도록 절연물질을 증착하여 제 1 절연막을 형성하는 공정과, 상기 제 1 절연막을 덮도록 두꺼운 제 2 절연막을 형성하는 공정과, 상기 제 2 절연막을 패터닝하여 콘택홀을 형성하는 공정을 구비한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a field oxide film on a semiconductor substrate having a first conductivity type to define an active region, a gate oxide film, polycrystalline silicon, and Forming a gate by sequentially forming and patterning an oxide for a cap insulating film; and forming a first impurity region by implanting impurities of a second conductivity type different from the semiconductor substrate at low concentration using the cap insulating film as a mask. Forming a second impurity region by forming a sidewall on the side of the gate and ion implanting impurities of a second conductivity type at a high concentration using the cap insulating film and the sidewall as a mask; Wet etching the sidewalls; and depositing an insulating material to cover the gate to form a first insulating layer. And forming a thick second insulating film so as to cover the first insulating film, and forming a contact hole by patterning the second insulating film.

도 1a 내지 도 1d는 종래 기술에 따른 반도체소자의 제조 방법을 도시하는 공정도.1A to 1D are process drawings showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 제조 방법을 도시하는 공정도.2A to 2D are flowcharts illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 간단한 설명〉<Brief description of symbols for the main parts of the drawings>

31 : 반도체기판 33 : 필드산화막31: semiconductor substrate 33: field oxide film

37 : 게이트 41 : 제 1 불순물영역37 gate 41 first impurity region

45 : 제 2 불순물영역 47 : 절연막45: second impurity region 47: insulating film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 제조 방법을 도시하는 공정도이다.2A to 2D are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

본 방법은 도 2a에 나타낸 바와 같이 제 1 도전형을 갖는 반도체기판(31), 예를 들어 P형의 반도체기판(31)에 STI 방법 등과 같은 통상적인 소자 격리 방법으로 필드산화막(33)을 형성하여 활성영역을 한정한다. 그리고, 상기 P형의 반도체기판(31) 상에 열산화 방법으로 게이트산화막(35)을 형성하고, 상기 게이트산화막(35) 상에 CVD 방법으로 불순물이 도핑된 다결정실리콘을 증착하여 다결정실리콘층을 형성하고, 상기 다결정실리콘층 상에 산화실리콘을 CVD 방법으로 증착하여 캡절연막(39)을 형성한다. 그런 후에 포토리쏘그래피의 방법으로 상기 캡절연막(39), 다결정실리콘층 및 게이트절연막(35)을 순차적으로 이방성식각하여 게이트(37)를 한정한다.2A, a field oxide film 33 is formed on a semiconductor substrate 31 having a first conductivity type, for example, a P-type semiconductor substrate 31 by a conventional device isolation method such as an STI method. To define the active area. A gate oxide film 35 is formed on the P-type semiconductor substrate 31 by thermal oxidation, and polycrystalline silicon doped with impurities is deposited on the gate oxide film 35 by CVD. And a silicon oxide is deposited on the polysilicon layer by CVD to form a cap insulating film 39. Thereafter, the cap insulation layer 39, the polysilicon layer, and the gate insulation layer 35 are sequentially anisotropically etched by photolithography to define the gate 37.

그리고, 도 2b와 같이 상기 게이트(37)가 형성된 P형의 반도체기판(31)에 상기 캡절연막(39)를 마스크로 사용하여 상기 P형의 반도체기판(31)과 도전형이 다른 제 2 도전형 불순물, 예를 들면 N형의 아세닉(As) 또는 인(P)을 저농도로 이온주입하여 저농도의 제 1 불순물영역(41)을 형성한다.As shown in FIG. 2B, the cap insulation film 39 is used as a mask for the P-type semiconductor substrate 31 on which the gate 37 is formed, and the second conductivity is different from that of the P-type semiconductor substrate 31. A low impurity first impurity region 41 is formed by ion implantation at low concentrations of an impurity, for example, an N-type arsenic (As) or phosphorus (P).

그런 후에, 도 2c와 같이 상기 필드산화막(33)과 식각선택비가 다른 물질, 예를 들면 질화실리콘 등을 CVD 방법으로 약 800∼1000Å정도로 두껍게 증착하였다가 에치백하여 상기 게이트(37)의 측면에 질화물 측벽(43)을 형성한다. 상기 캡절연막(39) 및 측벽(43)을 마스크로 사용하여 상기 P형의 반도체기판(31)과 다른 도전형, 즉 저농도의 제 1 불순물영역(41)을 형성하기 위해 주입한 불순물을 고농도로 이온주입하여 소오스/드레인 영역으로 사용되는 고농도의 제 2 불순물영역(45)을 형성한다.Subsequently, as shown in FIG. 2C, a material having an etch selectivity different from that of the field oxide film 33, for example, silicon nitride or the like, is deposited to a thickness of about 800 to 1000 Å by CVD and then etched back to the side of the gate 37. The nitride sidewall 43 is formed. By using the cap insulating film 39 and the sidewall 43 as a mask, impurities implanted to form a first impurity region 41 having a different conductivity type from that of the P-type semiconductor substrate 31, that is, a low concentration, are highly concentrated. Ion implantation forms a high concentration second impurity region 45 used as a source / drain region.

이후에, 도 2d에 나타낸 바와 같이 고농도의 제 2 불순물영역(45)을 형성하기 위한 마스크로 사용된 질화물 습식각하여 게이트(37)의 측면에 형성된 측벽(43)을 제거한다. 상기에서 측벽(43)은 질화물로 되어 있고, 상기 필드산화막(33)이나 캡절연막(39)은 산화물로 형성되어 있으므로 상기 필드산화막(33)이나 캡절연막(39)은 식각 되지 않는다. 그리고, 상기 측벽(43)이 제거된 게이트(37)를 덮도록 질화물을 증착하여 약 400∼600Å 정도의 절연막(47)을 형성한다. 상기에서 절연막(47)은 필드산화막(33) 및 캡절연막(39)을 보호하고, 절연을 위해 형성한다.Thereafter, as shown in FIG. 2D, the sidewall 43 formed on the side of the gate 37 is removed by wet etching the nitride used as a mask for forming the second impurity region 45 having a high concentration. Since the side wall 43 is made of nitride, and the field oxide film 33 and the cap insulating film 39 are formed of an oxide, the field oxide film 33 and the cap insulating film 39 are not etched. Then, nitride is deposited to cover the gate 37 from which the sidewall 43 is removed to form an insulating film 47 of about 400 to 600 Å. In this case, the insulating film 47 protects the field oxide film 33 and the cap insulating film 39 and is formed for insulation.

그런 후에 도시하지 않았지만 상기 절연막(47) 상에 층간절연막을 형성하고, 상기 층간절연막을 포토리쏘그래피의 방법으로 패터닝하여 자기 정렬을 위한 콘택홀을 형성한다.Thereafter, although not shown, an interlayer insulating film is formed on the insulating film 47, and the interlayer insulating film is patterned by photolithography to form contact holes for self alignment.

상술한 바와 같은 방법으로 저농도 드레인을 형성하면 상기 측벽을 제거함으로 인해 게이트간의 종횡비가 상대적으로 커지므로 이후 공정으로 층간절연막을 형성할 때, 상기 층간절연막에 보이드의 생성을 억제하게 된다.When the low concentration drain is formed in the above-described manner, the aspect ratio between the gates is relatively increased by removing the sidewalls, thereby suppressing generation of voids in the interlayer insulating film when the interlayer insulating film is formed in a subsequent process.

따라서, 본 발명에 따라 형성된 반도체소자는 게이트의 측벽을 제거하므로서 상대적으로 게이트간의 종횡비가 커져 이후에 형성한 층간절연막내에 보이드의 발생이 억제된다. 때문에 상기 층간절연막에 형성할 콘택홀의 이방성식각이 용이한 잇점이 있다.Therefore, in the semiconductor device formed according to the present invention, the aspect ratio between the gates is relatively increased by eliminating the sidewalls of the gate, thereby suppressing the generation of voids in the subsequently formed interlayer insulating film. Therefore, the anisotropic etching of the contact holes to be formed in the interlayer insulating film is easy.

Claims (2)

제 1 도전형을 갖는 반도체기판에 필드산화막을 형성하여 활성영역을 한정하는 공정과,Forming a field oxide film on a semiconductor substrate having a first conductivity type to define an active region; 상기 활성영역 상에 게이트산화막, 다결정실리콘, 그리고 캡절연막을 위한 산화물을 순차적으로 형성하고 패터닝하여 게이트를 형성하는 공정과,Forming a gate by sequentially forming and patterning an oxide for a gate oxide film, polysilicon, and a cap insulating film on the active region; 상기 캡절연막을 마스크로 사용하여 상기 반도체기판과 다른 제 2 도전형의 불순물을 저농도로 이온주입하여 제 1 불순물영역을 형성하는 공정과,Forming a first impurity region by implanting impurities of a second conductivity type different from the semiconductor substrate at low concentration using the cap insulating film as a mask; 상기 게이트의 측면에 측벽을 형성하고 상기 캡절연막 및 측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 이온주입하여 제 2 불순물영역을 형성하는 공정과,Forming a second impurity region by forming a sidewall on the side of the gate and ion implanting impurities of a second conductivity type at a high concentration using the cap insulating film and the sidewall as a mask; 상기 게이트의 측면의 측벽을 습식식각하여 제거하는 공정과,Wet-etching and removing sidewalls of sidewalls of the gate; 상기 게이트를 덮도록 절연물질을 증착하여 제 1 절연막을 형성하는 공정과,Depositing an insulating material to cover the gate to form a first insulating film; 상기 제 1 절연막을 덮도록 두꺼운 제 2 절연막을 형성하는 공정과,Forming a thick second insulating film to cover the first insulating film; 상기 제 2 절연막을 패터닝하여 콘택홀을 형성하는 공정을 구비하는 반도체소자의 제조 방법.And forming a contact hole by patterning the second insulating film. 청구항 1에 있어서 상기 측벽은 질화물로 형성하는 반도체소자의 제조 방법.The method of claim 1, wherein the sidewall is formed of nitride.
KR1019970059933A 1997-11-14 1997-11-14 Method for fabricating semiconductor device KR100247694B1 (en)

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