KR100900152B1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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KR100900152B1
KR100900152B1 KR1020020077700A KR20020077700A KR100900152B1 KR 100900152 B1 KR100900152 B1 KR 100900152B1 KR 1020020077700 A KR1020020077700 A KR 1020020077700A KR 20020077700 A KR20020077700 A KR 20020077700A KR 100900152 B1 KR100900152 B1 KR 100900152B1
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diffusion layer
gate electrode
semiconductor device
manufacturing
forming
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KR20040050115A (en
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김남식
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매그나칩 반도체 유한회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 게이트 전극을 형성한 후 소오스 및 드레인 확산층을 3중 층 구조로 형성하는 반도체 소자의 제조방법을 제공함으로써 단채널 효과를 감소시키면서 접합누설전류특성 및 게이트 전극 도핑효율특성을 동시에 확보할 수 있다. 더 나아가, 본 발명은 반도체 소자의 고집적화 및 신뢰성을 향상시킬 수 있다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. The present invention provides a method for manufacturing a semiconductor device in which a source electrode and a drain diffusion layer are formed in a triple layer structure after forming a gate electrode. The electrode doping efficiency characteristic can be secured at the same time. Furthermore, the present invention can improve high integration and reliability of semiconductor devices.

반도체 소자, 소오스 확산층, 드레인 확산층, 희생 산화막, 단채널 효과, 접합누설전류Semiconductor element, source diffusion layer, drain diffusion layer, sacrificial oxide film, short channel effect, junction leakage current

Description

반도체 소자의 제조방법{Method for manufacturing a semiconductor device} Method for manufacturing a semiconductor device             

도 1 내지 도 9는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.
1 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명>       <Explanation of symbols for the main parts of the drawings>

12 : 반도체 기판 14 : 소자 분리막12 semiconductor substrate 14 device isolation film

16 : 게이트 전극 16a : 게이트 절연막16 gate electrode 16a gate insulating film

16b : 폴리실리콘층 20a : 얕은 확산층16b: polysilicon layer 20a: shallow diffusion layer

20b : 중간 확산층 20c : 깊은 확산층20b: intermediate diffusion layer 20c: deep diffusion layer

22 : 스페이서 22a : 산화막22 spacer 22a oxide film

22b : 질화막 24 : 희생 산화막22b: nitride film 24: sacrificial oxide film

26 : 포토레지스트막 28 : 소오스 확산층 26 photoresist film 28 source diffusion layer

30 : 드레인 확산층
30: drain diffusion layer

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 단채널 효과를 감소시키면서 접합누설전류특성 및 게이트 전극 도핑효율특성을 동시에 확보할 수 있는 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simultaneously securing a junction leakage current characteristic and a gate electrode doping efficiency characteristic while reducing the short channel effect of the semiconductor device.

반도체 소자가 고집적화되어 게이트 전극의 길이가 마이크로미터(㎛)이하로 감소됨에 따라 소자의 단채널 효과(short channel effect)의 증가가 큰 문제로 대두되고 있다. 이러한 단채널 효과는 소오스/드레인(source/drain) 확산층의 채널영역으로의 측면 확산에 의해 유효채널길이(effective channel length)가 감소되어 발생한다. 특히 단채널 효과는 채널길이가 0.20㎛ 이하로 감소됨에 따라 더욱 커지고 있다. 심한 경우 유효채널길이가 거의 없어져 소오스에서 드레인으로 직접 전류가 흐르는 펀치 스루우(punch-through) 현상이 발생하며, 이에 따라 게이트 동작 특성이 저하되고 있는 실정이다. As the semiconductor device is highly integrated and the length of the gate electrode is reduced to less than or equal to micrometer (μm), an increase in short channel effect of the device is a big problem. This short channel effect is caused by the effective channel length being reduced by the side diffusion into the channel region of the source / drain diffusion layer. In particular, the short channel effect is further increased as the channel length is reduced to 0.20 μm or less. In severe cases, the effective channel length is virtually eliminated, and a punch-through phenomenon occurs in which a current flows directly from the source to the drain, resulting in deterioration of the gate operation characteristic.

이러한 단채널 효과를 감소시키기 위해서는 확산층의 측면 확산을 최대한 억제하여 유효채널길이를 크게해야 하며, 이를 위해서는 소오스/드레인 확산층의 깊이 감소가 필수적으로 요구된다. 그러나, 상기 소오스/드레인 확산층의 깊이 감소는 고집적 소자에서 접합누설전류(junction leakage current)의 증대를 유발시킨다. 특히, 금속샐리사이드 구조를 사용하고 있는 고속도의 로직소자에서는 금속샐리사이드의 비정상적 성장이나 금속확산 등이 수반되어 더욱 심각한 문제가 되고 있다. 그리고, 확산층의 깊이를 감소시키기 위하여 이온주입 깊이를 감소시키면 게이트 전극의 도핑효율이 떨어지는 현상이 유발되므로 역시 그 한계가 있다. 따라서 단채널 효과를 감소시키면서 접합누설전류특성 및 게이트 전극 도핑효율특성을 동시에 확보할 수 있도록 소오스/드레인 확산층 및 게이트 형성방법에 대한 개선이 요구되고 있다.
In order to reduce such short channel effects, the effective channel length must be increased by suppressing side diffusion of the diffusion layer as much as possible, and for this purpose, a depth reduction of the source / drain diffusion layer is required. However, the depth reduction of the source / drain diffusion layer causes an increase in junction leakage current in the highly integrated device. In particular, in high-speed logic devices using a metal salicide structure, abnormal growth of metal salicide, metal diffusion, and the like become more serious problems. In addition, since the ion implantation depth is decreased to reduce the depth of the diffusion layer, the doping efficiency of the gate electrode is lowered. Therefore, improvements in the source / drain diffusion layer and the gate forming method are required to simultaneously secure the junction leakage current characteristics and the gate electrode doping efficiency characteristics while reducing the short channel effect.

따라서, 본 발명은 상기에서 설명한 종래기술의 문제점을 해결하기 위해 안출된 것으로, 반도체 소자의 단채널 효과를 감소시키면서 접합누설전류특성 및 게이트 전극 도핑효율특성을 동시에 확보할 수 있는 반도체 소자 및 그 제조방법을 제공하는데 그 목적이 있다.
Accordingly, the present invention has been made to solve the above-described problems of the prior art, and a semiconductor device and a fabrication thereof capable of simultaneously securing a junction leakage current characteristic and a gate electrode doping efficiency characteristic while reducing the short channel effect of the semiconductor device. The purpose is to provide a method.

본 발명의 일측면에 따르면, 반도체 기판에 소자 분리막을 형성하는 단계와, 상기 소자 분리막 사이에 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 얕은 확산층을 형성하는 단계와, 상기 게이트 전극의 양측벽에 스페이서를 형성하는 단계와, 전체 구조 상부에 희생 산화막 및 포토레지스트막을 순차적으로 증착한 후 평탄화하여 상기 게이트 전극의 상부를 노출시키는 단계와, 제1 습식식각공정을 선택적으로 실시하여 상기 포토레지스트막을 제거하는 단계와, 제2 습식식각공정을 실시하여 상기 반도체 기판을 기준으로 상기 희생 산화막의 증착부위 중 다른 부위에 비하여 상기 스페이서와 인접하게 증착된 부위가 두껍게 잔재되도록 하는 단계와, 상기 스페이서를 마스크로 이용한 이온주 입공정을 실시하여 상기 얕은 확산층보다 깊게 중간 확산층 및 깊은 확산층을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다. According to an aspect of the invention, forming a device isolation film on a semiconductor substrate, forming a gate electrode between the device isolation film, and forming a shallow diffusion layer on the semiconductor substrate exposed to both sides of the gate electrode And forming spacers on both sidewalls of the gate electrode, sequentially depositing a sacrificial oxide film and a photoresist film on the entire structure, and then planarizing and exposing an upper portion of the gate electrode, and performing a first wet etching process. Selectively removing the photoresist film, and performing a second wet etching process so that a portion deposited adjacent to the spacer remains thicker than other portions of the deposition sites of the sacrificial oxide film based on the semiconductor substrate. And an ion implantation process using the spacer as a mask. To provide a method of manufacturing a semiconductor device comprising the steps of forming an intermediate diffusion layer, and a deep diffusion layer deeper than said shallow diffusion layer.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

도 1 내지 도 9는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면들로서, 그 일례로 CMOS(Complementary Metal-Oxide-Semiconductor) 소자에서 PMOS 영역을 제외한 NMOS 영역만을 도시한 단면도들이다. 1 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. As an example, only NMOS regions excluding PMOS regions in a complementary metal-oxide-semiconductor (CMOS) device are illustrated. It is a cross-sectional view.

도 1을 참조하면, P형 반도체 기판(12)을 활성영역과 소자분리영역으로 정으하기 위해 STI(Shallow Trench Isolation) 공정을 실시하여 소자 분리막(14)을 형성한 후 NMOS 영역에는 'p-' 불순물인 보론(boron)을 주입하여 P-웰(P-Well)을 형성한다. 1, after forming the device isolation film 14 is subjected to STI (Shallow Trench Isolation) process in order to jeongeu the P-type semiconductor substrate 12 in the active region and the device isolation region NMOS region 'p -' Boron, which is an impurity, is injected to form a P-well.

도 2를 참조하면, 전체 구조 상부에 게이트 절연막(16a) 및 게이트 전극용 폴리실리콘층(16b)을 순차적으로 증착한 후 게이트 전극 패턴용 마스크를 이용한 식각공정을 실시하여 폴리실리콘층(16b) 및 게이트 산화막(16a)을 순차적으로 패터닝하여 게이트 전극(16)을 형성한다. Referring to FIG. 2, the gate insulating layer 16a and the gate electrode polysilicon layer 16b are sequentially deposited on the entire structure, followed by an etching process using a mask for the gate electrode pattern, thereby performing the polysilicon layer 16b and The gate oxide film 16a is sequentially patterned to form the gate electrode 16.                     

도 3을 참조하면, LDD(Lightly Doped Drain) 이온주입 마스크용 포토레지스트 패턴(photoresist pattern; 미도시)을 형성한 후, 상기 포토레지스트 패턴을 마스크로 이용하고, 'n-' 이온을 이용한 LDD 이온주입공정을 실시하여 P-웰에 얕은 접합영역(Shallow junction)인 얕은 확산층(20a)을 형성한다.Referring to FIG. 3, after forming a photoresist pattern (not shown) for a lightly doped drain (LDD) ion implantation mask, the photoresist pattern is used as a mask and LDD ions using 'n ' ions. The implantation process is performed to form a shallow diffusion layer 20a, which is a shallow junction, in the P-well.

도 4를 참조하면, 전체 구조 상부에 CVD(Chemical Vapor Deposition)공정을 실시하여 산화막(22a)을 증착한 후 그 상부에 질화막(22b)을 증착한다. 그런 다음, 질화막(22b)과 산화막(22a)에 대해 에치백(Etch back)과 같은 전면 식각공정을 실시하여 게이트 전극(16)의 스페이서(22)를 형성한다. 이때, 산화막(22a)은 증착하지 않을 수도 있다. Referring to FIG. 4, an oxide film 22a is deposited by performing a chemical vapor deposition (CVD) process on the entire structure, and then a nitride film 22b is deposited thereon. Then, the entire surface etching process such as etch back is performed on the nitride film 22b and the oxide film 22a to form the spacer 22 of the gate electrode 16. At this time, the oxide film 22a may not be deposited.

도 5를 참조하면, 전체 구조 상부에 LPCVD(Low Pressure CVD) 공정을 이용하여 200 내지 500Å의 두께로 희생 산화막(24)을 증착한다. LPCVD 공정의 증착조건은 LPCVD 반응기의 반응온도를 650 내지 750℃로 하고, 소스 기체로는 TEOS(Tetra Ethyl Ortho Silicate)와 산소(O2) 기체가 혼합된 혼합기체를 이용하되, 이들의 혼합비가 30:1 내지 50:1 정도가 되도록 설정한다. Referring to FIG. 5, a sacrificial oxide layer 24 is deposited to a thickness of 200 to 500 Pa by using a low pressure CVD process. The deposition conditions of the LPCVD process is the reaction temperature of the LPCVD reactor is 650 ~ 750 ℃, as a source gas using a mixed gas mixed with TEOS (Tetra Ethyl Ortho Silicate) and oxygen (O 2 ) gas, the mixing ratio of these It is set to be about 30: 1 to 50: 1.

이어서, 전체 구조 상부에 포토레지스트막(photoresist film; 26)을 코팅(coating) 방식을 이용하여 코팅한다. 이때, 포토레지스트막(26)은 도 6에서 실시되는 건식식각방식을 이용한 식공공정시 충분히 평탄화가 이루어지도록 비교적 두껍게 코팅한다. 즉, 포토레지스트막(26)은 게이트 전극(16)을 완전히 덮도록 게이트 전극(16)의 두께보다 두껍게 코팅하는 것이 바람직하다. Subsequently, a photoresist film 26 is coated on the entire structure by using a coating method. In this case, the photoresist film 26 is coated relatively thick so that the planarization process is sufficiently flattened during the process of etching using the dry etching method of FIG. 6. That is, the photoresist film 26 is preferably coated thicker than the thickness of the gate electrode 16 so as to completely cover the gate electrode 16.                     

도 6을 참조하면, 전체 구조 상부에 대하여 건식식각방식으로 식각공정을 실시하여 포토레지스트막(26)과 희생 산화막(24)을 식각한다. 이때, 상기 식각공정을 적절히 조절하여 게이트 전극(16)의 상부 표면이 노출되도록 실시하는 것이 바람직하다. Referring to FIG. 6, the photoresist layer 26 and the sacrificial oxide layer 24 are etched by performing an etching process on the entire structure by dry etching. In this case, it is preferable to appropriately adjust the etching process so that the upper surface of the gate electrode 16 is exposed.

도 7을 참조하면, 포토레지스트막(26)에 대하여 습식식각방식으로 식각공정을 실시하여 선택적으로 포토레지스트막(26)만 제거한다. 이때, 습식식각방식은 H2SO4 : H2O2가 혼합된 SPM(Sulfuric acid hydrogen Peroxide Mixture) 용액을 이용하여 실시하는 것이 바람직하다. Referring to FIG. 7, an etching process is performed on the photoresist layer 26 by wet etching to selectively remove only the photoresist layer 26. In this case, the wet etching method is preferably performed using a sulfuric acid hydrogen peroxide mixture (SPM) solution in which H 2 SO 4 : H 2 O 2 is mixed.

도 8을 참조하면, 전체 구조 상부에 대하여 습식식각공정을 실시하여 희생 산화막(24)을 등방성 식각한다. 이때, 희생 산화막(24)은 습식식각공정에 의해 일정한 비율로 식각되며, 이에 따라, 희생 산화막(24)의 부위 중 스페이서(22)의 측벽부위에 증착된 부위는 다른 부위에 비해 비교적 두껍게 잔재한다. 즉, 도 5에서 도시된 바와 같이 희생 산화막(24)은 반도체 기판(12)을 기준으로 하여 볼때 다른 부위에 비해 스페이서(22)의 측벽에 증착된 부위가 가장 두껍게 증착되게 된다. 이에 따라, 습식식각공정을 실시한 후 다른 부위에 비해 이 부위가 가장 두껍게 잔재하게 된다. Referring to FIG. 8, the sacrificial oxide layer 24 is isotropically etched by performing a wet etching process on the entire structure. At this time, the sacrificial oxide film 24 is etched at a constant rate by a wet etching process, and thus, a portion deposited on the sidewall portion of the spacer 22 of the portion of the sacrificial oxide film 24 remains relatively thicker than other portions. . That is, as shown in FIG. 5, the sacrificial oxide film 24 has the thickest deposited portion on the sidewall of the spacer 22 as compared to other portions of the sacrificial oxide film 24. Accordingly, after performing the wet etching process, this area remains thickest compared to other areas.

습식식각공정은 식각용액으로 DHF(Diluted HF; HF:H2O의 혼합비율은 1:99 또는 1:500) 또는 BOE(Buffer Oxide Etchant; HF:NH4F의 혼합비율은 20:1 또는 100:1)를 이용한다. 또한, 습식식각공정의 식각시간은 DHF 또는 BOE의 혼합비율에 따른 식각속도를 고려하여 적절히 설정된다. 즉, 습식식각공정후 잔재하는 희생 산화막(24)의 잔재두께는 도 9에 도시된 확산층 이온주입공정을 통해 형성되는 중간 확산층(20b) 및 깊은 확산층(20c)의 깊이를 고려하여 적절히 조절하는 것이 바람직하다. In the wet etching process, the mixing ratio of DHF (Diluted HF; HF: H 2 O is 1:99 or 1: 500) or BOE (Buffer Oxide Etchant; HF: NH 4 F is 20: 1 or 100. Use: 1). In addition, the etching time of the wet etching process is appropriately set in consideration of the etching rate according to the mixing ratio of DHF or BOE. That is, the remaining thickness of the sacrificial oxide film 24 remaining after the wet etching process is appropriately adjusted in consideration of the depths of the intermediate diffusion layer 20b and the deep diffusion layer 20c formed through the diffusion layer ion implantation process shown in FIG. 9. desirable.

한편, 본 발명에서는 습식식각공정 대신에 건식식각공정을 실시하여도 무방하나, 건식식각공정을 실시할 경우에는 도 7에서 노출된 게이트 전극(16)의 상부가 식각될 수 있기 때문에 여기서는 습식식각공정을 실시하는 것이 공정상 바람직하다. Meanwhile, in the present invention, the dry etching process may be performed instead of the wet etching process. However, when the dry etching process is performed, the upper part of the gate electrode 16 exposed in FIG. 7 may be etched. It is preferable to perform the process.

도 9를 참조하면, 전체 구조 상부에 확산층 이온주입 마스크용 포토레지스트 패턴(미도시)을 형성한 후, 이 포토레지스트 패턴을 마스크로 이용하고, 'n+' 이온을 이용한 확산층 이온주입공정을 실시하여 P-웰에 중간 확산층(20b) 및 깊은 확산층(20c)을 형성한다. 이로써, 얕은 확산층(20a), 중간 확산층(20b) 및 깊은 확산층(20c)의 3중 층으로 이루어진 소오스 및 드레인 확산층(28 및 30)이 형성된다. Referring to FIG. 9, after forming a photoresist pattern (not shown) for a diffusion layer ion implantation mask on the entire structure, the photoresist pattern is used as a mask and a diffusion layer ion implantation process using 'n + ' ions is performed. To form an intermediate diffusion layer 20b and a deep diffusion layer 20c in the P-well. As a result, the source and drain diffusion layers 28 and 30 formed of the triple layer of the shallow diffusion layer 20a, the intermediate diffusion layer 20b, and the deep diffusion layer 20c are formed.

이때, 중간 확산층(20b)은 얕은 확산층(20a)의 깊이에 비해 비교적 깊게 형성되며, 일부가 스페이서(22)와 중첩되지 않도록 형성된다. 즉, 중간 확산층(20b)은 일측단부가 스페이서(22)의 두께만큼 게이트 전극(16)과 이격되도록 형성된다. 깊은 확산층(20c)은 중간 확산층(20b)의 깊이와 동일하게 형성되거나 더 깊게 형성된다. In this case, the intermediate diffusion layer 20b is formed to be relatively deep compared to the depth of the shallow diffusion layer 20a, and a portion of the intermediate diffusion layer 20b does not overlap with the spacer 22. That is, the intermediate diffusion layer 20b is formed such that one end thereof is spaced apart from the gate electrode 16 by the thickness of the spacer 22. The deep diffusion layer 20c is formed to be the same as or deeper than the depth of the intermediate diffusion layer 20b.                     

이후공정은 희생 산화막(24)을 제거한 후 일반적인 공정과 동일한 방법으로 진행한다. After the process is removed, the sacrificial oxide film 24 is removed in the same manner as the general process.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예들에서 구체적으로 기술되었으나, 상기한 실시예들은 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 이 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에서는 게이트 전극을 형성한 후 소오스 및 드레인 확산층을 3중 층 구조로 형성하는 반도체 소자의 제조방법을 제공함으로써 단채널 효과를 감소시키면서 접합누설전류특성 및 게이트 전극 도핑효율특성을 동시에 확보할 수 있다. 더 나아가, 본 발명은 반도체 소자의 고집적화 및 신뢰성을 향상시킬 수 있다. As described above, the present invention provides a method of manufacturing a semiconductor device in which a source and drain diffusion layer is formed in a triple layer structure after forming a gate electrode, thereby reducing junction short-circuit effect and reducing gate leakage current characteristics and gate electrode doping efficiency. Characteristics can be secured at the same time. Furthermore, the present invention can improve high integration and reliability of semiconductor devices.

Claims (8)

(a) 반도체 기판에 소자 분리막을 형성하는 단계;(a) forming an isolation layer on the semiconductor substrate; (b) 상기 소자 분리막 사이에 게이트 전극을 형성하는 단계;(b) forming a gate electrode between the device isolation layers; (c) 상기 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 얕은 확산층을 형성하는 단계;(c) forming a shallow diffusion layer on the semiconductor substrate exposed to both sides of the gate electrode; (d) 상기 게이트 전극의 양측벽에 스페이서를 형성하는 단계;(d) forming spacers on both sidewalls of the gate electrode; (e) 전체 구조 상부에 희생 산화막 및 포토레지스트막을 순차적으로 증착한 후 평탄화하여 상기 게이트 전극의 상부를 노출시키는 단계;(e) sequentially depositing a sacrificial oxide film and a photoresist film on the entire structure and then planarizing the exposed upper portion of the gate electrode; (f) 제1 습식식각공정을 선택적으로 실시하여 상기 포토레지스트막을 제거하는 단계; (f) selectively performing a first wet etching process to remove the photoresist film; (g) 제2 습식식각공정을 실시하여 상기 반도체 기판을 기준으로 상기 희생 산화막의 증착부위 중 다른 부위에 비하여 상기 스페이서와 인접하게 증착된 부위가 두껍게 잔재되도록 하는 단계; 및(g) performing a second wet etching process so that the deposited portions adjacent to the spacers remain thicker than other portions of the deposition regions of the sacrificial oxide film based on the semiconductor substrate; And (h) 상기 스페이서를 마스크로 이용한 이온주입공정을 실시하여 상기 얕은 확산층보다 깊게 중간 확산층 및 깊은 확산층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.(h) forming a middle diffusion layer and a deep diffusion layer deeper than the shallow diffusion layer by performing an ion implantation process using the spacer as a mask. 제 1 항에 있어서, The method of claim 1, 상기 얕은 확산층은 일부가 상기 스페이서와 중첩되도록 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.And the shallow diffusion layer is formed so that a portion thereof overlaps with the spacer. 제 1 항에 있어서, The method of claim 1, 상기 중간 확산층은 상기 게이트 전극의 일측벽을 기준으로 하여 상기 얕은 확산층보다 상기 스페이서 두께만큼 이격되는 것을 특징으로 하는 반도체 소자의 제조방법.The intermediate diffusion layer is a semiconductor device manufacturing method, characterized in that spaced apart from the shallow diffusion layer by the spacer thickness based on one side wall of the gate electrode. 제 1 항에 있어서, The method of claim 1, 상기 희생 산화막은 LPCVD 공정을 이용하여 200 내지 500Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 제조방법.The sacrificial oxide film is a method of manufacturing a semiconductor device, characterized in that to deposit a thickness of 200 to 500Å by using an LPCVD process. 제 1 항에 있어서, The method of claim 1, 상기 포토레지스트막은 상기 게이트 전극의 두께보다 두껍게 형성되는 것을 특징으로 하는 반도체 소자의 제조방법. And the photoresist film is formed thicker than the thickness of the gate electrode. 제 1 항에 있어서, The method of claim 1, 상기 평탄화 공정은 건식식각방식을 이용한 식각공정으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The planarization process is a manufacturing method of a semiconductor device, characterized in that performed by the etching process using a dry etching method. 제 1 항에 있어서, The method of claim 1, 상기 제1 습식식각공정은 H2SO4 : H2O2가 혼합된 SPM 용액을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법. The first wet etching process is a method of manufacturing a semiconductor device, characterized in that performed using a SPM solution mixed with H 2 SO 4 : H 2 O 2 . 제 1 항에 있어서, The method of claim 1, 상기 제2 습식식각공정은 DHF 또는 BOE 용액을 이용하여 실시하되, 상기 DHF는 HF:H2O의 혼합비율이 1:99 또는 1:500이고, 상기 BOE는 HF:NH4F의 혼합비율이 20:1 또는 100:1인 것을 특징으로 하는 반도체 소자의 제조방법.The second wet etching process is performed using a DHF or BOE solution, wherein the mixing ratio of HF: H 2 O is 1:99 or 1: 500, and the mixing ratio of HF: NH 4 F is BH. 20: 1 or 100: 1 manufacturing method of a semiconductor device.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536719A (en) * 1990-11-05 1993-02-12 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH06196495A (en) * 1992-11-04 1994-07-15 Matsushita Electric Ind Co Ltd Semiconductor device, complementary semiconductor device, and manufacture thereof
JPH07142726A (en) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd Manufacture of field effect transistor
KR19980034238A (en) * 1996-11-06 1998-08-05 문정환 Structure and Manufacturing Method of Semiconductor Device
US6225176B1 (en) * 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
KR20040036801A (en) * 2002-10-24 2004-05-03 주식회사 하이닉스반도체 Semiconductor device and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536719A (en) * 1990-11-05 1993-02-12 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH06196495A (en) * 1992-11-04 1994-07-15 Matsushita Electric Ind Co Ltd Semiconductor device, complementary semiconductor device, and manufacture thereof
JPH07142726A (en) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd Manufacture of field effect transistor
KR19980034238A (en) * 1996-11-06 1998-08-05 문정환 Structure and Manufacturing Method of Semiconductor Device
US6225176B1 (en) * 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
KR20040036801A (en) * 2002-10-24 2004-05-03 주식회사 하이닉스반도체 Semiconductor device and method of manufacturing the same

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