KR20070002661A - Method for forming transistor of semiconductor device - Google Patents

Abstract

A method for forming a transistor in a semiconductor device is provided to improve the uniformity of threshold voltage and to prevent misalignment between a recess gate and a gate electrode by using a mask insulating pattern. An insulating pattern(113-1) is formed on a substrate(111) to define a gate line region. A recess gate region is formed by using the insulating pattern as a mask. A gate oxide layer and a first polysilicon layer(121) are formed in the recess gate region and the gate line region. The exposed gate oxide layer is selectively removed. A second polysilicon layer, a metal film and a hard mask layer are sequentially stacked on the resultant structure. By removing the insulating pattern, a gate line is formed.

Description

Method for forming transistor of semiconductor device {Method for Forming Transistor of Semiconductor Device}

1A to 1C are process schematic diagrams showing a conventional transistor forming method.

2A to 2H are process schematic diagrams illustrating a method for forming a transistor according to the present invention.

<Brief description of the main parts of the drawing>

1, 111: semiconductor substrate 3, 119: gate oxide film

5: polycrystalline polysilicon layer 7, 127: metal layer

9, 129: Hard Mask 11: Property Fire

13: spacer 15: ion implantation region

113: insulating film 113-1: insulating film pattern

115: photoresist pattern 116: gate line region

117: recess gate region 118: region where the insulating film pattern is removed

121: primary polycrystalline polysilicon layer 123: removed upper region of gate oxide film

125: secondary polycrystalline polysilicon layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and by using an insulating layer pattern for a recess gate forming process in a process of stacking a gate material layer constituting a gate line, misalignment between the recess gate and the gate line is eliminated. A transistor forming method of a semiconductor device can be improved.

Today, as the field of application of semiconductor devices expands, there is an urgent need to develop process facilities or process technologies for manufacturing semiconductor devices with low manufacturing costs and improved integration and electrical properties.

In order to increase the degree of integration of a semiconductor device, the line width of the gate constituting the transistor, the thickness of the gate dielectric layer, and the junction depth of the source / drain should be reduced. However, when the gate line width is reduced to 90 nm or less, the depletion region of the source / drain region penetrates into the channel, thereby causing a short channel effect in which the effective channel length is reduced.

In order to improve the short channel effect, a method of injecting impurities of opposite conductivity type into the lower portion of the channel region is introduced in addition to the conventional shallow junction process. However, this method causes punch through between source / drain regions due to diffusion of impurities during impurity injection, leading to malfunction of the device.

In this regard, as another method for securing an effective channel length for the gate line width, a transistor structure including a recess gate and a transistor structure for forming a source / drain region on the substrate surface have been developed.

In this case, the transistor structure for forming the source / drain region on the substrate surface has a disadvantage in that the process step and the process cost are increased because the step of forming a silicon epitaxial layer on the surface should be further included.

Accordingly, more transistor forming methods including recess gate regions that can utilize conventional process methods are used. The transistor forming method including the recess gate region is a method of increasing the effective channel length by forming a thin trench having a thickness deeper than the junction depth of the source / drain regions on the active region by a dry etching process.

A method of forming a transistor including a recess gate region according to the related art as described above will be described in detail with reference to FIGS. 1A to 1C.

Referring to FIG. 1A, an upper portion of an active region (not shown) of a semiconductor substrate 1 having a device isolation region (not shown) is etched to form a recess gate region (not shown), and then the recess gate region. The gate oxide film (not shown), the polycrystalline polysilicon layer (not shown), the metal layer (not shown), and the hard mask nitride film (not shown) are sequentially formed and etched with respect to the formed structure of the gate oxide pattern (3), A polycrystalline polysilicon layer pattern 5, a metal layer pattern 7, and a hard mask nitride film pattern 9 are sequentially formed to form a gate line pattern.

The semiconductor substrate 1 on which the gate line pattern of FIG. 1A is formed is annealed in an oxygen atmosphere at an appropriate temperature to form a gate reoxidation film 11.

Next, an insulating film (not shown) is formed on the entire surface of the structure including the gate reoxidation film 11 of FIG. 1B and then etched to form a spacer 13 on the sidewall of the gate line pattern as shown in FIG. 1C. To form. The source / drain regions 15 are formed by ion implantation using the spacer 13 by a self alignment method.

However, the method of forming the recess gate is typically performed by (i) forming a recess gate region on the active region of the semiconductor substrate having the device isolation region by an exposure and etching process, and then (ii) the exposure and etching process. Since the process is performed to form a gate line under a process condition different from that of the process, a misalignment occurs between two structures, resulting in an uneven increase in the threshold voltage of the cell transistor. As a result, it is difficult to secure devices such as transistors and capacitors that perform stable operation, and semiconductor device yield is reduced.

Accordingly, the present inventors have completed the present invention by developing a method of forming a transistor of a semiconductor device capable of improving alignment errors between a recess gate region and a gate line without developing expensive equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional transistor manufacturing method as described above, and a transistor of a semiconductor device having a new concept of using a recess mask forming etching mask pattern when stacking a gate material layer constituting a gate line. It is an object to provide a method.

Further, an object of the present invention is to provide a method for forming a transistor of a semiconductor device in which a polycrystalline polysilicon layer is formed in two steps by a self-aligning method in stacking the gate material constituting the gate line.

In order to achieve the above object, in the present invention

Forming an insulating layer pattern defining a gate line region on the semiconductor substrate;

Forming a recess gate region using the insulating layer pattern as an etching mask;

Forming a gate oxide film and a primary polycrystalline polysilicon layer in the recess gate region and the gate line region, and etching to a predetermined thickness to expose the gate oxide film;

Removing the exposed upper portion of the gate oxide layer by a selective etching process;

Sequentially forming a second polycrystalline polysilicon layer, a metal layer, and a hard mask film on the front of the structure; And

And forming a gate line by removing the insulating layer pattern.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2H.

First, referring to FIG. 2A, an insulating film 113 and a photoresist pattern 115 by an exposure and development process are sequentially formed on a semiconductor substrate 111 having an isolation region (not shown).

In this case, the insulating film is formed of an oxide film (SiO ₂ ). In this case, the insulating layer is not particularly limited as long as the thickness is the same as the height of the gate line formed in the subsequent process or is thicker than the height of the gate line.

The insulating film pattern 113-1 defining the gate line region 116 is formed using the photoresist pattern 115 of FIG. 2A as an etch mask, and then the mask insulating film pattern 113 as shown in FIG. 2B. Recess gate region 117 is formed using -1) as an etching mask.

Subsequently, an inner sidewall of the insulating layer pattern 113-1 is removed 118 with a selective etching solution that removes only an oxide layer to secure a width of a gate line formed by a subsequent process.

In this case, the selective etching solution uses HF or NH ₄ .

As shown in FIG. 2C, the gate oxide layer 119 and the planarized first polycrystalline polysilicon layer 121 are formed on the entire surface including the recess gate region 117 and the insulating layer pattern 113-1 of FIG. 2B. Form sequentially.

A self-aligned etching process is performed on the gate oxide layer 119 and the first polycrystalline polysilicon layer 121 by using the insulating layer pattern 113-1 of FIG. 2C as an etching mask. As described above, the structures are formed to a predetermined thickness in the gate line region 116 by the etching process, and the upper portion of the gate oxide layer 119 is exposed. Thereafter, a selective etching process is performed on the structure to remove an upper portion of the exposed gate oxide layer formed between the insulating layer pattern 113-1 and the primary polycrystalline polysilicon layer 121 as shown in FIG. 2D. (123).

In the selective etching process, the etching selectivity of the oxide film is higher than that of polysilicon, and the thickness of the gate oxide film 119 to be removed is 50 to 150 kPa, more preferably 100 kPa.

If the selective etching process is not performed on the gate oxide layer, the gate oxide layer 119 exposed during the subsequent etching process of removing the insulating layer pattern 113-1 to form the gate line is lost. Because the field of the edge of the deterioration deteriorates, the gate induced drain leakage (GIDL) characteristic of the device is deteriorated.

Subsequently, as shown in FIG. 2E, the planarized secondary polycrystalline polysilicon layer 125 is formed on the entire structure of FIG. 2D, and a self-aligned etching method using the insulating layer pattern 113-1 as an etching mask is performed. As shown in FIG. 2F, a secondary polycrystalline polysilicon layer 125 having a predetermined thickness is formed in the gate line region 116.

Next, as shown in FIG. 2G, the metal layer 127 and the hard mask layer 129 having the predetermined thickness are disposed on the secondary polycrystalline polysilicon layer 125 having the predetermined thickness of FIG. 2F by using a self-aligned etching method. Form sequentially.

A gate line pattern as shown in FIG. 2H is formed by performing a self-aligned etching process of removing the insulating layer pattern 113-1 by using the upper hard mask layer 129 of the structure obtained in FIG. 2G as an etching mask. .

Thereafter, an insulating film (not shown) is formed on the entire gate line pattern of FIG. 2H and then etched to form a spacer (not shown). A transistor is formed by forming a source / drain region by a self-aligning method using the spacer (not shown) as an ion implantation mask.

As described above, in the present invention, the mask insulating layer pattern for forming the recess gate is used in stacking the gate material layer constituting the gate line, thereby improving the alignment error between the recess gate and the gate electrode, thereby making the transistor nonuniform in threshold voltage. Can be improved.

As described above, in the present invention, the mask insulating layer pattern for forming the gate is used for stacking the gate material layer constituting the gate line, thereby improving the alignment error between the recess gate and the gate electrode, thereby resulting in nonuniformity of the threshold voltage of the transistor. It can be improved to form a transistor with improved reliability.

Claims (7)

Forming an insulating layer pattern defining a gate line region on the semiconductor substrate; Forming a recess gate region using the insulating layer pattern as an etching mask; Forming a gate oxide film and a primary polycrystalline polysilicon layer in the recess gate region and the gate line region, and etching to a predetermined thickness to expose the gate oxide film; Removing the exposed upper portion of the gate oxide layer by a selective etching process; Sequentially forming a second polycrystalline polysilicon layer, a metal layer, and a hard mask film on the front of the structure; And Forming a gate line by removing the insulating layer pattern. The method of claim 1, And the insulating film pattern is an oxide film (SiO ₂ ). The method of claim 1, And the insulating film pattern has a thickness equal to a height of a gate line or a thickness thicker than a height of a gate line. The method of claim 1, After forming the recess gate, etching the inner sidewall of the insulating layer pattern to have a thickness sufficient to secure the width of the gate line using a selective etching solution. Forming method. The method of claim 4, wherein The selective etching solution is a method of forming a transistor of the semiconductor device, characterized in that a mixed solution of HF and NH ₄ . The method of claim 1, And exposing the upper portion of the exposed gate oxide layer by a thickness of 50 to 150 kV. A semiconductor device manufactured using the method of claim 1.

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