KR20070002700A - Method for forming transistor of semiconductor device - Google Patents

Abstract

A method for forming a transistor of a semiconductor device is provided to improve an align error between a recess gate region and a gate line by forming the recess gate region using a sidewall nitride pattern of a trench. An insulating pattern is formed on a semiconductor substrate(111). A trench is formed on the resultant structure by etching selectively the substrate using the insulating pattern as an etch mask. A nitride layer is formed on the resultant structure. A sidewall nitride pattern(117-1) is formed in the trench by etching the nitride layer. A recess gate region(119) is formed on the resultant structure by performing etching using the sidewall nitride pattern as an etch mask.

Description

Method for forming transistor of semiconductor device {Method for Forming Transistor of Semiconductor Device}

1A to 1C are process schematic diagrams showing a conventional transistor forming method.

2A to 2H are process schematic diagrams illustrating a method for forming a transistor according to the present invention.

<Brief description of the main parts of the drawing>

1, 111: semiconductor substrate 3, 121: gate oxide film

5, 123: polycrystalline polysilicon layer 7, 125: metal layer

9, 127: Hard Mask Film 11: Property Paint

13: spacer 15: ion implantation region

113: insulating film layer for forming a gate line

113-1: Insulation Pattern for Gate Line Formation

115: photoresist pattern 117: nitride film

117-1: nitride film pattern 119: recess gate region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor in a semiconductor device, wherein a sidewall nitride film pattern is formed inside a trench for forming a gate line, and then a recess gate region is formed using the same as an etching mask, thereby aligning the recess gate and the gate line. The present invention relates to a method for forming a transistor of a semiconductor device capable of improving misalignment.

As the field of application of semiconductor devices expands today, there is an urgent need for development of process equipment or process technologies for manufacturing high-capacity semiconductor devices with low manufacturing costs and improved integration and electrical properties. In this regard, various studies have been conducted to obtain stable process conditions by improving photo-lithography processes, cell structures, physical property limits of wiring forming materials and insulating film forming materials, and the like.

On the other hand, due to the high integration of the semiconductor device, the transistor size including physical dimensions such as the gate line line width of the semiconductor device and the dielectric film thickness of the gate line is reduced, while the depletion region of the source / drain region penetrates into the channel. In other words, a short channel effect is induced in which the effective channel length is reduced.

As a result, it is not only difficult to secure the data retention time of the semiconductor device, but also the process margin is reduced to increase the junction leakage current.

In order to improve the short channel effect, a conventional method of injecting an impurity of opposite conductivity type into the lower portion of the channel region together with a shallow junction process has been introduced, but rather the punch through between source / drain regions as the impurities diffuse. (punch through) was generated, causing malfunction of the device.

In this regard, as another method for securing an effective channel length for the gate line width, a transistor structure including a recess gate and a transistor structure for forming a source / drain region on the substrate surface have been developed.

In this case, the transistor structure for forming the source / drain region on the substrate surface has a disadvantage in that the process step and the process cost are increased because the step of forming a silicon epitaxial layer on the surface should be further included.

Therefore, a transistor forming method including a recess gate region to which a conventional process method can be applied is used more. The transistor forming method including the recess gate region is a method of increasing the effective channel length by forming a thin trench having a thickness deeper than the junction depth of the source / drain regions on the active region by a dry etching process.

A method of forming a transistor including a recess gate region according to the related art as described above will be described in detail with reference to FIGS. 1A to 1C.

Referring to FIG. 1A, an upper portion of an active region (not shown) of a semiconductor substrate 1 having a device isolation region (not shown) is etched to form a recess gate region (not shown), and then the recess gate region. A gate oxide film (not shown), a polycrystalline polysilicon layer (not shown), a metal layer (not shown), and a hard mask nitride film (not shown) are sequentially formed on the formed resultant structure.

The structures are etched to form a gate line pattern in which the gate oxide pattern 3, the polycrystalline polysilicon layer pattern 5, the metal layer pattern 7, and the hard mask nitride layer pattern 9 are sequentially stacked.

The semiconductor substrate 1 on which the gate line pattern of FIG. 1A is formed is annealed in an oxygen atmosphere at an appropriate temperature to form a gate reoxidation film 11.

Next, an insulating film (not shown) is formed on the entire surface of the structure including the gate reoxidation film 11 of FIG. 1B and then etched to form a spacer 13 on the sidewall of the gate line pattern as shown in FIG. 1C. Form. The source / drain regions 15 are formed by ion implantation using the spacer 13 by a self alignment method.

However, a method of forming a transistor including the recess gate region typically includes (i) forming a recess gate region in an active region of a semiconductor substrate provided with an isolation region by a process of exposure and etching, and then (ii) Forming a gate line on the recess gate region. In this case, since the exposure and etching processes of the respective structures are performed under different process conditions, a misalignment occurs between the two structures, resulting in an uneven increase in the threshold voltage of the cell transistor. As a result, it is difficult to secure a transistor or a capacitor that performs a stable operation, and the yield of the semiconductor element is reduced.

Accordingly, the present inventors have completed the present invention by developing a method of forming a transistor of a semiconductor device capable of improving alignment errors between a recess gate region and a gate line without developing expensive equipment.

The present invention has been made to solve the problem of alignment error occurred in the conventional transistor formation process as described above, by forming a nitride film pattern on the inner sidewall of the trench for forming a gate line, by using a recess gate region It is an object of the present invention to provide a method capable of forming a transistor having improved reliability.

In order to achieve the above object, in the present invention

Forming an insulating film pattern for forming a gate line on the semiconductor substrate;

Etching the semiconductor substrate using the insulating layer pattern as an etching mask to form a trench;

Forming a nitride film on the entire surface of the structure;

Etching the nitride film to form a sidewall nitride film pattern in the trench;

Forming a recess gate region using the sidewall nitride layer pattern as an etch mask;

After removing the sidewall nitride layer pattern, forming a gate oxide layer and a polycrystalline polysilicon layer having a predetermined thickness on an entire surface of the structure;

Sequentially forming a planarized metal layer having a predetermined thickness and a hard mask layer on the polycrystalline polysilicon layer; And

And forming a gate line by etching the insulating layer pattern and the semiconductor substrate having a predetermined thickness using the hard mask layer as an etch mask.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2H.

First, referring to FIG. 2A, the insulating film layer 113 for forming a gate line and the photoresist pattern 115 by an exposure and development process are sequentially formed on a semiconductor substrate 111 having an isolation region (not shown). Form.

In this case, the insulating film is formed to have a thickness of 2000 to 3000 kPa, preferably 2500 kPa using an oxide film (SiO ₂ ).

An insulating film pattern 113-1 is formed using the photoresist pattern of FIG. 2A as an etching mask, and then an active region (not shown) of the semiconductor substrate is formed using the insulating film pattern 113-1 as an etching mask. A gate line forming trench (not shown) is formed.

In this case, the trench preferably has a depth of 3000 to 5000 kPa, preferably 4000 kPa from the top of the insulating film pattern.

A nitride film 117 is formed on the entire surface of the structure including the gate line forming trench (not shown) as shown in FIG. 2B.

Next, an anisotropic dry etching process is performed on the nitride layer 117 until the semiconductor substrate is exposed to form the nitride layer pattern 117-1 on the inner side of the trench as illustrated in FIG. 2C.

An etching process is performed on the semiconductor substrate exposed to the nitride film pattern 117-1 of FIG. 2C with an etching mask to form a recess gate region 119 as illustrated in FIG. 2D.

A gate oxide layer 121 is formed on the entire surface of the structure including the recess gate region 119 of FIG. 2D, and then a planarized polycrystalline polysilicon layer (not shown) is formed on the entire surface of the structure including the gate oxide layer.

A polycrystalline polysilicon layer 123 having a predetermined thickness as shown in FIG. 2F by etching the recess gate region 119 and the trench region in a self-aligned etching process using the insulating layer pattern 1131-1 as an etching mask. To form.

At this time, the thickness of the polycrystalline polysilicon layer is preferably 3000 to 3500 Pa.

Next, the planarized metal layer 125 having a predetermined thickness is formed on the polycrystalline polysilicon layer 123 of FIG. 2F by a self-aligned etching process using the insulating layer pattern 113-1 as an etching mask as shown in FIG. 2G. And a hard mask film 127 are sequentially formed.

After performing the selective etching process on the structure of FIG. 2G, all the insulating film patterns 113-1 are removed until the semiconductor substrate 111 is exposed, and then the hard mask film 127 is shown in FIG. 2H. The semiconductor substrate 111 is etched by a self-aligned etching method using the etching mask to form a gate line (not shown).

In this case, the self-aligned etching process may be performed by setting a semiconductor substrate region as an etching target at a depth of 5000 to 8000 Pa, preferably 6500 Pa, from the hard mask film.

Next, a selective oxidation process is performed to oxidize the semiconductor substrate 111 on which the gate line (not shown) of FIG. 2H is formed under a large amount of hydrogen atmosphere, thereby forming a reoxidation film (not shown) around the gate line (not shown). May be formed).

The reoxidation process recovers micro trenches and damages in the gate oxide layer formed during the etching after the gate electrode is etched, oxidizes the remaining electrode material remaining on the semiconductor substrate 111, and gates at the edge of the gate electrode. The reliability of the semiconductor device can be improved by increasing the thickness of the oxide film.

After that, an insulating film (not shown) is formed over the gate electrode on which the gate reoxidation film is formed, and then, the entire structure is etched to form a spacer (not shown) on the sidewall of the gate electrode pattern, and then the field oxide film (not shown). Transistors are fabricated by ion implantation by means of a self-aligning method using an array) and a spacer (not shown) to form source and drain regions.

In addition, the present invention provides a semiconductor device manufactured using the above method.

As described above, in the present invention, a nitride pattern is formed on the inner sidewall of the trench for forming the gate line, and then a recess gate region is formed using the nitride layer pattern, thereby forming an alignment error between the recess gate region and the gate line generated in the conventional transistor forming process. It can be improved to improve the nonuniformity of the threshold voltage of the transistor.

As described above, in the present invention, a nitride pattern is formed on the inner sidewall of the trench for forming the gate line, and then a recess gate region is formed using the nitride layer pattern, thereby improving alignment errors between the recess gate region and the gate line generated in the conventional transistor forming process. As a result, it is possible to improve the nonuniformity of the threshold voltage of the transistor, thereby forming a transistor having improved reliability.

Claims (5)

Forming an insulating film pattern for forming a gate line on the semiconductor substrate; Etching the semiconductor substrate using the insulating layer pattern as an etching mask to form a trench; Forming a nitride film on the entire surface of the structure; Etching the nitride film to form a sidewall nitride film pattern in the trench; Forming a recess gate region using the sidewall nitride layer pattern as an etch mask; After removing the sidewall nitride layer pattern, forming a gate oxide layer and a polycrystalline polysilicon layer having a predetermined thickness on an entire surface of the structure; Sequentially forming a planarized metal layer having a predetermined thickness and a hard mask layer on the polycrystalline polysilicon layer; And Forming a gate line by etching the insulating layer pattern and a semiconductor substrate having a predetermined thickness using the hard mask layer as an etch mask. The method of claim 1, And the insulating film pattern is formed to have a thickness of 2000 to 3000 mW using an oxide film (SiO ₂ ). The method of claim 1, And said trench is formed at a depth of 3000 to 5000 microns. The method of claim 1, And etching the gate line to form a semiconductor substrate region of 5000 to 8000 microns deep from the surface of the hard mask film as an etching target. A semiconductor device manufactured using the method of claim 1.

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