CN115732412A - Method for manufacturing semiconductor structure - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor structure, which includes the following steps. Provide the base. The base includes a first area and a second area. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer. A second gate is formed on the second dielectric layer. A first spacer is formed on the sidewall of the first gate, and a second spacer is formed on the sidewall of the second gate at the same time. A patterned photoresist layer is formed. The patterned photoresist layer covers the first spacer and exposes the second spacer. Using the patterned photoresist layer as a mask, the second spacer is removed. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is formed on the sidewall of the second gate at the same time.

Description

Fabrication method of semiconductor structure

technical field

The invention relates to a semiconductor manufacturing process, and in particular to a manufacturing method of a semiconductor structure.

Background technique

With the advancement of semiconductor manufacturing process technology, the semiconductor industry continues to reduce the size of semiconductor devices. Therefore, in a semiconductor structure having both low voltage devices and high voltage devices, spacer engineering between different semiconductor devices will face challenges. For example, when both the low-voltage device and the high-voltage device have smaller spacers, the high-voltage device will have a higher leakage current, thereby reducing the electrical performance of the high-voltage device.

Contents of the invention

The invention provides a method for manufacturing a semiconductor structure, which can effectively improve the electrical performance of semiconductor elements in different element regions.

The invention provides a method for manufacturing a semiconductor structure, which includes the following steps. Provide the base. The base includes a first area and a second area. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer in the first region. A second gate is formed on the second dielectric layer in the second region. A first spacer is formed on the sidewall of the first gate, and a second spacer is formed on the sidewall of the second gate at the same time. A patterned photoresist layer is formed in the first region. The patterned photoresist layer covers the first spacer and exposes the second spacer. Using the patterned photoresist layer as a mask, the second spacer is removed. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is formed on the sidewall of the second gate at the same time.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the method for simultaneously forming the first spacer and the second spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. An etching process is performed on the spacer material layer.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the etching process is, for example, a dry etching process.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the method for removing the second spacer includes, for example, a wet etching method, a dry etching method or a combination thereof.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the method for simultaneously forming the third spacer and the fourth spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. An etching process is performed on the spacer material layer.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the etching process is, for example, a dry etching process.

According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. Before forming the first spacer and the second spacer, a spacer layer is formed on the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the sidewall of the second gate. The spacer layer can expose the top surface of the first gate and the top surface of the second gate.

According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. After forming the third spacer and the fourth spacer, the spacer layer exposed by the first spacer, the third spacer and the fourth spacer can be removed, and the first spacer and the first grid A fifth spacer is formed between the first spacer and the first dielectric layer, and between the third spacer and the first dielectric layer, and between the fourth spacer and the second gate and the fourth A sixth spacer is formed between the spacer and the second dielectric layer.

According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. Before forming the spacer layer, a fifth spacer may be formed on the sidewall of the first gate, and a sixth spacer may be formed on the sidewall of the second gate at the same time.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the first region may be a high-voltage device region, and the second region may be a low-voltage device region.

Based on the above, in the manufacturing method of the semiconductor structure proposed by the present invention, the first spacer and the third spacer are formed on the sidewall of the first gate in the first region, and the second gate in the second region A fourth spacer is formed on the sidewall of the . Therefore, the spacer structure required by the semiconductor elements in the first region and the spacer structure required by the semiconductor elements in the second region can be formed, thereby improving the electrical properties of the semiconductor elements in the first region and the semiconductor elements in the second region. Performance. In addition, by adjusting the size of the first spacer and the third spacer in the first region and the size of the fourth spacer in the second region, the electrical contact between the semiconductor elements in the first region and the semiconductor elements in the second region can be elastically adjusted. sexual performance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention.

Symbol Description

10:Semiconductor structure

100: base

102: Isolation structure

104,106: well area

108,110: dielectric layer

112,114: gate

116, 118, 144, 146: doped regions

120,122,128,130,136,138,140,142: gap wall

124: Interstitial wall layer

126,134: Spacer material layer

132: Patterned photoresist layer

R1: Region 1

R2: second area

Detailed ways

1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention.

A method for manufacturing a semiconductor structure includes the following steps. A substrate 100 is provided. The substrate 100 includes a first region R1 and a second region R2. In some embodiments, the first region R1 may be a high-voltage device region (eg, a high-voltage transistor region), and the second region R2 may be a low-voltage device region (eg, a low-voltage transistor region). The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, an isolation structure 102 may be formed in the substrate 100 . The isolation structure 102 may be a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide.

In some embodiments, a well region 104 may be formed in the substrate 100 in the first region R1. In some embodiments, a well region 106 may be formed in the substrate 100 in the second region R2. The well region 104 and the well region 106 may have a first conductivity type (eg, P type). Herein, the first conductivity type and the second conductivity type are different conductivity types. That is, the first conductivity type and the second conductivity type may be one and the other of the P-type conductivity and the N-type conductivity, respectively. In this embodiment, the first conductivity type is an example of a P-type conductivity type, and the second conductivity type is an example of an N-type conductivity type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be N-type conductivity, and the second conductivity type may be P-type conductivity.

Next, a dielectric layer 108 is formed on the substrate 100 in the first region R1. The material of the dielectric layer 108 is, for example, silicon oxide. The forming method of the dielectric layer 108 is, for example, a thermal oxidation method. In addition, a dielectric layer 110 is formed on the substrate 100 in the first region R2. The material of the dielectric layer 110 is, for example, silicon oxide. The forming method of the dielectric layer 110 is, for example, a thermal oxidation method. In some embodiments, the dielectric layer 108 may be formed first, and then the dielectric layer 110 may be formed.

Then, a gate 112 is formed on the dielectric layer 108 in the first region R1. The material of the gate 112 is, for example, doped polysilicon. In addition, a gate 114 is formed on the dielectric layer 110 in the second region R2. The material of the gate 114 is, for example, doped polysilicon. In some embodiments, the gate 112 and the gate 114 can be formed simultaneously through the same manufacturing process, but the invention is not limited thereto.

In some embodiments, a doped region 116 may be formed in the substrate 100 . The doped region 116 may have a second conductivity type (eg, N type). The doped region 116 can serve as a drift region of a high voltage device (eg, a high voltage transistor). The doped region 116 may be located in the well region 104 . The gate 112 can be located between the doped regions 116 , and the gate 112 can be directly above a portion of the doped regions 116 . In some embodiments, the doped region 116 may be formed before the gate 112 is formed. The method of forming the doped region 116 is, for example, ion implantation.

In some embodiments, doped regions 118 may be formed in the substrate 100 on both sides of the gate 114 . The doped region 118 may have a second conductivity type (eg, N type). The gate doped region 118 can be used as a lightly doped drain (LDD) of a low voltage device (eg, a low voltage transistor). Doped region 118 may be located in well region 106 . In some embodiments, the doped region 118 may be formed after the gate 114 is formed. The method of forming the doped region 118 is, for example, ion implantation.

Next, the spacer 120 may be formed on the sidewall of the gate 112 , and the spacer 122 may be formed on the sidewall of the gate 114 at the same time. The material of the spacer 120 and the spacer 122 is, for example, silicon oxide, but the invention is not limited thereto. The forming method of the spacer 120 and the spacer 122 is, for example, conformally forming a spacer material layer (not shown) on the gate 112 and the gate 114 , and then performing an etching process on the spacer material layer. The method for forming the spacer material layer is, for example, a chemical vapor deposition method. The aforementioned etching process is, for example, a dry etching process.

Furthermore, the spacer layer 124 can be formed on the dielectric layer 108 , the sidewalls of the gate 112 , the dielectric layer 110 and the sidewalls of the gate 114 . The spacer layer 124 can expose the top surface of the gate 112 and the top surface of the gate 114 . In addition, the spacer layer 124 can cover the sidewalls of the spacer 120 and the sidewalls of the spacer 122 . The material of the spacer layer 124 is, for example, silicon nitride, but the invention is not limited thereto. The formation method of the spacer layer 124 is, for example, to conformally form a spacer material layer (not shown) on the gate 112 and the gate 114, and then pattern the spacer material layer through a photolithography process and an etching process. . The method for forming the spacer material layer is, for example, a chemical vapor deposition method. The aforementioned etching process is, for example, a dry etching process.

Subsequently, a spacer material layer 126 may be conformally formed on the gates 112 and 114 . In some embodiments, the spacer material layer 126 can cover the gate 112 , the gate 114 , the spacer 120 , the spacer 122 and the spacer layer 124 . The material of the spacer material layer 126 is, for example, silicon oxide, but the invention is not limited thereto. The formation method of the spacer material layer 126 is, for example, chemical vapor deposition.

Referring to FIG. 1B , an etching process may be performed on the spacer material layer 126 . Thus, the spacer 128 is formed on the sidewall of the gate 112 , and the spacer 130 is formed on the sidewall of the gate 114 at the same time. When performing an etching process on the spacer material layer 126 , the spacer layer 124 can be used as an etching stop layer. In some embodiments, the spacer 128 may be located on the spacer layer 124 in the first region R1, and the spacer 130 may be located on the spacer layer 124 in the second region R2. The etching process performed on the spacer material layer 126 is, for example, a dry etching process.

Referring to FIG. 1C, a patterned photoresist layer 132 is formed in the first region R1. The patterned photoresist layer 132 covers the spacer 128 and exposes the spacer 130 . In some embodiments, the patterned photoresist layer 132 can also cover the gate 112 , the spacer 120 and the spacer layer 124 in the first region R1 . In some embodiments, the patterned photoresist layer 132 can also expose the gate 114 , the spacer 122 and the spacer layer 124 in the second region R2 . The patterned photoresist layer 132 can be formed by a photolithography process.

Referring to FIG. 1D , using the patterned photoresist layer 132 as a mask, the spacers 130 are removed. The removal method of the spacer 130 is, for example, a wet etching method, a dry etching method or a combination thereof.

Referring to FIG. 1E , the patterned photoresist layer 132 may be removed after the spacer 130 is removed. The removal method of the patterned photoresist layer 132 is, for example, dry stripping or wet stripping.

Next, a spacer material layer 134 may be conformally formed on the gate 112 and the gate 114 . In some embodiments, the spacer material layer 134 may cover the gate 112 , the gate 114 , the spacer 120 , the spacer 122 , the spacer layer 124 and the spacer 128 . The material of the spacer material layer 134 is, for example, silicon oxide, but the invention is not limited thereto. The formation method of the spacer material layer 134 is, for example, chemical vapor deposition.

Referring to FIG. 1F , an etching process is performed on the spacer material layer 134 . Thus, the spacer 136 is formed on the sidewall of the spacer 128 , and the spacer 138 is formed on the sidewall of the gate 114 at the same time. When performing an etching process on the spacer material layer 134 , the spacer layer 124 can be used as an etching stop layer. In some embodiments, the spacer 136 may be located on the spacer layer 124 in the first region R1 , and the spacer 138 may be located on the spacer layer 124 in the second region R2 . The etching process performed on the spacer material layer 134 is, for example, a dry etching process.

1G, after forming the spacer 136 and the spacer 138, the spacer layer 124 exposed by the spacer 128, the spacer 136 and the spacer 138 can be removed, and between the spacer 128 and the gate 112 A spacer 140 is formed between the spacer 128 and the dielectric layer 108 and between the spacer 136 and the dielectric layer 108, and between the spacer 138 and the gate 114 and between the spacer 138 and the dielectric layer 110 Spacers 142 are formed.

In some embodiments, a doped region 144 may be formed in the substrate 100 of the first region R1. The doped region 144 may have a second conductivity type (eg, N type). The doped region 144 can serve as a source region or a drain region of a high voltage device (eg, a high voltage transistor). In addition, the doped region 144 may be located in the substrate 100 on one side of the spacer 136 . In addition, doped region 144 may be located in doped region 116 . The method of forming the doped region 144 is, for example, ion implantation.

In some embodiments, a doped region 146 may be formed in the substrate 100 of the second region R2. The doped region 146 can have a second conductivity type (eg, N type). The doped region 146 can serve as a source region or a drain region of a low voltage device (eg, a low voltage transistor). In addition, the doped region 146 may be located in the substrate 100 on one side of the spacer 138 . Additionally, the doped region 146 may be located in the well region 106 . The method of forming the doped region 146 is, for example, ion implantation. In some embodiments, the doped region 146 in the second region R2 may be formed first, and then the doped region 144 in the first region R1 may be formed.

Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the semiconductor structure 10, the spacer 128 and the spacer 136 are formed on the sidewall of the gate 112 in the first region R1, and the sidewall of the gate 114 in the second region R2 A spacer wall 138 is formed thereon. Therefore, the spacer structure required by the semiconductor elements (such as high-voltage elements) in the first region R1 and the spacer structure required by the semiconductor elements (such as low-voltage elements) in the second region R2 can be formed, thereby improving the first Electrical properties of the semiconductor elements (eg, high-voltage elements) in the region R1 and the semiconductor elements (eg, low-voltage elements) in the second region R2 . In addition, by adjusting the size of the spacer 128 and the spacer 136 in the first region R1 and the size of the spacer 138 in the second region R2, the semiconductor elements (such as high voltage elements) and the second region of the first region R1 can be elastically adjusted. The electrical performance of the semiconductor components (eg, low-voltage components) in the region R2.

In the above-mentioned embodiments, the manufacturing method of the semiconductor structure 10 in the above-mentioned embodiments is exemplified by manufacturing high-voltage devices (eg, high-voltage transistors) and low-voltage devices (eg, low-voltage transistors), and the present invention is not limited thereto. In some other embodiments, the manufacturing method of the semiconductor structure 10 of the above-mentioned embodiments can be further applied to components including high-voltage components (such as high-voltage transistors), medium-voltage components (such as medium-voltage transistors) and low-voltage components (such as low-voltage transistors) In the manufacturing process of the semiconductor structure, the description thereof is omitted here. Therefore, the high-voltage component, the medium-voltage component and the low-voltage component can respectively have required spacer structures.

To sum up, through the manufacturing method of the semiconductor structure of the above embodiment, the spacer structure required by different semiconductor elements can be formed, thereby improving the electrical performance of the semiconductor element, and can flexibly adjust the electrical performance of the semiconductor element .

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. A method of manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate includes a first region and a second region; forming a first dielectric layer on the substrate in the first region; forming a second dielectric layer on the substrate in the second region; forming a first gate on the first dielectric layer in the first region; forming a second gate on the second dielectric layer in the second region; forming a first spacer on a sidewall of the first gate, and simultaneously forming a second spacer on a sidewall of the second gate; forming a patterned photoresist layer in the first region, wherein the patterned photoresist layer covers the first spacer and exposes the second spacer; removing the second spacer by using the patterned photoresist layer as a mask; removing the patterned photoresist layer after removing the second spacer; and A third spacer is formed on a sidewall of the first spacer, and a fourth spacer is formed on a sidewall of the second gate at the same time. 2. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for simultaneously forming the first spacer and the second spacer comprises: conformally forming a layer of spacer material on the first gate and the second gate; and An etching process is performed on the spacer material layer. 3. The method of manufacturing a semiconductor structure according to claim 2, wherein the etching process comprises a dry etching process. 4. The method of manufacturing the semiconductor structure as claimed in claim 1, wherein the method for removing the second spacer comprises a wet etching method, a dry etching method or a combination thereof. 5. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for simultaneously forming the third spacer and the fourth spacer comprises: conformally forming a layer of spacer material on the first gate and the second gate; and An etching process is performed on the spacer material layer. 6. The method of manufacturing a semiconductor structure as claimed in claim 5, wherein the etching process comprises a dry etching process. 7. The manufacturing method of the semiconductor structure as claimed in claim 1, further comprising: Before forming the first spacer and the second spacer, the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the second gate A spacer layer is formed on the sidewall of the grid, wherein the spacer layer exposes the top surface of the first gate and the top surface of the second gate. 8. The manufacturing method of the semiconductor structure as claimed in claim 7, further comprising: After forming the third spacer and the fourth spacer, removing the spacer layer exposed by the first spacer, the third spacer and the fourth spacer, Between the first spacer and the first gate, between the first spacer and the first dielectric layer, and between the third spacer and the first dielectric layer A fifth spacer is formed between the fourth spacer and the second gate, and a sixth spacer is formed between the fourth spacer and the second dielectric layer. 9. The method for manufacturing a semiconductor structure as claimed in claim 7, further comprising: Before forming the spacer layer, a fifth spacer is formed on the sidewall of the first gate, and a sixth spacer is formed on the sidewall of the second gate at the same time. 10. The method of manufacturing a semiconductor structure according to claim 1, wherein the first region comprises a high-voltage device region, and the second region comprises a low-voltage device region.

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