CN115732412A - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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CN115732412A
CN115732412A CN202111180868.0A CN202111180868A CN115732412A CN 115732412 A CN115732412 A CN 115732412A CN 202111180868 A CN202111180868 A CN 202111180868A CN 115732412 A CN115732412 A CN 115732412A
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spacer
gate
region
layer
semiconductor structure
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许茗舜
黄韦清
陈文吉
陈辉煌
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Powerchip Technology Corp
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Abstract

本发明公开一种半导体结构的制造方法,包括以下步骤。提供基底。基底包括第一区与第二区。在第一区中的基底上形成第一介电层。在第二区中的基底上形成第二介电层。在第一介电层上形成第一栅极。在第二介电层上形成第二栅极。在第一栅极的侧壁上形成第一间隙壁,且同时在第二栅极的侧壁上形成第二间隙壁。形成图案化光致抗蚀剂层。图案化光致抗蚀剂层覆盖第一间隙壁且暴露出第二间隙壁。利用图案化光致抗蚀剂层作为掩模,移除第二间隙壁。在移除第二间隙壁之后,移除图案化光致抗蚀剂层。在第一间隙壁的侧壁上形成第三间隙壁,且同时在第二栅极的侧壁上形成第四间隙壁。

Figure 202111180868

The invention discloses a method for manufacturing a semiconductor structure, which includes the following steps. Provide the base. The base includes a first area and a second area. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer. A second gate is formed on the second dielectric layer. A first spacer is formed on the sidewall of the first gate, and a second spacer is formed on the sidewall of the second gate at the same time. A patterned photoresist layer is formed. The patterned photoresist layer covers the first spacer and exposes the second spacer. Using the patterned photoresist layer as a mask, the second spacer is removed. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is formed on the sidewall of the second gate at the same time.

Figure 202111180868

Description

半导体结构的制造方法Fabrication method of semiconductor structure

技术领域technical field

本发明涉及一种半导体制作工艺,且特别是涉及一种半导体结构的制造方法。The invention relates to a semiconductor manufacturing process, and in particular to a manufacturing method of a semiconductor structure.

背景技术Background technique

随着半导体制作工艺技术的进步,半导体产业持续不断地缩小半导体元件的尺寸。因此,在同时具有低压元件与高压元件的半导体结构中,在不同半导体元件之间的间隙壁工程将面临挑战。举例来说,当低压元件与高压元件同时具有较小尺寸的间隙壁时,会导致高压元件具有较高的漏电流,进而降低高压元件的电性表现。With the advancement of semiconductor manufacturing process technology, the semiconductor industry continues to reduce the size of semiconductor devices. Therefore, in a semiconductor structure having both low voltage devices and high voltage devices, spacer engineering between different semiconductor devices will face challenges. For example, when both the low-voltage device and the high-voltage device have smaller spacers, the high-voltage device will have a higher leakage current, thereby reducing the electrical performance of the high-voltage device.

发明内容Contents of the invention

本发明提供一种半导体结构的制造方法,其可有效提升不同元件区中的半导体元件的电性表现。The invention provides a method for manufacturing a semiconductor structure, which can effectively improve the electrical performance of semiconductor elements in different element regions.

本发明提出一种半导体结构的制造方法,包括以下步骤。提供基底。基底包括第一区与第二区。在第一区中的基底上形成第一介电层。在第二区中的基底上形成第二介电层。在第一区中的第一介电层上形成第一栅极。在第二区中的第二介电层上形成第二栅极。在第一栅极的侧壁上形成第一间隙壁,且同时在第二栅极的侧壁上形成第二间隙壁。在第一区中形成图案化光致抗蚀剂层。图案化光致抗蚀剂层覆盖第一间隙壁且暴露出第二间隙壁。利用图案化光致抗蚀剂层作为掩模,移除第二间隙壁。在移除第二间隙壁之后,移除图案化光致抗蚀剂层。在第一间隙壁的侧壁上形成第三间隙壁,且同时在第二栅极的侧壁上形成第四间隙壁。The invention provides a method for manufacturing a semiconductor structure, which includes the following steps. Provide the base. The base includes a first area and a second area. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer in the first region. A second gate is formed on the second dielectric layer in the second region. A first spacer is formed on the sidewall of the first gate, and a second spacer is formed on the sidewall of the second gate at the same time. A patterned photoresist layer is formed in the first region. The patterned photoresist layer covers the first spacer and exposes the second spacer. Using the patterned photoresist layer as a mask, the second spacer is removed. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is formed on the sidewall of the second gate at the same time.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,同时形成第一间隙壁与第二间隙壁的方法可包括以下步骤。在第一栅极与第二栅极上共形地形成间隙壁材料层。对间隙壁材料层进行蚀刻制作工艺。According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the method for simultaneously forming the first spacer and the second spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. An etching process is performed on the spacer material layer.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,上述蚀刻制作工艺例如是干式蚀刻制作工艺。According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the etching process is, for example, a dry etching process.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,第二间隙壁的移除方法例如是包括湿式蚀刻法、干式蚀刻法或其组合。According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the method for removing the second spacer includes, for example, a wet etching method, a dry etching method or a combination thereof.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,同时形成第三间隙壁与第四间隙壁的方法可包括以下步骤。在第一栅极与第二栅极上共形地形成间隙壁材料层。对间隙壁材料层进行蚀刻制作工艺。According to an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor structure, the method for simultaneously forming the third spacer and the fourth spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. An etching process is performed on the spacer material layer.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,上述蚀刻制作工艺例如是干式蚀刻制作工艺。According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the etching process is, for example, a dry etching process.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括以下步骤。在形成第一间隙壁与第二间隙壁之前,在第一介电层、第一栅极的侧壁、第二介电层与第二栅极的侧壁上形成间隙壁层。间隙壁层可暴露出第一栅极的顶面与第二栅极的顶面。According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. Before forming the first spacer and the second spacer, a spacer layer is formed on the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the sidewall of the second gate. The spacer layer can expose the top surface of the first gate and the top surface of the second gate.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括以下步骤。在形成第三间隙壁与第四间隙壁之后,可移除由第一间隙壁、第三间隙壁与第四间隙壁所暴露出的间隙壁层,而在第一间隙壁与第一栅极之间、第一间隙壁与第一介电层之间以及第三间隙壁与第一介电层之间形成第五间隙壁,且在第四间隙壁与第二栅极之间以及第四间隙壁与第二介电层之间形成第六间隙壁。According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. After forming the third spacer and the fourth spacer, the spacer layer exposed by the first spacer, the third spacer and the fourth spacer can be removed, and the first spacer and the first grid A fifth spacer is formed between the first spacer and the first dielectric layer, and between the third spacer and the first dielectric layer, and between the fourth spacer and the second gate and the fourth A sixth spacer is formed between the spacer and the second dielectric layer.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括以下步骤。在形成间隙壁层之前,可在第一栅极的侧壁上形成第五间隙壁,且可同时在第二栅极的侧壁上形成第六间隙壁。According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor structure may further include the following steps. Before forming the spacer layer, a fifth spacer may be formed on the sidewall of the first gate, and a sixth spacer may be formed on the sidewall of the second gate at the same time.

依照本发明的一实施例所述,在上述半导体结构的制造方法中,第一区可为高压元件区,且第二区可为低压元件区。According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the first region may be a high-voltage device region, and the second region may be a low-voltage device region.

基于上述,在本发明所提出的半导体结构的制造方法中,在第一区的第一栅极的侧壁上形成第一间隙壁与第三间隙壁,且在第二区的第二栅极的侧壁上形成第四间隙壁。因此,可形成第一区的半导体元件所需的间隙壁结构与第二区的半导体元件所需的间隙壁结构,由此可提升第一区的半导体元件与第二区的半导体元件的电性表现。此外,通过调整第一区中的第一间隙壁与第三间隙壁以及第二区中的第四间隙壁的尺寸,可弹性地调整第一区的半导体元件与第二区的半导体元件的电性表现。Based on the above, in the manufacturing method of the semiconductor structure proposed by the present invention, the first spacer and the third spacer are formed on the sidewall of the first gate in the first region, and the second gate in the second region A fourth spacer is formed on the sidewall of the . Therefore, the spacer structure required by the semiconductor elements in the first region and the spacer structure required by the semiconductor elements in the second region can be formed, thereby improving the electrical properties of the semiconductor elements in the first region and the semiconductor elements in the second region. Performance. In addition, by adjusting the size of the first spacer and the third spacer in the first region and the size of the fourth spacer in the second region, the electrical contact between the semiconductor elements in the first region and the semiconductor elements in the second region can be elastically adjusted. sexual performance.

为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附的附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

附图说明Description of drawings

图1A至图1G为本发明一实施例半导体结构的制造流程剖面图。1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention.

符号说明Symbol Description

10:半导体结构10:Semiconductor structure

100:基底100: base

102:隔离结构102: Isolation structure

104,106:阱区104,106: well area

108,110:介电层108,110: dielectric layer

112,114:栅极112,114: gate

116,118,144,146:掺杂区116, 118, 144, 146: doped regions

120,122,128,130,136,138,140,142:间隙壁120,122,128,130,136,138,140,142: gap wall

124:间隙壁层124: Interstitial wall layer

126,134:间隙壁材料层126,134: Spacer material layer

132:图案化光致抗蚀剂层132: Patterned photoresist layer

R1:第一区R1: Region 1

R2:第二区R2: second area

具体实施方式Detailed ways

图1A至图1G为根据本发明一实施例半导体结构的制造流程剖面图。1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the present invention.

一种半导体结构的制造方法,包括以下步骤。提供基底100。基底100包括第一区R1与第二区R2。在一些实施例中,第一区R1可为高压元件区(如,高压晶体管区),且第二区R2可为低压元件区(如,低压晶体管区)。基底100可为半导体基底,如硅基底。此外,可在基底100中形成隔离结构102。隔离结构102可为浅沟槽隔离(shallow trench isolation,STI)结构。隔离结构102的材料例如是氧化硅。A method for manufacturing a semiconductor structure includes the following steps. A substrate 100 is provided. The substrate 100 includes a first region R1 and a second region R2. In some embodiments, the first region R1 may be a high-voltage device region (eg, a high-voltage transistor region), and the second region R2 may be a low-voltage device region (eg, a low-voltage transistor region). The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, an isolation structure 102 may be formed in the substrate 100 . The isolation structure 102 may be a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide.

在一些实施例中,可在第一区R1中的基底100中形成阱区104。在一些实施例中,可在第二区R2中的基底100中形成阱区106。阱区104与阱区106可具有第一导电型(如,P型)。在本文中,第一导电型与第二导电型为不同导电型。亦即,第一导电型与第二导电型可分别为P型导电型与N型导电型中的一者与另一者。在本实施例中,第一导电型是以P型导电型为例,且第二导电型是以N型导电型为例,但本发明并不以此为限。在另一些实施例中,第一导电型可为N型导电型,且第二导电型可为P型导电型。In some embodiments, a well region 104 may be formed in the substrate 100 in the first region R1. In some embodiments, a well region 106 may be formed in the substrate 100 in the second region R2. The well region 104 and the well region 106 may have a first conductivity type (eg, P type). Herein, the first conductivity type and the second conductivity type are different conductivity types. That is, the first conductivity type and the second conductivity type may be one and the other of the P-type conductivity and the N-type conductivity, respectively. In this embodiment, the first conductivity type is an example of a P-type conductivity type, and the second conductivity type is an example of an N-type conductivity type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be N-type conductivity, and the second conductivity type may be P-type conductivity.

接着,在第一区R1中的基底100上形成介电层108。介电层108的材料例如是氧化硅。介电层108的形成方法例如是热氧化法。此外,在第一区R2中的基底100上形成介电层110。介电层110的材料例如是氧化硅。介电层110的形成方法例如是热氧化法。在一些实施例中,可先形成介电层108,再形成介电层110。Next, a dielectric layer 108 is formed on the substrate 100 in the first region R1. The material of the dielectric layer 108 is, for example, silicon oxide. The forming method of the dielectric layer 108 is, for example, a thermal oxidation method. In addition, a dielectric layer 110 is formed on the substrate 100 in the first region R2. The material of the dielectric layer 110 is, for example, silicon oxide. The forming method of the dielectric layer 110 is, for example, a thermal oxidation method. In some embodiments, the dielectric layer 108 may be formed first, and then the dielectric layer 110 may be formed.

然后,在第一区R1中的介电层108上形成栅极112。栅极112的材料例如是掺杂多晶硅。此外,在第二区R2中的介电层110上形成栅极114。栅极114的材料例如是掺杂多晶硅。在一些实施例中,栅极112与栅极114可通过相同制作工艺同时形成,但本发明并不以此为限。Then, a gate 112 is formed on the dielectric layer 108 in the first region R1. The material of the gate 112 is, for example, doped polysilicon. In addition, a gate 114 is formed on the dielectric layer 110 in the second region R2. The material of the gate 114 is, for example, doped polysilicon. In some embodiments, the gate 112 and the gate 114 can be formed simultaneously through the same manufacturing process, but the invention is not limited thereto.

在一些实施例中,可在基底100中形成掺杂区116。掺杂区116可具有第二导电型(如,N型)。掺杂区116可作为高压元件(如,高压晶体管)的偏移区(drift region)。掺杂区116可位于阱区104中。栅极112可位于掺杂区116之间,且栅极112可位于部分掺杂区116的正上方。在一些实施例中,可在形成栅极112之前,形成掺杂区116。掺杂区116的形成方法例如是离子注入法。In some embodiments, a doped region 116 may be formed in the substrate 100 . The doped region 116 may have a second conductivity type (eg, N type). The doped region 116 can serve as a drift region of a high voltage device (eg, a high voltage transistor). The doped region 116 may be located in the well region 104 . The gate 112 can be located between the doped regions 116 , and the gate 112 can be directly above a portion of the doped regions 116 . In some embodiments, the doped region 116 may be formed before the gate 112 is formed. The method of forming the doped region 116 is, for example, ion implantation.

在一些实施例中,可在栅极114的两侧的基底100中形成掺杂区118。掺杂区118可具有第二导电型(如,N型)。栅极掺杂区118可作为低压元件(如,低压晶体管)的轻掺杂漏极(lightly doped drain,LDD)。掺杂区118可位于阱区106中。在一些实施例中,可在形成栅极114之后,形成掺杂区118。掺杂区118的形成方法例如是离子注入法。In some embodiments, doped regions 118 may be formed in the substrate 100 on both sides of the gate 114 . The doped region 118 may have a second conductivity type (eg, N type). The gate doped region 118 can be used as a lightly doped drain (LDD) of a low voltage device (eg, a low voltage transistor). Doped region 118 may be located in well region 106 . In some embodiments, the doped region 118 may be formed after the gate 114 is formed. The method of forming the doped region 118 is, for example, ion implantation.

接下来,可在栅极112的侧壁上形成间隙壁120,且可同时在栅极114的侧壁上形成间隙壁122。间隙壁120与间隙壁122的材料例如是氧化硅,但本发明并不以此为限。间隙壁120与间隙壁122的形成方法例如是在栅极112与栅极114上共形地形成间隙壁材料层(未示出),再对间隙壁材料层进行蚀刻制作工艺。上述间隙壁材料层的形成方法例如是化学气相沉积法。上述蚀刻制作工艺例如是干式蚀刻制作工艺。Next, the spacer 120 may be formed on the sidewall of the gate 112 , and the spacer 122 may be formed on the sidewall of the gate 114 at the same time. The material of the spacer 120 and the spacer 122 is, for example, silicon oxide, but the invention is not limited thereto. The forming method of the spacer 120 and the spacer 122 is, for example, conformally forming a spacer material layer (not shown) on the gate 112 and the gate 114 , and then performing an etching process on the spacer material layer. The method for forming the spacer material layer is, for example, a chemical vapor deposition method. The aforementioned etching process is, for example, a dry etching process.

再者,可在介电层108、栅极112的侧壁、介电层110与栅极114的侧壁上形成间隙壁层124。间隙壁层124可暴露出栅极112的顶面与栅极114的顶面。此外,间隙壁层124可覆盖间隙壁120的侧壁与间隙壁122的侧壁。间隙壁层124的材料例如是氮化硅,但本发明并不以此为限。间隙壁层124的形成方法例如是在栅极112与栅极114上共形地形成间隙壁材料层(未示出),再通过光刻制作工艺与蚀刻制作工艺对间隙壁材料层进行图案化。上述间隙壁材料层的形成方法例如是化学气相沉积法。上述蚀刻制作工艺例如是干式蚀刻制作工艺。Furthermore, the spacer layer 124 can be formed on the dielectric layer 108 , the sidewalls of the gate 112 , the dielectric layer 110 and the sidewalls of the gate 114 . The spacer layer 124 can expose the top surface of the gate 112 and the top surface of the gate 114 . In addition, the spacer layer 124 can cover the sidewalls of the spacer 120 and the sidewalls of the spacer 122 . The material of the spacer layer 124 is, for example, silicon nitride, but the invention is not limited thereto. The formation method of the spacer layer 124 is, for example, to conformally form a spacer material layer (not shown) on the gate 112 and the gate 114, and then pattern the spacer material layer through a photolithography process and an etching process. . The method for forming the spacer material layer is, for example, a chemical vapor deposition method. The aforementioned etching process is, for example, a dry etching process.

随后,可在栅极112与栅极114上共形地形成间隙壁材料层126。在一些实施例中,间隙壁材料层126可覆盖栅极112、栅极114、间隙壁120、间隙壁122与间隙壁层124。间隙壁材料层126的材料例如是氧化硅,但本发明并不以此为限。间隙壁材料层126的形成方法例如是化学气相沉积法。Subsequently, a spacer material layer 126 may be conformally formed on the gates 112 and 114 . In some embodiments, the spacer material layer 126 can cover the gate 112 , the gate 114 , the spacer 120 , the spacer 122 and the spacer layer 124 . The material of the spacer material layer 126 is, for example, silicon oxide, but the invention is not limited thereto. The formation method of the spacer material layer 126 is, for example, chemical vapor deposition.

请参照图1B,可对间隙壁材料层126进行蚀刻制作工艺。由此,在栅极112的侧壁上形成间隙壁128,且同时在栅极114的侧壁上形成间隙壁130。在对间隙壁材料层126进行蚀刻制作工艺时,可利用间隙壁层124作为蚀刻终止层。在一些实施例中,间隙壁128可位于第一区R1中的间隙壁层124上,且间隙壁130可位于第二区R2中的间隙壁层124上。对间隙壁材料层126所进行的蚀刻制作工艺例如是干式蚀刻制作工艺。Referring to FIG. 1B , an etching process may be performed on the spacer material layer 126 . Thus, the spacer 128 is formed on the sidewall of the gate 112 , and the spacer 130 is formed on the sidewall of the gate 114 at the same time. When performing an etching process on the spacer material layer 126 , the spacer layer 124 can be used as an etching stop layer. In some embodiments, the spacer 128 may be located on the spacer layer 124 in the first region R1, and the spacer 130 may be located on the spacer layer 124 in the second region R2. The etching process performed on the spacer material layer 126 is, for example, a dry etching process.

请参照图1C,在第一区R1中形成图案化光致抗蚀剂层132。图案化光致抗蚀剂层132覆盖间隙壁128且暴露出间隙壁130。在一些实施例中,图案化光致抗蚀剂层132还可覆盖第一区R1中的栅极112、间隙壁120与间隙壁层124。在一些实施例中,图案化光致抗蚀剂层132还可暴露出第二区R2中的栅极114、间隙壁122与间隙壁层124。图案化光致抗蚀剂层132可通过光刻制作工艺来形成。Referring to FIG. 1C, a patterned photoresist layer 132 is formed in the first region R1. The patterned photoresist layer 132 covers the spacer 128 and exposes the spacer 130 . In some embodiments, the patterned photoresist layer 132 can also cover the gate 112 , the spacer 120 and the spacer layer 124 in the first region R1 . In some embodiments, the patterned photoresist layer 132 can also expose the gate 114 , the spacer 122 and the spacer layer 124 in the second region R2 . The patterned photoresist layer 132 can be formed by a photolithography process.

请参照图1D,利用图案化光致抗蚀剂层132作为掩模,移除间隙壁130。间隙壁130的移除方法例如是湿式蚀刻法、干式蚀刻法或其组合。Referring to FIG. 1D , using the patterned photoresist layer 132 as a mask, the spacers 130 are removed. The removal method of the spacer 130 is, for example, a wet etching method, a dry etching method or a combination thereof.

请参照图1E,可在移除间隙壁130之后,移除图案化光致抗蚀剂层132。图案化光致抗蚀剂层132的移除方法例如是干式剥离法(dry stripping)或湿式剥离法(wetstripping)。Referring to FIG. 1E , the patterned photoresist layer 132 may be removed after the spacer 130 is removed. The removal method of the patterned photoresist layer 132 is, for example, dry stripping or wet stripping.

接着,可在栅极112与栅极114上共形地形成间隙壁材料层134。在一些实施例中,间隙壁材料层134可覆盖栅极112、栅极114、间隙壁120、间隙壁122、间隙壁层124与间隙壁128。间隙壁材料层134的材料例如是氧化硅,但本发明并不以此为限。间隙壁材料层134的形成方法例如是化学气相沉积法。Next, a spacer material layer 134 may be conformally formed on the gate 112 and the gate 114 . In some embodiments, the spacer material layer 134 may cover the gate 112 , the gate 114 , the spacer 120 , the spacer 122 , the spacer layer 124 and the spacer 128 . The material of the spacer material layer 134 is, for example, silicon oxide, but the invention is not limited thereto. The formation method of the spacer material layer 134 is, for example, chemical vapor deposition.

请参照图1F,对间隙壁材料层134进行蚀刻制作工艺。由此,在间隙壁128的侧壁上形成间隙壁136,且同时在栅极114的侧壁上形成间隙壁138。在对间隙壁材料层134进行蚀刻制作工艺时,可利用间隙壁层124作为蚀刻终止层。在一些实施例中,间隙壁136可位于第一区R1中的间隙壁层124上,且间隙壁138可位于第二区R2中的间隙壁层124上。对间隙壁材料层134所进行的蚀刻制作工艺例如是干式蚀刻制作工艺。Referring to FIG. 1F , an etching process is performed on the spacer material layer 134 . Thus, the spacer 136 is formed on the sidewall of the spacer 128 , and the spacer 138 is formed on the sidewall of the gate 114 at the same time. When performing an etching process on the spacer material layer 134 , the spacer layer 124 can be used as an etching stop layer. In some embodiments, the spacer 136 may be located on the spacer layer 124 in the first region R1 , and the spacer 138 may be located on the spacer layer 124 in the second region R2 . The etching process performed on the spacer material layer 134 is, for example, a dry etching process.

请参照图1G,在形成间隙壁136与间隙壁138之后,可移除由间隙壁128、间隙壁136与间隙壁138所暴露出的间隙壁层124,而在间隙壁128与栅极112之间、间隙壁128与介电层108之间以及间隙壁136与介电层108之间形成间隙壁140,且在间隙壁138与栅极114之间以及间隙壁138与介电层110之间形成间隙壁142。1G, after forming the spacer 136 and the spacer 138, the spacer layer 124 exposed by the spacer 128, the spacer 136 and the spacer 138 can be removed, and between the spacer 128 and the gate 112 A spacer 140 is formed between the spacer 128 and the dielectric layer 108 and between the spacer 136 and the dielectric layer 108, and between the spacer 138 and the gate 114 and between the spacer 138 and the dielectric layer 110 Spacers 142 are formed.

在一些实施例中,可在第一区R1的基底100中形成掺杂区144。掺杂区144可具有第二导电型(如,N型)。掺杂区144可作为高压元件(如,高压晶体管)的源极区或漏极区。此外,掺杂区144可位于间隙壁136的一侧的基底100中。另外,掺杂区144可位于掺杂区116中。掺杂区144的形成方法例如是离子注入法。In some embodiments, a doped region 144 may be formed in the substrate 100 of the first region R1. The doped region 144 may have a second conductivity type (eg, N type). The doped region 144 can serve as a source region or a drain region of a high voltage device (eg, a high voltage transistor). In addition, the doped region 144 may be located in the substrate 100 on one side of the spacer 136 . In addition, doped region 144 may be located in doped region 116 . The method of forming the doped region 144 is, for example, ion implantation.

在一些实施例中,可在第二区R2的基底100中形成掺杂区146。掺杂区146可具有第二导电型(如,N型)。掺杂区146可作为低压元件(如,低压晶体管)的源极区或漏极区。此外,掺杂区146可位于间隙壁138的一侧的基底100中。另外,掺杂区146可位于阱区106中。掺杂区146的形成方法例如是离子注入法。在一些实施例中,可先形成第二区R2中的掺杂区146,再形成第一区R1中的掺杂区144。In some embodiments, a doped region 146 may be formed in the substrate 100 of the second region R2. The doped region 146 can have a second conductivity type (eg, N type). The doped region 146 can serve as a source region or a drain region of a low voltage device (eg, a low voltage transistor). In addition, the doped region 146 may be located in the substrate 100 on one side of the spacer 138 . Additionally, the doped region 146 may be located in the well region 106 . The method of forming the doped region 146 is, for example, ion implantation. In some embodiments, the doped region 146 in the second region R2 may be formed first, and then the doped region 144 in the first region R1 may be formed.

基于上述实施例可知,在半导体结构10的制造方法中,在第一区R1的栅极112的侧壁上形成间隙壁128与间隙壁136,且在第二区R2的栅极114的侧壁上形成间隙壁138。因此,可形成第一区R1的半导体元件(如,高压元件)所需的间隙壁结构与第二区R2的半导体元件(如,低压元件)所需的间隙壁结构,由此可提升第一区R1的半导体元件(如,高压元件)与第二区R2的半导体元件(如,低压元件)的电性表现。此外,通过调整第一区R1中的间隙壁128与间隙壁136以及第二区R2中的间隙壁138的尺寸,可弹性地调整第一区R1的半导体元件(如,高压元件)与第二区R2的半导体元件(如,低压元件)的电性表现。Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the semiconductor structure 10, the spacer 128 and the spacer 136 are formed on the sidewall of the gate 112 in the first region R1, and the sidewall of the gate 114 in the second region R2 A spacer wall 138 is formed thereon. Therefore, the spacer structure required by the semiconductor elements (such as high-voltage elements) in the first region R1 and the spacer structure required by the semiconductor elements (such as low-voltage elements) in the second region R2 can be formed, thereby improving the first Electrical properties of the semiconductor elements (eg, high-voltage elements) in the region R1 and the semiconductor elements (eg, low-voltage elements) in the second region R2 . In addition, by adjusting the size of the spacer 128 and the spacer 136 in the first region R1 and the size of the spacer 138 in the second region R2, the semiconductor elements (such as high voltage elements) and the second region of the first region R1 can be elastically adjusted. The electrical performance of the semiconductor components (eg, low-voltage components) in the region R2.

在上述实施例中,上述实施例的半导体结构10的制造方法是以制作高压元件(如,高压晶体管)与低压元件(如,低压晶体管)为例,且但本发明并不以此为限。在另一些实施例中,上述实施例的半导体结构10的制造方法更可应用于包括高压元件(如,高压晶体管)、中压元件(如,中压晶体管)与低压元件(如,低压晶体管)的半导体结构的制作工艺中,于此省略其说明。由此,高压元件、中压元件与低压元件可分别具有所需的间隙壁结构。In the above-mentioned embodiments, the manufacturing method of the semiconductor structure 10 in the above-mentioned embodiments is exemplified by manufacturing high-voltage devices (eg, high-voltage transistors) and low-voltage devices (eg, low-voltage transistors), and the present invention is not limited thereto. In some other embodiments, the manufacturing method of the semiconductor structure 10 of the above-mentioned embodiments can be further applied to components including high-voltage components (such as high-voltage transistors), medium-voltage components (such as medium-voltage transistors) and low-voltage components (such as low-voltage transistors) In the manufacturing process of the semiconductor structure, the description thereof is omitted here. Therefore, the high-voltage component, the medium-voltage component and the low-voltage component can respectively have required spacer structures.

综上所述,通过上述实施例的半导体结构的制造方法,可形成不同半导体元件所需的间隙壁结构,由此可提升半导体元件的电性表现,且可弹性地调整半导体元件的电性表现。To sum up, through the manufacturing method of the semiconductor structure of the above embodiment, the spacer structure required by different semiconductor elements can be formed, thereby improving the electrical performance of the semiconductor element, and can flexibly adjust the electrical performance of the semiconductor element .

虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1.一种半导体结构的制造方法,包括:1. A method of manufacturing a semiconductor structure, comprising: 提供基底,其中所述基底包括第一区与第二区;providing a substrate, wherein the substrate includes a first region and a second region; 在所述第一区中的所述基底上形成第一介电层;forming a first dielectric layer on the substrate in the first region; 在所述第二区中的所述基底上形成第二介电层;forming a second dielectric layer on the substrate in the second region; 在所述第一区中的所述第一介电层上形成第一栅极;forming a first gate on the first dielectric layer in the first region; 在所述第二区中的所述第二介电层上形成第二栅极;forming a second gate on the second dielectric layer in the second region; 在所述第一栅极的侧壁上形成第一间隙壁,且同时在所述第二栅极的侧壁上形成第二间隙壁;forming a first spacer on a sidewall of the first gate, and simultaneously forming a second spacer on a sidewall of the second gate; 在所述第一区中形成图案化光致抗蚀剂层,其中所述图案化光致抗蚀剂层覆盖所述第一间隙壁且暴露出所述第二间隙壁;forming a patterned photoresist layer in the first region, wherein the patterned photoresist layer covers the first spacer and exposes the second spacer; 利用所述图案化光致抗蚀剂层作为掩模,移除所述第二间隙壁;removing the second spacer by using the patterned photoresist layer as a mask; 在移除所述第二间隙壁之后,移除所述图案化光致抗蚀剂层;以及removing the patterned photoresist layer after removing the second spacer; and 在所述第一间隙壁的侧壁上形成第三间隙壁,且同时在所述第二栅极的侧壁上形成第四间隙壁。A third spacer is formed on a sidewall of the first spacer, and a fourth spacer is formed on a sidewall of the second gate at the same time. 2.如权利要求1所述的半导体结构的制造方法,其中同时形成所述第一间隙壁与所述第二间隙壁的方法包括:2. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for simultaneously forming the first spacer and the second spacer comprises: 在所述第一栅极与所述第二栅极上共形地形成间隙壁材料层;以及conformally forming a layer of spacer material on the first gate and the second gate; and 对所述间隙壁材料层进行蚀刻制作工艺。An etching process is performed on the spacer material layer. 3.如权利要求2所述的半导体结构的制造方法,其中所述蚀刻制作工艺包括干式蚀刻制作工艺。3. The method of manufacturing a semiconductor structure according to claim 2, wherein the etching process comprises a dry etching process. 4.如权利要求1所述的半导体结构的制造方法,其中所述第二间隙壁的移除方法包括湿式蚀刻法、干式蚀刻法或其组合。4. The method of manufacturing the semiconductor structure as claimed in claim 1, wherein the method for removing the second spacer comprises a wet etching method, a dry etching method or a combination thereof. 5.如权利要求1所述的半导体结构的制造方法,其中同时形成所述第三间隙壁与所述第四间隙壁的方法包括:5. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for simultaneously forming the third spacer and the fourth spacer comprises: 在所述第一栅极与所述第二栅极上共形地形成间隙壁材料层;以及conformally forming a layer of spacer material on the first gate and the second gate; and 对所述间隙壁材料层进行蚀刻制作工艺。An etching process is performed on the spacer material layer. 6.如权利要求5所述的半导体结构的制造方法,其中所述蚀刻制作工艺包括干式蚀刻制作工艺。6. The method of manufacturing a semiconductor structure as claimed in claim 5, wherein the etching process comprises a dry etching process. 7.如权利要求1所述的半导体结构的制造方法,还包括:7. The manufacturing method of the semiconductor structure as claimed in claim 1, further comprising: 在形成所述第一间隙壁与所述第二间隙壁之前,在所述第一介电层、所述第一栅极的侧壁、所述第二介电层与所述第二栅极的侧壁上形成间隙壁层,其中所述间隙壁层暴露出所述第一栅极的顶面与所述第二栅极的顶面。Before forming the first spacer and the second spacer, the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the second gate A spacer layer is formed on the sidewall of the grid, wherein the spacer layer exposes the top surface of the first gate and the top surface of the second gate. 8.如权利要求7所述的半导体结构的制造方法,还包括:8. The manufacturing method of the semiconductor structure as claimed in claim 7, further comprising: 在形成所述第三间隙壁与所述第四间隙壁之后,移除由所述第一间隙壁、所述第三间隙壁与所述第四间隙壁所暴露出的所述间隙壁层,而在所述第一间隙壁与所述第一栅极之间、所述第一间隙壁与所述第一介电层之间以及所述第三间隙壁与所述第一介电层之间形成第五间隙壁,且在所述第四间隙壁与所述第二栅极之间以及所述第四间隙壁与所述第二介电层之间形成第六间隙壁。After forming the third spacer and the fourth spacer, removing the spacer layer exposed by the first spacer, the third spacer and the fourth spacer, Between the first spacer and the first gate, between the first spacer and the first dielectric layer, and between the third spacer and the first dielectric layer A fifth spacer is formed between the fourth spacer and the second gate, and a sixth spacer is formed between the fourth spacer and the second dielectric layer. 9.如权利要求7所述的半导体结构的制造方法,还包括:9. The method for manufacturing a semiconductor structure as claimed in claim 7, further comprising: 在形成所述间隙壁层之前,在所述第一栅极的侧壁上形成第五间隙壁,且同时在所述第二栅极的侧壁上形成第六间隙壁。Before forming the spacer layer, a fifth spacer is formed on the sidewall of the first gate, and a sixth spacer is formed on the sidewall of the second gate at the same time. 10.如权利要求1所述的半导体结构的制造方法,其中所述第一区包括高压元件区,且所述第二区包括低压元件区。10. The method of manufacturing a semiconductor structure according to claim 1, wherein the first region comprises a high-voltage device region, and the second region comprises a low-voltage device region.
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