CN115732412A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN115732412A CN115732412A CN202111180868.0A CN202111180868A CN115732412A CN 115732412 A CN115732412 A CN 115732412A CN 202111180868 A CN202111180868 A CN 202111180868A CN 115732412 A CN115732412 A CN 115732412A
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Abstract
The invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps. A substrate is provided. The substrate includes a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer. A second gate is formed on the second dielectric layer. A first spacer is formed on a sidewall of the first gate and a second spacer is simultaneously formed on a sidewall of the second gate. A patterned photoresist layer is formed. The patterned photoresist layer covers the first spacer and exposes the second spacer. The second spacer is removed using the patterned photoresist layer as a mask. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is simultaneously formed on the sidewall of the second gate.
Description
Technical Field
The present invention relates to semiconductor fabrication processes, and more particularly, to a method for fabricating a semiconductor structure.
Background
With the progress of semiconductor fabrication technology, the semiconductor industry continues to shrink the size of semiconductor devices. Therefore, in a semiconductor structure having both low voltage devices and high voltage devices, the engineering of spacers between different semiconductor devices will be challenging. For example, when the low voltage device and the high voltage device have spacers with smaller sizes, the high voltage device has higher leakage current, thereby reducing the electrical performance of the high voltage device.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor structure, which can effectively improve the electrical performance of semiconductor elements in different element areas.
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps. A substrate is provided. The substrate includes a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A second dielectric layer is formed on the substrate in the second region. A first gate is formed on the first dielectric layer in the first region. A second gate is formed on the second dielectric layer in the second region. A first spacer is formed on a sidewall of the first gate and a second spacer is simultaneously formed on a sidewall of the second gate. A patterned photoresist layer is formed in the first region. The patterned photoresist layer covers the first spacer and exposes the second spacer. The second spacer is removed using the patterned photoresist layer as a mask. After removing the second spacer, the patterned photoresist layer is removed. A third spacer is formed on the sidewall of the first spacer, and a fourth spacer is simultaneously formed on the sidewall of the second gate.
In the method for fabricating a semiconductor structure according to an embodiment of the present invention, the method for simultaneously forming the first spacer and the second spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. And carrying out an etching manufacturing process on the spacer material layer.
According to an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the etching process is, for example, a dry etching process.
According to an embodiment of the present invention, in the method for manufacturing a semiconductor structure, a method for removing the second spacer includes a wet etching method, a dry etching method or a combination thereof.
According to an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the method for simultaneously forming the third spacer and the fourth spacer may include the following steps. A spacer material layer is conformally formed on the first gate and the second gate. And carrying out an etching manufacturing process on the spacer material layer.
According to an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the etching process is, for example, a dry etching process.
According to an embodiment of the present invention, the method for manufacturing a semiconductor structure may further include the following steps. Before forming the first spacer and the second spacer, a spacer layer is formed on the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the sidewall of the second gate. The spacer layer may expose a top surface of the first gate and a top surface of the second gate.
According to an embodiment of the present invention, the method for manufacturing a semiconductor structure may further include the following steps. After the third spacer and the fourth spacer are formed, the spacer exposed by the first spacer, the third spacer and the fourth spacer can be removed, and a fifth spacer is formed between the first spacer and the first gate, between the first spacer and the first dielectric layer and between the third spacer and the first dielectric layer, and a sixth spacer is formed between the fourth spacer and the second gate and between the fourth spacer and the second dielectric layer.
According to an embodiment of the present invention, the method for manufacturing a semiconductor structure may further include the following steps. Before forming the spacer layer, fifth spacers may be formed on sidewalls of the first gate electrode, and sixth spacers may be simultaneously formed on sidewalls of the second gate electrode.
According to an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the first region may be a high voltage device region, and the second region may be a low voltage device region.
In view of the above, in the method for manufacturing a semiconductor structure provided by the present invention, the first spacer and the third spacer are formed on the sidewall of the first gate in the first region, and the fourth spacer is formed on the sidewall of the second gate in the second region. Therefore, the spacer structure required by the semiconductor element in the first area and the spacer structure required by the semiconductor element in the second area can be formed, and therefore the electrical performance of the semiconductor element in the first area and the semiconductor element in the second area can be improved. In addition, the electrical performance of the semiconductor element in the first area and the semiconductor element in the second area can be flexibly adjusted by adjusting the sizes of the first gap wall and the third gap wall in the first area and the fourth gap wall in the second area.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1G are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention.
Description of the symbols
10 semiconductor structure
100 base
102 isolation structure
104,106 well regions
108,110 dielectric layer
112,114: gate
116,118,144,146 doped region
120,122,128,130,136,138,140,142 spacer
124 spacer layer
126,134 spacer material layer
132 patterned photoresist layer
R1 is the first region
R2 is the second region
Detailed Description
Fig. 1A to 1G are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present invention.
A method for fabricating a semiconductor structure includes the following steps. A substrate 100 is provided. The substrate 100 includes a first region R1 and a second region R2. In some embodiments, the first region R1 may be a high voltage device region (e.g., a high voltage transistor region), and the second region R2 may be a low voltage device region (e.g., a low voltage transistor region). The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 may be a Shallow Trench Isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide.
In some embodiments, a well region 104 may be formed in the substrate 100 in the first region R1. In some embodiments, a well region 106 may be formed in the substrate 100 in the second region R2. Well 104 and well 106 can have a first conductivity type (e.g., P-type). Herein, the first conductivity type and the second conductivity type are different conductivity types. That is, the first and second conductivity types may be one and the other of the P-type conductivity and the N-type conductivity, respectively. In the present embodiment, the first conductive type is a P-type conductive type, and the second conductive type is an N-type conductive type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be an N-type conductivity and the second conductivity type may be a P-type conductivity.
Next, a dielectric layer 108 is formed on the substrate 100 in the first region R1. The material of the dielectric layer 108 is, for example, silicon oxide. The dielectric layer 108 is formed by, for example, thermal oxidation. In addition, a dielectric layer 110 is formed on the substrate 100 in the first region R2. The material of the dielectric layer 110 is, for example, silicon oxide. The dielectric layer 110 is formed by, for example, thermal oxidation. In some embodiments, dielectric layer 108 may be formed first, followed by dielectric layer 110.
Then, a gate electrode 112 is formed on the dielectric layer 108 in the first region R1. The material of the gate 112 is, for example, doped polysilicon. In addition, a gate electrode 114 is formed on the dielectric layer 110 in the second region R2. The material of the gate 114 is, for example, doped polysilicon. In some embodiments, the gate 112 and the gate 114 can be formed simultaneously by the same process, but the invention is not limited thereto.
In some embodiments, doped regions 116 may be formed in the substrate 100. The doped region 116 may have a second conductivity type (e.g., N-type). The doped region 116 may serve as an offset region (drift region) for a high voltage device (e.g., a high voltage transistor). Doped region 116 may be located in well region 104. The gate 112 may be located between the doped regions 116, and the gate 112 may be located directly over a portion of the doped regions 116. In some embodiments, the doped region 116 may be formed prior to forming the gate 112. The doped region 116 is formed by ion implantation, for example.
In some embodiments, doped regions 118 may be formed in the substrate 100 on both sides of the gate 114. The doped region 118 can have a second conductivity type (e.g., N-type). The gate doped region 118 may serve as a Lightly Doped Drain (LDD) for low voltage devices (e.g., low voltage transistors). Doped region 118 may be located in well region 106. In some embodiments, the doped region 118 may be formed after the gate 114 is formed. The doped region 118 is formed by ion implantation, for example.
Next, spacers 120 may be formed on sidewalls of the gate 112, and spacers 122 may be simultaneously formed on sidewalls of the gate 114. The material of the spacers 120 and 122 is, for example, silicon oxide, but the invention is not limited thereto. The spacers 120 and 122 are formed by, for example, conformally forming a spacer material layer (not shown) on the gates 112 and 114, and then performing an etching process on the spacer material layer. The spacer material layer is formed by, for example, chemical vapor deposition. The etching process is, for example, a dry etching process.
Furthermore, a spacer layer 124 may be formed on the sidewalls of the dielectric layer 108, the gate 112, the dielectric layer 110 and the gate 114. The spacer layer 124 may expose the top surfaces of the gate 112 and the gate 114. In addition, the spacer layer 124 may cover the sidewalls of the spacers 120 and the sidewalls of the spacers 122. The material of the spacer layer 124 is, for example, silicon nitride, but the invention is not limited thereto. The spacer layer 124 is formed by, for example, conformally forming a spacer material layer (not shown) on the gate 112 and the gate 114, and then patterning the spacer material layer by a photolithography process and an etching process. The spacer material layer is formed by, for example, chemical vapor deposition. The etching process is, for example, a dry etching process.
Subsequently, a spacer material layer 126 may be conformally formed on the gate 112 and the gate 114. In some embodiments, the spacer material layer 126 may cover the gate 112, the gate 114, the spacers 120, the spacers 122, and the spacer layer 124. The material of the spacer material layer 126 is, for example, silicon oxide, but the invention is not limited thereto. The spacer material layer 126 is formed by, for example, chemical vapor deposition.
Referring to fig. 1B, an etching process may be performed on the spacer material layer 126. Thus, spacers 128 are formed on the sidewalls of gate 112, and spacers 130 are formed on the sidewalls of gate 114 at the same time. The spacer layer 124 may be utilized as an etch stop layer during the etching process for the spacer material layer 126. In some embodiments, the spacers 128 may be located on the spacer layer 124 in the first region R1, and the spacers 130 may be located on the spacer layer 124 in the second region R2. The spacer material layer 126 is etched by a dry etching process, for example.
Referring to fig. 1C, a patterned photoresist layer 132 is formed in the first region R1. The patterned photoresist layer 132 covers the spacers 128 and exposes the spacers 130. In some embodiments, the patterned photoresist layer 132 may also cover the gate 112, the spacers 120 and the spacer layer 124 in the first region R1. In some embodiments, the patterned photoresist layer 132 may also expose the gate 114, the spacers 122 and the spacer layer 124 in the second region R2. The patterned photoresist layer 132 may be formed by a photolithography process.
Referring to fig. 1D, the spacers 130 are removed using the patterned photoresist layer 132 as a mask. The spacer 130 is removed by, for example, wet etching, dry etching or a combination thereof.
Referring to fig. 1E, the patterned photoresist layer 132 may be removed after the spacers 130 are removed. The patterned photoresist layer 132 is removed by, for example, a dry stripping method (dry stripping) or a wet stripping method (wet stripping).
Next, a spacer material layer 134 may be conformally formed on the gate 112 and the gate 114. In some embodiments, the spacer material layer 134 may cover the gate 112, the gate 114, the spacers 120, the spacers 122, the spacer layer 124, and the spacers 128. The material of the spacer material layer 134 is, for example, silicon oxide, but the invention is not limited thereto. The spacer material layer 134 is formed by, for example, chemical vapor deposition.
Referring to fig. 1F, an etching process is performed on the spacer material layer 134. Thus, spacers 136 are formed on the sidewalls of spacers 128, and spacers 138 are formed on the sidewalls of gate 114 at the same time. The spacer layer 124 may be utilized as an etch stop layer during the etching process for the spacer material layer 134. In some embodiments, the spacer 136 may be located on the spacer layer 124 in the first region R1, and the spacer 138 may be located on the spacer layer 124 in the second region R2. The spacer material layer 134 is etched by a dry etching process, for example.
Referring to fig. 1G, after forming the spacers 136 and 138, the spacer layer 124 exposed by the spacers 128, 136 and 138 can be removed, spacers 140 are formed between the spacers 128 and the gate 112, between the spacers 128 and the dielectric layer 108, and between the spacers 136 and the dielectric layer 108, and spacers 142 are formed between the spacers 138 and the gate 114, and between the spacers 138 and the dielectric layer 110.
In some embodiments, the doped region 144 may be formed in the substrate 100 of the first region R1. The doped region 144 may have a second conductivity type (e.g., N-type). The doped region 144 may serve as a source region or a drain region of a high voltage device (e.g., a high voltage transistor). In addition, the doped region 144 may be located in the substrate 100 at one side of the spacer 136. In addition, the doped region 144 may be located in the doped region 116. The doped region 144 is formed by ion implantation, for example.
In some embodiments, the doped region 146 may be formed in the substrate 100 of the second region R2. The doped region 146 may have a second conductivity type (e.g., N-type). The doped region 146 may serve as a source region or a drain region for low voltage devices (e.g., low voltage transistors). In addition, the doped region 146 may be located in the substrate 100 on one side of the spacer 138. In addition, doped region 146 may be located in well region 106. The doped region 146 may be formed by ion implantation, for example. In some embodiments, the doped region 146 in the second region R2 may be formed first, and then the doped region 144 in the first region R1 may be formed.
Based on the above embodiments, in the manufacturing method of the semiconductor structure 10, the spacers 128 and 136 are formed on the sidewalls of the gate 112 in the first region R1, and the spacer 138 is formed on the sidewalls of the gate 114 in the second region R2. Therefore, the spacer structure required for the semiconductor devices (e.g., high voltage devices) in the first region R1 and the spacer structure required for the semiconductor devices (e.g., low voltage devices) in the second region R2 can be formed, thereby improving the electrical performance of the semiconductor devices (e.g., high voltage devices) in the first region R1 and the semiconductor devices (e.g., low voltage devices) in the second region R2. In addition, by adjusting the sizes of the spacers 128 and 136 in the first region R1 and the spacers 138 in the second region R2, the electrical performance of the semiconductor devices (e.g., high voltage devices) in the first region R1 and the semiconductor devices (e.g., low voltage devices) in the second region R2 can be flexibly adjusted.
In the above embodiments, the manufacturing method of the semiconductor structure 10 of the above embodiments is exemplified by manufacturing a high voltage device (e.g., a high voltage transistor) and a low voltage device (e.g., a low voltage transistor), and the invention is not limited thereto. In other embodiments, the method for manufacturing the semiconductor structure 10 of the above embodiments can be further applied to a manufacturing process of a semiconductor structure including a high voltage device (e.g., a high voltage transistor), a medium voltage device (e.g., a medium voltage transistor) and a low voltage device (e.g., a low voltage transistor), and the description thereof is omitted here. Thus, the high voltage element, the medium voltage element and the low voltage element can respectively have the required spacer structure.
In summary, by the method for manufacturing a semiconductor structure according to the above embodiments, the spacer structures required by different semiconductor devices can be formed, so that the electrical performance of the semiconductor device can be improved, and the electrical performance of the semiconductor device can be flexibly adjusted.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region;
forming a first dielectric layer on the substrate in the first region;
forming a second dielectric layer on the substrate in the second region;
forming a first gate on the first dielectric layer in the first region;
forming a second gate on the second dielectric layer in the second region;
forming a first spacer on a sidewall of the first gate and simultaneously forming a second spacer on a sidewall of the second gate;
forming a patterned photoresist layer in the first region, wherein the patterned photoresist layer covers the first spacer and exposes the second spacer;
removing the second spacer using the patterned photoresist layer as a mask;
removing the patterned photoresist layer after removing the second spacer; and
forming a third spacer on a sidewall of the first spacer and simultaneously forming a fourth spacer on a sidewall of the second gate.
2. The method of claim 1, wherein the step of simultaneously forming the first and second spacers comprises:
forming a spacer material layer conformally on the first gate and the second gate; and
and carrying out an etching manufacturing process on the spacer material layer.
3. The method of claim 2, wherein said etch process comprises a dry etch process.
4. The method according to claim 1, wherein the second spacer is removed by wet etching, dry etching or a combination thereof.
5. The method of claim 1, wherein the step of simultaneously forming the third spacer and the fourth spacer comprises:
conformally forming a spacer material layer on the first gate and the second gate; and
and carrying out an etching manufacturing process on the spacer material layer.
6. The method of claim 5, wherein said etch process comprises a dry etch process.
7. The method of fabricating a semiconductor structure according to claim 1, further comprising:
forming a spacer layer on the first dielectric layer, the sidewall of the first gate, the second dielectric layer and the sidewall of the second gate before forming the first spacer and the second spacer, wherein the spacer layer exposes the top surface of the first gate and the top surface of the second gate.
8. The method of fabricating a semiconductor structure according to claim 7, further comprising:
after forming the third and fourth spacers, removing the spacer layer exposed by the first, third and fourth spacers, forming fifth spacers between the first spacer and the first gate, between the first spacer and the first dielectric layer and between the third spacer and the first dielectric layer, and forming sixth spacers between the fourth spacer and the second gate and between the fourth spacer and the second dielectric layer.
9. The method of fabricating a semiconductor structure according to claim 7, further comprising:
forming a fifth spacer on a sidewall of the first gate and simultaneously forming a sixth spacer on a sidewall of the second gate before forming the spacer layer.
10. The method of claim 1, wherein the first region comprises a high voltage device region and the second region comprises a low voltage device region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110132668A TW202312351A (en) | 2021-09-02 | 2021-09-02 | Method of manufacturing semiconductor structure |
| TW110132668 | 2021-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115732412A true CN115732412A (en) | 2023-03-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111180868.0A Pending CN115732412A (en) | 2021-09-02 | 2021-10-11 | Method for manufacturing semiconductor structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115732412A (en) |
| TW (1) | TW202312351A (en) |
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2021
- 2021-09-02 TW TW110132668A patent/TW202312351A/en unknown
- 2021-10-11 CN CN202111180868.0A patent/CN115732412A/en active Pending
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| Publication number | Publication date |
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| TW202312351A (en) | 2023-03-16 |
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