CN101350307A - Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage - Google Patents
Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage Download PDFInfo
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- CN101350307A CN101350307A CNA200710137116XA CN200710137116A CN101350307A CN 101350307 A CN101350307 A CN 101350307A CN A200710137116X A CNA200710137116X A CN A200710137116XA CN 200710137116 A CN200710137116 A CN 200710137116A CN 101350307 A CN101350307 A CN 101350307A
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Abstract
The invention relates to a process for preparing a high voltage transistor with a double-diffused drain, which has the advantages that an original photosensitive resist which is used for defining a grid pattern is utilized as the photosensitive resist to define the double-diffused drain, and the complexity of the technology is not increased. The process comprises the following steps: firstly, orderly forming a dielectric layer and a conductive layer on a substrate, then forming a patterned photosensitive resist on the conductive layer, wherein the conductive layer and the dielectric layer are etched through taking the photosensitive resist as an etching mask, and forming a grid electrode and a grid dielectric layer on the substrate, after steadying the structure of the photosensitive resist, carrying out the first ion doping technology, and respectively forming depth light doping areas in the substrates on both sides of the grid electrode, removing the photosensitive resist, and forming two interstitial walls on the side walls of the grid electrode, then carrying out the second ion doping technology, and respectively forming heavy doping areas in the substrates which are arranged on the outer sides of the interstitial walls. The invention relates to a low voltage transistor and a process for integrally preparing the high voltage transistor with the double diffusing drain.
Description
Technical field
The present invention relates to a kind of manufacture method of high voltage transistor and the integrated manufacture method of low pressure and high voltage transistor, and particularly have a double-diffused drain electrode (double-diffused drain relevant for a kind of; The manufacture method of high voltage transistor DDD) and low voltage transistor and have the integrated manufacture method of the high voltage transistor of double-diffused drain electrode.
Background technology
In general, have the high voltage transistor of double-diffused drain electrode, most likely use metal silicide to make its grid and source/drain if want to restrain oneself high pressure and high speed operation.But, just must further increase the breakdown voltage of the knot between source/drain and substrate, so also must further increase the junction depth of the dark knot light doping section of double-diffused drain electrode.
The formation method of existing dark knot light doping section is nothing more than following three kinds of methods.First kind forms dark knot light doping section for directly utilizing polysilicon gate to carry out self-aligning energetic ion doping process, but the structure that only relies on polysilicon gate and the gate oxide under it can not stop penetrating of energetic ion and influence transistor arrangement and characteristic thereof.
Carry out self-aligning energetic ion doping process if on polysilicon gate, add one deck hard mask layer again, can protect the structure of polysilicon gate and the gate oxide under it more effectively.If but on grid, form metal silicide layer, then must remove the hard mask layer on the polysilicon gate earlier.Because the material of hard mask layer mostly is silica or silicon nitride, regular meeting causes the damage to shallow slot isolation structure when removing hard mask layer, and influences the running of integrated circuit.
If carry out the energetic ion doping process with other mask layer earlier, form gate oxide and polysilicon gate again.Then whether the critical size that tolerable alignment error will have influence on semiconductor technology between mask layer and the polysilicon gate can further dwindle.
Summary of the invention
Therefore one of purpose of the present invention just provides a kind of manufacture method with high voltage transistor of double-diffused drain electrode, to integrate easily with low voltage transistor technology.
According to one embodiment of the invention, on substrate, form earlier dielectric layer and conductive layer in regular turn, on conductive layer, form the photoresist of patterning then.With the photoresist is that etching mask comes etching conductive layer and dielectric layer, to form grid and gate dielectric layer on substrate.Stablize after the structure of photoresist, carry out the first ion doping technology, in the substrate of grid both sides, to form dark knot light doping section respectively.Remove above-mentioned photoresist, form the sidewall of two clearance walls again in grid.Then, carry out the second ion doping technology, in the substrate in the clearance wall outside, to form heavily doped region respectively.Wherein, the ion doping energy of the second ion doping technology is less than the ion doping energy of the first ion doping technology, and the ion doping concentration of light doping section is less than the ion doping concentration of heavily doped region.
According to another embodiment of the present invention, on substrate, form dielectric layer and conductive layer in regular turn earlier with low voltage component district and high voltage device district, on conductive layer, form a plurality of first photoresists of patterning then.With first photoresist is that etching mask comes etching conductive layer and dielectric layer, forms the first/second grid and the first/the second gate dielectric layer respectively to form on the substrate in low voltage component district and high voltage device district.Stablize after the structure of photoresist, second photoresist that forms patterning is covered on the low voltage component district, carries out the first ion doping technology again, to form dark knot light doping section respectively in the substrate of second grid both sides.Remove second photoresist, carry out the second ion doping technology again, in the substrate of first grid both sides, to form lightly doped drain respectively.Remove first photoresist, on the sidewall of first and second grid, form clearance wall then.Carry out the 3rd ion doping technology again, in the substrate of the outside of clearance wall, to form source/drain.
According to the present invention, utilize original photoresist of definition grid to be used as the ion doping mask, in the substrate of high voltage device grid both sides, form the light doping section of dark knot, can protect the structure of grid and gate dielectric layer effectively.In addition, follow-up can also be like a cork with the mode that removes of general photoresist with photoresist remove and can not damage shallow slot isolation structure, therefore can be like a cork and the metal silicide process integration.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of accompanying drawing:
Figure 1A-1D is a kind of manufacturing process generalized section with high voltage transistor of double-diffused drain electrode that illustrates according to one embodiment of the present invention.
Description of reference numerals
100: substrate 105: the low voltage component district
110: high voltage device district 115: shallow slot isolation structure
120a, 120b: gate dielectric layer 125a, 125b: grid
130a, 130b: 135: the second photoresists of first photoresist
140: the first ion doping technology 145: tie light doping section deeply
150: the second ion doping technology 155: lightly doped drain
160: 165: the three ion doping technology of clearance wall
170a, 170b: source/drain
Embodiment
Please refer to Figure 1A-1D, it illustrates a kind of manufacturing process generalized section with high voltage transistor of double-diffused drain electrode according to one embodiment of the present invention.
In Figure 1A, on substrate 100, have low voltage component district 105 and high voltage device district 110, define active area and in substrate 100, have shallow slot isolation structure 115.On substrate 100, form earlier dielectric layer and conductive layer (for example polysilicon layer or metal silicide layer) in regular turn, on conductive layer, form the first photoresist 130a, the 130b of patterning then.With the first photoresist 130a, 130b is that etching mask comes etching conductive layer and dielectric layer in regular turn, to form grid 125a, 125b and gate dielectric layer 120a, 120b respectively in low voltage component district on substrate 100 105 and the high voltage device district 110.
Then, stablize the structure of the first photoresist 130a, 130b.According to one embodiment of the invention, the thickness of the first photoresist 130a, 130b is greater than 8000 dusts, and the method for stablizing the first photoresist structure 130a, 130b for example can use the mode of heating (200 ℃ according to appointment) or irradiating ultraviolet light to bake the first photoresist 130a, 130b firmly.
In Figure 1B, form second photoresist 135 and cover low voltage component district 105.Then high voltage device district 110 is carried out the first ion doping technology 140, in the substrate 100 of the grid 125b both sides of high voltage device, to form dark knot light doping section 145 respectively.
In Fig. 1 C, remove second photoresist 135, the comprehensive second ion doping technology 150 of carrying out is to form lightly doped drain 155 respectively in the substrate 100 of the grid 125a both sides of low voltage component.
In Fig. 1 D, remove the first photoresist 130a, 130b earlier, on the sidewall of the both sides of grid 125a, 125b, form clearance wall 160 then.Then, comprehensive the 3rd ion doping technology 165 of carrying out is to form source/ drain 170a, 170b respectively respectively in the substrate 100 of grid 125a, 125b both sides.
In each above-mentioned ion doping technology, ion doping energy the maximum is the first ion doping technology 140, and ion doping energy reckling is the second ion doping technology 150.The above-mentioned first photoresist 130a, the 130b and the removal method of second photoresist 135 comprise that oxygen plasma ashing method or wet type divest method.Follow-uply can also optionally on grid 125a, 125b and/or source/ drain 170a, 170b, form metal silicide layer, to promote transistorized operation rate.Because the formation method of metal silicide layer is well known to those skilled in the art, therefore repeat no more.
According to the above embodiments as can be known, utilize original photoresist of definition grid to be used as the ion doping mask, in the substrate of high voltage device grid both sides, form the light doping section of dark knot, can protect the structure of grid and gate dielectric layer effectively.In addition, follow-up can also be like a cork with the mode that removes of general photoresist with photoresist remove and can not damage shallow slot isolation structure, therefore can be like a cork and the metal silicide process integration.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the appending claims person of defining.
Claims (12)
1. manufacture method with high voltage transistor of double-diffused drain electrode comprises:
Form a dielectric layer and a conductive layer in regular turn on a substrate;
A photoresist that forms patterning is on this conductive layer;
This conductive layer that etch exposed goes out and under this dielectric layer, to form a grid and a gate dielectric layer on this substrate;
Stablize the structure of this photoresist;
Carry out one first ion doping technology, in this substrate of these grid both sides, to form a dark knot light doping section respectively;
Remove this photoresist;
Form the sidewall of two clearance walls in this grid; And
Carry out one second ion doping technology, in the substrate of the outside of those clearance walls, to form heavily doped region, the ion doping energy of this second ion doping technology is less than the ion doping energy of this first ion doping technology, and those tie the ion doping concentration of the ion doping concentration of light doping section less than those heavily doped regions deeply.
2. the manufacture method with high voltage transistor of double-diffused drain electrode as claimed in claim 1, the method for wherein stablizing this photoresist comprises hard roasting.
3. the manufacture method with high voltage transistor of double-diffused drain electrode as claimed in claim 1 wherein should hard roasting method comprise heating or irradiating ultraviolet light.
4. the manufacture method with high voltage transistor of double-diffused drain electrode as claimed in claim 1, wherein the thickness of this photoresist is greater than 8000 dusts.
5. the manufacture method with high voltage transistor of double-diffused drain electrode as claimed in claim 1, wherein the material of this conductive layer comprises polysilicon or metal silicide.
6. the manufacture method with high voltage transistor of double-diffused drain electrode as claimed in claim 1, the removal method of this photoresist comprises that oxygen plasma ashing method or wet type divest method.
7. low voltage transistor and the integrated manufacture method with high voltage transistor of double-diffused drain electrode comprise:
Form a dielectric layer and a conductive layer in regular turn on a substrate, this substrate has a low voltage component district and a high voltage device district;
At least two first photoresists that form patterning are on this conductive layer;
This conductive layer that etch exposed goes out and under this dielectric layer, to form one first and one second grid and one first and one second gate dielectric layer respectively in this low voltage component district and this high voltage device district on this substrate;
Stablize the structure of those first photoresists;
One second photoresist that forms patterning is covered on this low voltage component district;
This high voltage device district is carried out one first ion doping technology, in this substrate of these second grid both sides, to form a dark knot light doping section respectively;
Remove this second photoresist;
Carry out one second ion doping technology, in this substrate of these first grid both sides, to form lightly doped drain respectively;
Remove those first photoresists;
Form a plurality of clearance walls in this first with the sidewall of this second grid; And
Carry out one the 3rd ion doping technology, in the substrate of the outside of those clearance walls, to form source/drain.
8. low voltage transistor as claimed in claim 7 and the integrated manufacture method with high voltage transistor of double-diffused drain electrode, the method for wherein stablizing those first photoresists comprises hard roasting.
9. low voltage transistor as claimed in claim 8 and the integrated manufacture method with high voltage transistor of double-diffused drain electrode wherein should hard roasting method comprise heating or irradiating ultraviolet light.
10. low voltage transistor as claimed in claim 7 and the integrated manufacture method with high voltage transistor of double-diffused drain electrode, wherein the thickness of those first photoresists is greater than 8000 dusts.
11. low voltage transistor as claimed in claim 7 and the integrated manufacture method with high voltage transistor of double-diffused drain electrode, wherein the material of this conductive layer comprises polysilicon or metal silicide.
12. low voltage transistor as claimed in claim 7 and the integrated manufacture method with high voltage transistor of double-diffused drain electrode, the removal method of those first photoresists comprises that oxygen plasma ashing method or wet type divest method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710137116XA CN101350307A (en) | 2007-07-19 | 2007-07-19 | Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200710137116XA CN101350307A (en) | 2007-07-19 | 2007-07-19 | Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage |
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| CN101350307A true CN101350307A (en) | 2009-01-21 |
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| CNA200710137116XA Pending CN101350307A (en) | 2007-07-19 | 2007-07-19 | Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446852A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method used for integrating deep junction depth device and shallow junction depth device |
| CN102945809A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Forming method of drift region |
| WO2014093644A1 (en) * | 2012-12-14 | 2014-06-19 | Spansion Llc | Use disposable gate cap to form transistors, and split gate charge trapping memory cells |
| CN107919280A (en) * | 2017-11-06 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | The integrated manufacturing method of different voltages device |
-
2007
- 2007-07-19 CN CNA200710137116XA patent/CN101350307A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446852A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method used for integrating deep junction depth device and shallow junction depth device |
| CN102945809A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Forming method of drift region |
| WO2014093644A1 (en) * | 2012-12-14 | 2014-06-19 | Spansion Llc | Use disposable gate cap to form transistors, and split gate charge trapping memory cells |
| US9590079B2 (en) | 2012-12-14 | 2017-03-07 | Cypress Semiconductor Corporation | Use disposable gate cap to form transistors, and split gate charge trapping memory cells |
| US10777568B2 (en) | 2012-12-14 | 2020-09-15 | Cypress Semiconductor Corporation | Split gate charge trapping memory cells having different select gate and memory gate heights |
| US11450680B2 (en) | 2012-12-14 | 2022-09-20 | Infineon Technologies LLC | Split gate charge trapping memory cells having different select gate and memory gate heights |
| CN107919280A (en) * | 2017-11-06 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | The integrated manufacturing method of different voltages device |
| CN107919280B (en) * | 2017-11-06 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | Integrated manufacturing method of different-voltage device |
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Open date: 20090121 |