CN102945809A - Forming method of drift region - Google Patents
Forming method of drift region Download PDFInfo
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- CN102945809A CN102945809A CN2012105075999A CN201210507599A CN102945809A CN 102945809 A CN102945809 A CN 102945809A CN 2012105075999 A CN2012105075999 A CN 2012105075999A CN 201210507599 A CN201210507599 A CN 201210507599A CN 102945809 A CN102945809 A CN 102945809A
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- dielectric layer
- drift region
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Abstract
The invention provides a forming method of a drift region, and the method comprises the following steps of: forming a grid electrode on a semiconductor substrate; coating a photoetching glue layer; developing and exposing the photoetching glue layer, then etching a grid dielectric layer exposed from two sides of the grid electrode, remaining one part of the grid dielectric layer; and directly carrying out ion implantation on the remained grid dielectric layer and the semiconductor substrate under the remained grid dielectric layer to form the drift region. According to the forming method, the process step is simplified and the production cost is lowered.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of drift region.
Background technology
At present, general asymmetric metal-oxide-semiconductor, its source electrode can not be high pressure resistant, only has the drain electrode can be high pressure resistant, and another kind of symmetric form metal-oxide-semiconductor, its source electrode and drain electrode all can be born high pressure.Therefore, most symmetric form MOS devices that adopt in the high voltage integrated circuit.
The formation method of traditional high pressure symmetric form metal-oxide-semiconductor comprises:
At first, provide Semiconductor substrate 10, gate dielectric layer 20 on described Semiconductor substrate 10; Form grid 30 at described gate dielectric layer 20, as shown in Figure 1; Wherein, the thickness of described gate dielectric layer 20 is usually greater than 400 dusts.
Then, apply the first photoresist layer 41, described the first photoresist layer 41 covers described Semiconductor substrate 10 and described grid 30; Subsequently described the first photoresist layer 41 is exposed, develops, expose the described gate dielectric layer 20 of described grid 30 both sides, as shown in Figure 2;
Then, as mask, the gate dielectric layer 20 that exposes is carried out etching with described the first photoresist layer 41, keep the gate dielectric layer 20 ' of a part; Remove described the first photoresist layer 41, expose described grid 30, as shown in Figure 3;
Next, apply the second photoresist layer 42, and described the second photoresist layer 42 is exposed, develops, expose the gate dielectric layer 20 ' of described grid 30 both sides; Remaining gate dielectric layer 20 ' and described Semiconductor substrate 10 are carried out Implantation, form P type drift region (or N-type drift region) 70, and remove described the second photoresist layer 42, such as Fig. 4 and shown in Figure 5.
Usually, because when the preparation high voltage device, the thickness of described gate dielectric layer 20 surpasses 400 dusts, when the described gate dielectric layer 20 of Implantation and described Semiconductor substrate 10 formation P type drift region 70(or N-type drift regions 70) time, gate dielectric layer 20 blocked up meetings are carried out certain stopping to ion, can cause the P type drift region 70(or the N-type drift region 70 that form) excessively shallow, even failure.So need first etching to remove the gate dielectric layer 20 of a part of described grid 30 both sides, make ion be more prone to be injected into described Semiconductor substrate 10 formation P type drift region 70(or the N-type drift regions 70 of described grid 30 both sides).
Yet in the existing technique, apply first the first photoresist layer, to the first photoresist layer expose, after the development treatment, the first photoresist layer cover gate as mask, is carried out etching to described gate dielectric layer by the first photoresist layer again; On the one hand because described the first photoresist layer is subject to certain damage, the follow-up Implantation that carries out need to be made photoresist layer only exposes grid both sides source drain region as mask Semiconductor substrate again on the other hand, thereby just can carry out Implantation, thereby need to remove described the first photoresist layer, apply again the second photoresist layer, the second photoresist layer is exposed, after the development treatment, carries out Implantation again and form P type drift region 70(or N-type drift region 70).Wherein, the first photoresist layer is used for the etch mask layer as the etching grid dielectric layer, and the second photoresist layer is used for the mask layer as Implantation, causes the technique of prior art loaded down with trivial details, and the waste consumptive material, increases cost.
Summary of the invention
The object of the invention is to propose a kind of formation method of drift region, reduce processing step, reduce production costs.
To achieve these goals, the present invention proposes a kind of formation method of drift region, comprising:
Semiconductor substrate is provided;
Surface in described Semiconductor substrate forms gate dielectric layer;
Surface at described gate dielectric layer forms grid;
Apply photoresist layer, described photoresist layer covers described Semiconductor substrate and described grid;
Described photoresist layer is exposed, develops, expose the gate dielectric layer of described grid both sides;
As mask, etching is removed the gate dielectric layer of a part with described photoresist layer;
As stopping, remaining gate dielectric layer and described Semiconductor substrate are carried out Implantation with described photoresist layer, form the drift region.
Further, described Semiconductor substrate is N trap or P trap substrate.
Further, the material of described gate dielectric layer is silicon dioxide.
Further, described gate dielectric layer adopts chemical vapor deposition method to form.
Further, the thickness of described gate dielectric layer is greater than 400 dusts.
Further, the thickness of remaining gate dielectric layer is 80～120 dusts.
Further, described photoresist layer thickness is greater than 20000 dusts.
Further, described drift region is symmetrical drift region.
Further, described drift region is P type drift region or N-type drift region.
Compared with prior art, beneficial effect major embodiment of the present invention in: form grid in Semiconductor substrate, apply again photoresist layer, to described photoresist layer develop, after the exposure-processed, the gate dielectric layer that first the grid exposed at both sides is gone out carries out etching, keeps a part of gate dielectric layer, more directly to remaining gate dielectric layer with and lower Semiconductor substrate carry out Implantation formation drift region, thereby simplified processing step, reduced production cost.
Description of drawings
Fig. 1 to Fig. 5 is the structural representation of a drift region formation method in the prior art;
Fig. 6 is the flow chart of the formation method of drift region in one embodiment of the invention;
Fig. 7 to Figure 11 is the structural representation of drift region formation method in one embodiment of the invention.
Embodiment
For the ease of understanding, be described in detail below in conjunction with specific embodiment and Fig. 6-11 couple the present invention.
Please refer to Fig. 6, the present invention proposes a kind of formation method of drift region, comprising:
Step S1: Semiconductor substrate 100 is provided; Be formed with N trap or P trap (not shown) in the described Semiconductor substrate 100, in the present embodiment, select to be formed with the Semiconductor substrate 100 of N trap.
Step S2: the surface in described Semiconductor substrate 100 forms gate dielectric layer, and the thickness of described gate dielectric layer is greater than 400 dusts; In the present embodiment, make the first device region, the second device region and the 3rd device region on the described Semiconductor substrate 100, described the first device region is used to form high voltage device, for example is the 30V high tension apparatus; Described the second device region is used to form middle voltage devices district; Described the 3rd device region is used to form the voltage devices district; When needs formed high voltage device, the voltage that can bear in order to improve device then needed to form thicker gate dielectric layer, when needs form low-voltage electrical equipment, only needed to form thinner gate dielectric layer; The step that forms this three classes device region specifically comprises: at first, only form first grid dielectric layer (high voltage dielectric layer) 210 at the first device region; Secondly, only form second grid dielectric layer (middle voltage dielectric layer) 220 at the first device region and the second device region; Then, only form the 3rd gate dielectric layer (low-voltage dielectric layer) 230 at the first device region, the second device region and the 3rd device region; Because present embodiment only relates to the first device region (high voltage device district), so the formation technique of other two kinds of device regions do not repeat them here, and accompanying drawing only shows the first device region.
Concrete, as shown in Figure 7, the gate dielectric layer of the first device region comprises first grid dielectric layer 210, second grid dielectric layer 220 and the 3rd gate dielectric layer 230 in the present embodiment; Described first grid dielectric layer 210, described second grid dielectric layer 220 and described the 3rd gate dielectric layer 230 materials are silicon dioxide; Described first grid dielectric layer 210, described second grid dielectric layer 220 and described the 3rd gate dielectric layer 230 all adopt chemical vapor deposition method to form; The thickness of described first grid dielectric layer 210 is 400～500 dusts, for example is 480 dusts; The thickness of described second grid dielectric layer 220 is 90～120 dusts, for example is 110 dusts; The thickness of described the 3rd gate dielectric layer 230 is 30～50 dusts, for example is 40 dusts.
Step S3: the surface at described the 3rd gate dielectric layer 230 forms grid 300; Wherein, as shown in Figure 7, form one deck polysilicon layer on the surface of described the 3rd gate dielectric layer 230 first, then described polysilicon layer is carried out etching and form described grid 300, this technique is this area technological means commonly used, does not repeat them here.
Step S4: apply photoresist layer 400, described photoresist layer 400 covers described Semiconductor substrate 100 and described grid 300; Wherein, described photoresist layer thickness is greater than 20000 dusts, for subsequent etching and Implantation are done mask and stopped.
Step S5: described photoresist layer 400 is exposed, develops, expose the 3rd gate dielectric layer 230 of described grid 300 both sides; Wherein, exposure and development are the technological means that those skilled in the art habitually practise, and do not repeat them here.In general, after described photoresist layer 400 was exposed development treatment, 400 of described photoresist layers exposed the Semiconductor substrate 100 of described grid 300 both sides, so that subsequent technique processes, as shown in Figure 8.
Step S6: as mask, the 3rd gate dielectric layer 230, second grid dielectric layer 220 and the first grid dielectric layer 210 that exposes carried out etching with described photoresist layer 400, keep the first grid dielectric layer 210 ' of a part, as shown in Figure 9; As what mention in the background technology, because the thickness sum of described first grid dielectric layer 210, second grid dielectric layer 220 and the 3rd gate dielectric layer 230 surpasses 400 dusts usually, when the described Semiconductor substrate 100 of using ion directly to pass first grid dielectric layer 210, second grid dielectric layer 220 and 230 pairs of described grids of the 3rd gate dielectric layer, 400 both sides is injected, can cause the P type drift region 500(or the N-type drift region 500 that form) excessively shallow, even failure.So need etching to remove the first grid dielectric layer 210 of the 3rd gate dielectric layer 230 of grid 400 both sides, second grid dielectric layer 220 and a part, make ion be more prone to be injected into described Semiconductor substrate 100 formation P type drift region 500(or the N-type drift regions 500 of described grid 400 both sides); Wherein, describe for convenient, remaining first grid dielectric layer is designated as 210 ', the thickness of described remaining first grid dielectric layer 210 ' is 80～120 dusts, for example is 100 dusts.
Step S7: as stopping, directly described remaining first grid dielectric layer 210 ' and described Semiconductor substrate 100 are carried out Implantation with described photoresist layer 400, form drift region 500, such as Figure 10 and shown in Figure 11; Wherein, described drift region 500 is the symmetric form drift region, for example is all P type drift region or is all the N-type drift region, should form P type drift region in the present embodiment.
In the present embodiment, because described photoresist layer 400 thickness are thicker, after described first grid dielectric layer 210, described second grid dielectric layer 220 and described the 3rd gate dielectric layer 230 are carried out etching, still remaining with enough photoresist layers 400 can stop for the Implantation conduct, therefore no longer remove described photoresist layer 400, but again with described photoresist layer 400 as stopping, described remaining first grid dielectric layer 210 ' and described Semiconductor substrate 100 are carried out Implantation, form drift region 500; So just can reduce processing step, reach the purpose that reduces cost.
Only be the preferred embodiments of the present invention below, the present invention do not played any restriction.Any person of ordinary skill in the field; in the scope that does not break away from technical scheme of the present invention; technical scheme and technology contents that the present invention discloses are made any type of changes such as replacement or modification that are equal to; all belong to the content that does not break away from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (9)
1. the formation method of a drift region comprises:
Semiconductor substrate is provided;
Surface in described Semiconductor substrate forms gate dielectric layer;
Surface at described gate dielectric layer forms grid;
Apply photoresist layer, described photoresist layer covers described Semiconductor substrate and described grid;
Described photoresist layer is exposed, develops, expose the gate dielectric layer of described grid both sides;
As mask, etching is removed the gate dielectric layer of a part with described photoresist layer;
As stopping, remaining gate dielectric layer and described Semiconductor substrate are carried out Implantation with described photoresist layer, form the drift region.
2. the formation method of drift region as claimed in claim 1 is characterized in that, described Semiconductor substrate is N trap or P trap substrate.
3. the formation method of drift region as claimed in claim 1 is characterized in that, the material of described gate dielectric layer is silicon dioxide.
4. the formation method of drift region as claimed in claim 3 is characterized in that, described gate dielectric layer adopts chemical vapor deposition method to form.
5. the formation method of drift region as claimed in claim 1 is characterized in that, the thickness of described gate dielectric layer is greater than 400 dusts.
6. the formation method of drift region as claimed in claim 1 is characterized in that, the thickness of remaining gate dielectric layer is 80～120 dusts.
7. the formation method of drift region as claimed in claim 1 is characterized in that, the thickness of described photoresist layer is greater than 20000 dusts.
8. the formation method of drift region as claimed in claim 1 is characterized in that, described drift region is symmetrical drift region.
9. the formation method of drift region as claimed in claim 8 is characterized in that, described drift region is P type drift region or N-type drift region.
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| CN2012105075999A CN102945809A (en) | 2012-11-30 | 2012-11-30 | Forming method of drift region |
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| CN2012105075999A CN102945809A (en) | 2012-11-30 | 2012-11-30 | Forming method of drift region |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448888A (en) * | 2014-08-21 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, manufacturing method thereof, and semiconductor device |
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| CN87107677A (en) * | 1986-11-04 | 1988-06-22 | 英特尔公司 | Method for producing metal oxide semi-conductor field effect integrated circuit with slowly changing source leakage |
| US20050250342A1 (en) * | 2004-04-13 | 2005-11-10 | Naohiro Ueda | Semiconductor device placing high, medium, and low voltage transistors on the same substrate |
| CN1873929A (en) * | 2005-06-03 | 2006-12-06 | 联华电子股份有限公司 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
| CN101154614A (en) * | 2006-09-27 | 2008-04-02 | 上海华虹Nec电子有限公司 | Isolation structure used for semiconductor integrated circuit and method of producing the same |
| CN101350307A (en) * | 2007-07-19 | 2009-01-21 | 茂德科技股份有限公司 | Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage |
| US20100314695A1 (en) * | 2009-06-10 | 2010-12-16 | International Rectifier Corporation | Self-aligned vertical group III-V transistor and method for fabricated same |
| CN102270576A (en) * | 2011-09-01 | 2011-12-07 | 上海宏力半导体制造有限公司 | Method for manufacturing MOS (Metal Oxide Semiconductor) transistor |
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2012
- 2012-11-30 CN CN2012105075999A patent/CN102945809A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87107677A (en) * | 1986-11-04 | 1988-06-22 | 英特尔公司 | Method for producing metal oxide semi-conductor field effect integrated circuit with slowly changing source leakage |
| US20050250342A1 (en) * | 2004-04-13 | 2005-11-10 | Naohiro Ueda | Semiconductor device placing high, medium, and low voltage transistors on the same substrate |
| CN1873929A (en) * | 2005-06-03 | 2006-12-06 | 联华电子股份有限公司 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
| CN101154614A (en) * | 2006-09-27 | 2008-04-02 | 上海华虹Nec电子有限公司 | Isolation structure used for semiconductor integrated circuit and method of producing the same |
| CN101350307A (en) * | 2007-07-19 | 2009-01-21 | 茂德科技股份有限公司 | Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage |
| US20100314695A1 (en) * | 2009-06-10 | 2010-12-16 | International Rectifier Corporation | Self-aligned vertical group III-V transistor and method for fabricated same |
| CN102270576A (en) * | 2011-09-01 | 2011-12-07 | 上海宏力半导体制造有限公司 | Method for manufacturing MOS (Metal Oxide Semiconductor) transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448888A (en) * | 2014-08-21 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, manufacturing method thereof, and semiconductor device |
| CN105448888B (en) * | 2014-08-21 | 2019-02-26 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, the production method of interlayer dielectric layer and semiconductor devices |
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Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address after: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
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Free format text: CORRECT: APPLICANT; FROM: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI TO: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION |
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Application publication date: 20130227 |
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