CN1873929A - Component of metal oxide semiconductor transistor in high voltage, and fabricating method - Google Patents
Component of metal oxide semiconductor transistor in high voltage, and fabricating method Download PDFInfo
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- CN1873929A CN1873929A CN 200510074787 CN200510074787A CN1873929A CN 1873929 A CN1873929 A CN 1873929A CN 200510074787 CN200510074787 CN 200510074787 CN 200510074787 A CN200510074787 A CN 200510074787A CN 1873929 A CN1873929 A CN 1873929A
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Abstract
The modified technique of high voltage is in use for improving efficiency of breakdown voltage on components in high voltage. Meanwhile, the invention maintains integrality of insulation structure of shallow grooves. Main characters are that it is not needed to carry out back etching for thick oxide layer in region of components in high voltage before ion implantation in high concentration is carried out. Therefore, cost for one piece of mask is saved.
Description
Technical field
The present invention relates to the making of semiconductor integrated circuit, particularly relate to a kind of high-voltage metal oxide semiconductor (MOS) transistor unit technology of improvement.
Background technology
Known to the sector person, with high voltage device and low voltage component, as high/low pressure metal-oxide semiconductor (MOS) (MOS) transistor, the integrated circuit technique of integration and making is existing skill simultaneously.For example, use low voltage component to come the production control circuit, using high voltage device to make can electric program read-only memory (ElectricallyProgrammable Read-Only-Memory, EPROM) or the drive circuit of LCD or the like.
See also Fig. 1 to Fig. 7, what it illustrated is to adopt shallow groove insulation configuration to make the generalized section of isolated high pressure NMOS element technology according to existing method.At first, as shown in Figure 1, elder generation is at high voltage device p type wells (the high-voltage P well at the semiconductor-based end 10, HVPW) form shallow-channel insulation (STI) structure 14 and 16 on 12, wherein shallow groove insulation configuration 14 defines high voltage device zone 102, and shallow groove insulation configuration 16 then separates into high voltage device zone 102 two zones 104 and 106 again.
As shown in Figure 2, carry out an ion implantation technology, in high voltage device p type wells 12, form N type grade doping zone (N-grade region) 20.Then, on the surface at the semiconductor-based end 10, form sacrificial oxide layer 22 and silicon nitride cap rock 24 in regular turn.
As shown in Figure 3, then carry out a photoetching and etch process, with the sacrificial oxide layer 22 and silicon nitride cap rock 24 ablations in high voltage device zone 102, to expose the semiconductor-based basal surface in high voltage device zone 102.
As shown in Figure 4, the thick oxide layer 42 on the about 850 Izod right sides of growth thickness (at the high voltage device of 32 volts or 40 volts) on the surface, the semiconductor-based ends 10 of the zone 104 in high voltage device zone 102 and 106.Then, as shown in Figure 5, on the thick oxide layer 42 in zone 104, form polysilicon gate 52, and an end of polysilicon gate 52 extends to shallow groove insulation configuration 16 tops.
As shown in Figure 6, the source/drain that next will carry out high concentration mixes, but before this, needs earlier to remove with one photomask and with the thick oxide layer on the regions and source 42.Yet, in the time of etching thick oxide layer 42, also can form the sunk area 64 and 66 of the hundreds of dusts of the degree of depth respectively in shallow groove insulation configuration 14 and 16.
At last, as shown in Figure 7, carry out a high concentration N
+Ion implantation technology, a side of the polysilicon gate 52 in the zone 104 in high voltage device zone 102 forms N
+ Doped region 72 forms N in the zone 106 in high voltage device zone 102 simultaneously
+Doped region 74.But because the cause of sunk area 64 and 66 is being carried out aforementioned high concentration N
+After the ion implantation technology, can make N
+ Doped region 72 and 74 doping profile comprise the doped region 72a and the 74a of downward extension.Yet, because N
+ Doped region 74 more near the knot 78 of N type grade doping zone 20 with high voltage device p type wells 12, causes the puncture voltage (breakdown voltage) of this high voltage device to reduce via doped region 74a.
Hence one can see that, and conventional semiconductor high-pressure MOS element technology still has the space of further improvement.
Summary of the invention
Therefore, main purpose of the present invention is in that a kind of high-pressure MOS element technology of improvement is provided, to solve the problem of above-mentioned existing skill.
Another object of the present invention is in the semiconductor technology that a kind of while integrating high-voltage element and low voltage component are provided, to promote the usefulness of high voltage device.
For reaching above-mentioned purpose, the preferred embodiments of the present invention provide a kind of method of making component of metal oxide semiconductor transistor in high voltage, comprise the steps:
The semiconductor substrate is provided, comprises a high voltage device zone, wherein be formed with shallow groove insulation configuration on this semiconductor-based end, and this high voltage device zone is separated into first area and second area again;
This intermediate ion of semiconductor-based end in this high voltage device zone injects one first doped region and one second doped region, and is a passage area between this first doped region and second doped region;
On this semiconductor-based end, form a sacrificial oxide layer;
Deposition one silicon nitride cap rock on this sacrificial oxide layer;
Form an opening in this silicon nitride cap rock and this sacrificial oxide layer, this opening only exposes this first area of part that comprises this passage area, but covers this second area;
Growth one first oxide layer on this semiconductor-based end that this opening exposed;
Remove this silicon nitride cap rock and this sacrificial oxide layer;
One second oxide layer of on this first area in this high voltage device zone and this second area, growing up, and this second thickness of oxide layer is less than this first thickness of oxide layer;
On this first oxide layer, form a grid; And
Utilize this grid and this first oxide layer to inject shielding and carry out ion implantation technology as ion, form the 3rd doped region in this first doped region in this first area, form the 4th doped region in this second doped region in this second area simultaneously.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended graphic only for reference and aid illustration usefulness is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 7 illustrated is according to the generalized section that has method high-pressure MOS element technology now.
What Fig. 8 to Figure 14 illustrated is the generalized section of high-pressure MOS element technology of the present invention.
The simple symbol explanation
10 high voltage device p type wellses of the semiconductor-based ends 12
14 shallow groove insulation configuration, 16 shallow groove insulation configuration
20a N type grade doping zone, 20 N type grade dopings zone
20b N type grade doping zone 22 sacrificial oxide layers
24 silicon nitride cap rocks, 42 thick oxide layers
46 thin oxide layers, 52 polysilicon gates
64 sunk areas, 66 sunk areas
72 N
+Doped region 74 N
+Doped region
The doped region that the doped region 74a that 72a extends downwards extends downwards
78 knots, 90 passage area
102 high voltage device zones, 100 low voltage components zone
104 regional 106 zones
114 shallow groove insulation configuration, 146 thin oxide layers
152 polysilicon gates, 174 N
+Doped region
224 openings
Embodiment
See also Fig. 8 to Figure 14, what it illustrated is the generalized section of high pressure NMOS element technology of the present invention.The present invention can also be applied in high voltage PMOS element technology, only needs to get final product electrically making suitable modification.
As shown in Figure 8, provide semiconductor substrate 10, be formed with high voltage device p type wells (high-voltage P well, HVPW) 12 on it.At first, on the semiconductor-based end 10, form shallow-channel insulation (STI) structure 14,16 and 114, wherein shallow groove insulation configuration 114 defines low voltage component zone 100, shallow groove insulation configuration 14 defines high voltage device zone 102, and shallow groove insulation configuration 16 then separates high voltage device zone 102 become zone 104 and 106 again.In zone 104, will hold the passage area and the regions and source of high voltage device, and in zone 106, will form another regions and source of high voltage device.
As shown in Figure 9, carry out an ion implantation technology, in high voltage device p type wells 12, form N type grade doping zone (N-grade region) 20a and 20b, wherein form a passage area 90 between N type grade doping zone 20a and the 20b.N type grade doping zone 20a coats shallow groove insulation configuration 16, and extends to zone 104.Then, on the surface at the semiconductor-based end 10, form sacrificial oxide layer 22 and silicon nitride cap rock 24 in regular turn.
As shown in figure 10, carry out a photoetching and etch process, to form an opening 224 in sacrificial oxide layer 22 in high voltage device zone 102 and the silicon nitride cap rock 24, it exposes a part of zone 104, comprises aforesaid passage area 90.At this moment, silicon nitride cap rock 24 still covers the zone 106 in low voltage component zone 100 and high voltage device zone 102.
As shown in figure 11, carry out oxide layer growth technology, the thickness of only growing up on the surface, the semiconductor-based ends 10 that opening 224 is come out is about 700 to 900 dusts, for example the thick oxide layer 42 of 850 dusts.Then, as shown in figure 12, sacrificial oxide layer 22 at the semiconductor-based end 10 and silicon nitride cap rock 24 are removed.Carry out another oxide layer growth technology then, go up the surface, the semiconductor-based ends 10 in grow up a thin oxide layer 146 and high voltage device zone 102 simultaneously in the surface, the semiconductor-based ends 10 in low voltage component zone 100 and go up the thin oxide layer 46 of growing up.
As shown in figure 13, on 104 the thick oxide layer 42 of zone, form polysilicon gate 52, and an end of polysilicon gate 52 extends to shallow groove insulation configuration 16 tops, simultaneously, on the thin oxide layer 146 in low voltage component zone 100, form polysilicon gate 152.
As shown in figure 14, carry out a high concentration N
+Ion implantation technology, a side of the polysilicon gate 52 in the zone 104 in high voltage device zone 102 forms N
+ Doped region 72, and at the zone in high voltage device zone 102 106 formation N
+Doped region 74.Simultaneously, the both sides of the polysilicon gate 152 in low voltage component zone 100 form N
+ Doped region 174.
Compared to existing skill, advantage of the present invention mainly includes:
(1) carrying out high concentration N
+Before the ion implantation technology, do not need to carry out the etching of thick oxide layer, therefore can in shallow groove insulation configuration, not form sunk area.So, N
+The doping profile of doped region does not have the phenomenon of downward extension, therefore can improve the breakdown voltage characteristics of high voltage device.
(2), one photomask and etch process have therefore also been saved owing to do not need to carry out the etching of thick oxide layer.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (13)
1. method of making component of metal oxide semiconductor transistor in high voltage comprises:
The semiconductor substrate is provided, comprises a high voltage device zone, wherein be formed with shallow groove insulation configuration on this semiconductor-based end, it separates into first area and second area again with this high voltage device zone;
This intermediate ion of semiconductor-based end in this high voltage device zone injects one first doped region and one second doped region, and is a passage area between this first doped region and second doped region;
On this semiconductor-based end, form a sacrificial oxide layer;
Deposition one silicon nitride cap rock on this sacrificial oxide layer;
Form an opening in this silicon nitride cap rock and this sacrificial oxide layer, this opening only exposes this first area of part that comprises this passage area, but covers this second area;
Growth one first oxide layer on this semiconductor-based end that this opening exposed;
Remove this silicon nitride cap rock and this sacrificial oxide layer;
One second oxide layer of on this first area in this high voltage device zone and this second area, growing up;
On this first oxide layer, form a grid; And
Utilize this grid and this first oxide layer to inject shielding and carry out ion implantation technology as ion, form the 3rd doped region in this first doped region in this first area, form the 4th doped region in this second doped region in this second area simultaneously.
2. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein this second thickness of oxide layer is less than this first thickness of oxide layer.
3. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 2, wherein this first thickness of oxide layer is about 700 to 900 dusts.
4. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, this grid that wherein is formed on this first oxide layer extends on this shallow groove insulation configuration.
5. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein the doping content of the doping content of this first doped region and this second doped region about equally.
6. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein the doping content of the doping content of the 3rd doped region and the 4th doped region about equally.
7. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein the doping content of the 3rd doped region is greater than the doping content of this first doped region.
8. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein the doping content of the 4th doped region is greater than the doping content of this second doped region.
9. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 1, wherein this second doped region coats this shallow groove insulation configuration, and extends to this first area.
10. method of making component of metal oxide semiconductor transistor in high voltage comprises:
The semiconductor substrate is provided, comprises a high voltage device zone, wherein be formed with shallow groove insulation configuration on this semiconductor-based end, it separates into first area and second area again with this high voltage device zone;
This intermediate ion of semiconductor-based end in this high voltage device zone injects one the one N type grade doping zone and one the 2nd N type grade doping zone, and is a passage area between N type grade doping zone and the 2nd N type grade doping zone;
On this semiconductor-based end, form a screen;
Form an opening in this screen, this opening only exposes this first area of part that comprises this passage area, but covers this second area;
Growth one first oxide layer on this semiconductor-based end that this opening exposed;
Remove this screen;
One second oxide layer of on this first area in this high voltage device zone and this second area, growing up;
On this first oxide layer, form a grid; And
Utilize this grid and this first oxide layer to inject shielding and carry out ion implantation technology as ion, form the 3rd N type doped region in the N type grade doping zone in this first area, form the 4th N type doped region in the 2nd N type grade doping zone in this second area simultaneously.
11. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 10, wherein this second thickness of oxide layer is less than this first thickness of oxide layer.
12. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 10, wherein this first thickness of oxide layer is about 700 to 900 dusts.
13. the method for making component of metal oxide semiconductor transistor in high voltage as claimed in claim 10, wherein this grid extends on this shallow groove insulation configuration.
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| CN1873929A true CN1873929A (en) | 2006-12-06 |
| CN100416780C CN100416780C (en) | 2008-09-03 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194684A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Grid dielectric layer manufacturing method |
| CN102945809A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Forming method of drift region |
| CN108257919A (en) * | 2016-12-29 | 2018-07-06 | 联华电子股份有限公司 | Stochastic and dynamic handles the forming method of memory component |
| CN113745161A (en) * | 2021-09-06 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306711B1 (en) * | 1998-11-03 | 2001-10-23 | United Microelectronics Corp. | Method of fabricating a high-voltage lateral double diffused metal oxide semiconductor |
| US6198131B1 (en) * | 1998-12-07 | 2001-03-06 | United Microelectronics Corp. | High-voltage metal-oxide semiconductor |
| US6392274B1 (en) * | 2000-04-04 | 2002-05-21 | United Microelectronics Corp. | High-voltage metal-oxide-semiconductor transistor |
| GB2374456A (en) * | 2000-12-09 | 2002-10-16 | Esm Ltd | High-voltage metal oxide semiconductor device and method of forming the device |
| TW594993B (en) * | 2001-02-16 | 2004-06-21 | Sanyo Electric Co | Semiconductor device and manufacturing process therefor |
| KR100460272B1 (en) * | 2003-02-27 | 2004-12-08 | 매그나칩 반도체 유한회사 | Method for fabricating of high voltage dual gate device |
-
2005
- 2005-06-03 CN CNB2005100747877A patent/CN100416780C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194684A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Grid dielectric layer manufacturing method |
| CN102194684B (en) * | 2010-03-12 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Grid dielectric layer manufacturing method |
| CN102945809A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Forming method of drift region |
| CN108257919A (en) * | 2016-12-29 | 2018-07-06 | 联华电子股份有限公司 | Stochastic and dynamic handles the forming method of memory component |
| CN108257919B (en) * | 2016-12-29 | 2020-10-27 | 联华电子股份有限公司 | Method for forming random dynamic processing memory element |
| CN113745161A (en) * | 2021-09-06 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
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| CN100416780C (en) | 2008-09-03 |
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