KR101123041B1 - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- KR101123041B1 KR101123041B1 KR1020040105559A KR20040105559A KR101123041B1 KR 101123041 B1 KR101123041 B1 KR 101123041B1 KR 1020040105559 A KR1020040105559 A KR 1020040105559A KR 20040105559 A KR20040105559 A KR 20040105559A KR 101123041 B1 KR101123041 B1 KR 101123041B1
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- forming
- semiconductor device
- metal layer
- silicide
- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
Abstract
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 반도체 소자의 동작속도를 향상시키기 위하여 저항을 감소시킬 수 있는 실리사이드(Silicide)를 형성하는데 있어서, 특히 PMOS 게이트에 형성되는 실리사이드의 열적 안정성이 떨어지는 문제를 해결하기 위하여, 게이트를 형성한 후 게이트 전극과 스페이서 사이에 공간을 형성하여 그 영역에 실리사이드를 형성하는 금속층이 매립되도록 함으로써, 실리사이드의 형성을 위한 반응 면적이 더 증가되도록 하는 반도체 소자의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In order to improve the operating speed of a semiconductor device, a silicide capable of reducing a resistance may be formed. In order to solve the problem, a method of forming a semiconductor device in which a space is formed between the gate electrode and the spacer after the gate is formed so that the metal layer forming the silicide is buried in the region, thereby increasing the reaction area for the formation of the silicide. It is about.
Description
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 >Description of the Related Art
100 : 반도체 기판 110 : 게이트 산화막100
120 : 게이트 전극 130 : 측벽 산화막120
140 : 스페이서 150 : 마스크층140: spacer 150: mask layer
160 : 금속층 170 : 실리사이드160: metal layer 170: silicide
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 반도체 소자의 동작속도를 향상시키기 위하여 저항을 감소시킬 수 있는 실리사이드를 형성하는데 있어서, 특히 PMOS 게이트에 형성되는 실리사이드의 열적 안정성이 떨어지는 문제를 해결하기 위하여, 게이트를 형성한 후 게이트 전극과 스페이서 사이에 공간을 형성하여 그 영역에 실리사이드를 형성하는 금속층이 매립되도록 함으로써, 실리사이드의 형성을 위한 반응 면적이 더 증가되도록 하는 반도체 소자의 형성 방법에 관한 것이 다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and in order to solve the problem of lowering the thermal stability of silicide formed in a PMOS gate in forming a silicide capable of reducing resistance in order to improve the operation speed of the semiconductor device. And forming a space between the gate electrode and the spacer after the gate is formed so that the metal layer forming the silicide is embedded in the region, thereby increasing the reaction area for forming the silicide. .
반도체 소자의 형성 공정에 있어서, 반도체 소자의 동작속도는 매우 중요한 요소이다. 이를 위해 특히, 게이트 전극 및 소스/드레인 접합 영역의 저항 감소시키려는 노력으로 실리사이드 형성 공정을 적용하고 있다. 이러한 실리사이드 형성 공정은 금속층을 증착하고 열처리를 통하여 금속과 폴리실리콘층이 반응하여 실리사이드가 형성되도록 하는 것이다. 이때, 반도체 소자에서 폴리실리콘층은 주로 게이트 전극 및 불순물이 도핑된 소스/드레인 접합 영역이므로 활성영역과 게이트 전극 상부에만 실리사이드가 형성되고, 그 주변의 절연 물질에는 형성되지 않도록 하는 것이 중요하다. In the process of forming a semiconductor device, the operating speed of the semiconductor device is a very important factor. To this end, silicide formation processes have been applied, particularly in an effort to reduce the resistance of the gate electrode and source / drain junction regions. The silicide forming process is to deposit a metal layer and to react with the metal and the polysilicon layer through heat treatment to form a silicide. In this case, since the polysilicon layer of the semiconductor device is mainly a source / drain junction region doped with a gate electrode and an impurity, it is important that silicide is formed only in the active region and the upper portion of the gate electrode, and not in the insulating material around the gate electrode and the impurity.
반도체 소자의 회로 선폭이 0.18㎛ 급의 실리사이드 형성 공정에서는 코발트를 적용하고 있으며, 상기의 활성영역 및 게이트 전극 상부에만 실리사이드가 형성되도록 하는 공정(Self Aligned Silicide : 이하 샐리사이드)이 양호하게 수행되고 있다. Cobalt is applied in the process of forming a silicide having a circuit line width of 0.18 占 퐉, and a process of allowing silicide to be formed only in the active region and the upper portion of the gate electrode (Self Aligned Silicide) is performed satisfactorily. .
그러나, 반도체 소자가 고집적화 되면서, I/O(input/output) 영역과 같은 높은 저항 특성을 요구하는 영역에는 샐리사이드 공정이 제대로 수행되지 않아 절연특성을 상실하는 문제가 발생한다. 따라서, 이를 방지하기 위하여 샐리사이드 블로킹(Blocking) 공정이 수행되어야 하는데, 이 과정에서 블로킹 영역에 포함되는 PMOS 게이트의 경우 실리사이드가 제대로 형성되지 못하여 NMOS 게이트 보다 열적 안정성이 떨어지게 되는 문제가 발생한다.However, as semiconductor devices become highly integrated, a salicide process is not properly performed in regions requiring high resistance characteristics such as input / output (I / O) regions, resulting in a loss of insulation characteristics. Therefore, in order to prevent this, a salicide blocking process should be performed. In this process, the PMOS gate included in the blocking region does not have silicide formed properly, resulting in lower thermal stability than the NMOS gate.
또한, 실리사이드를 두껍게 형성하면 반도체 소자의 열적안정성을 증가시킬 수 있으나, 소스/드레인 접합 영역의 경우 두꺼워진 부분만큼 접합 거리가 가까워지게 되어 접합 누설 전류(junction leakage current)가 증가하게 되고 반도체 소자의 특성이 열화 되는 문제가 발생할 수 있다.In addition, when the silicide is formed thicker, the thermal stability of the semiconductor device may be increased. However, in the case of the source / drain junction region, the junction distance is increased by the thickened portion, thereby increasing the junction leakage current and increasing the junction leakage current. The problem of deterioration may occur.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 게이트를 형성한 후 게이트 전극과 스페이서 사이에 공간을 형성하여 그 영역에 실리사이드를 형성하는 금속층이 매립되도록 함으로써, 실리사이드의 형성을 위한 반응 면적이 더 증가되도록 하고 접합 누설 전류의 문제 및 열적 안정성 문제를 해결할 수 있는 반도체 소자의 형성 방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above problems, by forming a space between the gate electrode and the spacer after forming the gate so that the metal layer to form the silicide in the region is embedded, the reaction area for the formation of the silicide is further It is an object of the present invention to provide a method for forming a semiconductor device that can be increased and solves the problem of junction leakage current and thermal stability.
본 발명은 상기와 같은 목적을 달성하기 위한 것으로서,The present invention is to achieve the above object,
(a) 게이트 산화막, 게이트 전극, 측벽 산화막, 스페이서 및 소스/드레인 접합 영역이 구비된 반도체 기판 상에 마스크층을 형성하는 단계와,(a) forming a mask layer on a semiconductor substrate having a gate oxide film, a gate electrode, a sidewall oxide film, a spacer, and a source / drain junction region;
(b) 상기 마스크층을 전면 식각하여 상기 게이트 전극, 측벽 산화막 및 스페이서 상부의 소정부분을 노출시키는 단계와,(b) etching the entire mask layer to expose a predetermined portion of the gate electrode, the sidewall oxide layer, and the spacer;
(c) 상기 노출된 측벽 산화막을 소정 두께 제거하는 단계와,(c) removing the exposed sidewall oxide layer by a predetermined thickness;
(d) 상기 반도체 기판 상에 잔류하는 마스크층을 제거하는 단계와,(d) removing the mask layer remaining on the semiconductor substrate;
(e) 상기 기판 전체 표면 상부에 금속층을 형성하되, 상기 측벽 산화막이 제거되어 형성된 공간을 매립하도록 하는 단계 및(e) forming a metal layer over the entire surface of the substrate, and filling the space formed by removing the sidewall oxide layer;
(f) 상기 금속층을 열처리하여 상기 게이트 전극과 금속층의 계면 및 소스/ 드레인 접합 영역과 금속층의 계면에 실리사이드를 형성하는 단계를 포함하는 것을 특징으로 한다.(f) heat treating the metal layer to form silicide at an interface between the gate electrode and the metal layer and at an interface between the source / drain junction region and the metal layer.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
도 1a를 참조하면, 게이트 산화막(110), 게이트 전극(120), 측벽 산화막(130), 스페이서(140) 및 소스/드레인 접합 영역(미도시)이 구비된 반도체 기판(100) 상에 마스크층(150)을 형성한다. 여기서, 게이트 양측의 반도체 기판(100)을 소스/드레인 접합 영역으로 한다. 이때, 마스크층(150)은 반사방지막 또는 감광막을 사용하는 것이 바람직하며, 반사방지막은 주로 BARC(Bottom Anti Reflect Coating)막을 사용한다. Referring to FIG. 1A, a mask layer on a
도 1b를 참조하면, 마스크층(150)을 전면 식각하여 게이트 전극(120), 측벽 산화막(130) 및 스페이서(140) 상부의 소정부분을 노출시킨다. 이때, 산소 플라즈마를 이용하여 마스크(150)층 상부를 소정 부분 제거하는 것이 바람직하다.Referring to FIG. 1B, the
도 1c를 참조하면, 노출된 측벽 산화막(130)의 상부를 소정 두께 제거한다. 이때, 산화막(130) 제거 용액은 BOE(Buffered Oxide Etchant) 또는 HF를 사용하는 것이 바람직하다.Referring to FIG. 1C, an upper portion of the exposed
다음에는, 반도체 기판(100) 상에 잔류하는 마스크층(150)을 제거한다.Next, the
도 1d를 참조하면, 전체 표면 상부에 금속층(160)을 형성하되, 측벽 산화막 (130)이 제거되어 형성된 공간을 매립하도록 한다. 이때, 금속층(160)은 Co/TiN을 사용하는 것이 바람직하다. 종래의 게이트 전극 상부에만 증착되던 금속층(160)이 게이트 전극의 측벽에까지 형성되도록 함으로써, 후속의 열처리 공정을 통해 실리사이드를 형성하는데 있어서, 반응 면적을 효과적으로 증가시킬 수 있다. 따라서, 게이트 전극 상부에 형성되는 실리사이드는 두껍게 형성하면서, 소스/드레인 접합 영역의 실리사이드는 접합 누설 전류가 발생하지 않도록 실리사이드 공정을 진행할 수 있게 된다.Referring to FIG. 1D, the
도 1e를 참조하면, 금속층(160)을 열처리하여 게이트 전극(120)과 금속층(160)의 계면 및 소스/드레인 접합 영역(미도시)과 금속층(160)의 계면에 실리사이드(170)를 형성 한다.Referring to FIG. 1E, the
이상에서 설명한 바와 같이, 게이트를 형성한 후 게이트 전극과 스페이서 사이에 공간을 형성하여 그 영역에 실리사이드를 형성하는 금속층이 매립되도록 함으로써, 게이트에 형성되는 실리사이드의 열적 안정성이 떨어지는 문제를 해결할 수 있다. 따라서, 고집적 반도체 소자의 동작속도를 안정적으로 확보할 수 있어 반도체 소자의 신뢰성을 향상시키고, 접합 누설 전류 발생을 방지하여 반도체 소자 형성의 수율을 향상시킬 수 있는 효과를 제공한다.As described above, after forming the gate, a space is formed between the gate electrode and the spacer so that the metal layer forming the silicide in the region is buried, thereby reducing the thermal stability of the silicide formed in the gate. Accordingly, the operation speed of the highly integrated semiconductor device can be stably secured, thereby improving the reliability of the semiconductor device and preventing the occurrence of junction leakage current, thereby improving the yield of semiconductor device formation.
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으 로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.
Claims (5)
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