KR100630769B1 - Semiconductor device and method of fabricating the same device - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to prevent defects of the device due to nickel oxidation in an annealing process by forming a cobalt film on a nickel film using in-situ processing. A gate structure(300) having a spacer is formed on an active layer of a substrate(100). A source and a drain regions(130) are formed in the active layer by ion-implantation using the gate structure as a mask. A nickel film is then formed on the resultant structure. A cobalt film is deposited on the nickel film by in-situ, and a cobalt silicide layer(400) is then formed by an annealing process.

Description

Semiconductor device and method of manufacturing the device {Semiconductor device and method of fabricating the same device}

1A and 1B are graphs showing Rc and Rs defects of a semiconductor device having only a conventional Ni silicide layer.

2 is a cross-sectional view of a semiconductor device further including a cobalt silicide layer according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a cobalt silicide layer according to the present invention.

4 is a flowchart illustrating a comparison between a conventional semiconductor device and a method of manufacturing a semiconductor device according to the present invention.

<Description of main parts in the drawing>

100: Substrate ............... 120,120a: LDD area

130: source or drain ... 200: device isolation region

300: gate structure ......... 310: gate insulating layer

320: gate ... 340: spacer

400: silicide layer .............. 420: nickel silicide layer

420a: nickel layer ...... 420b: nickel layer having silicide formed

430: Cobalt silicide layer ... 430a: Cobalt layer

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of preventing oxidation of a nickel silicide layer and a method of manufacturing the same.

In order to solve the problem of increased resistance caused by the miniaturization of the semiconductor device, a method of lowering sheet resistance and contact resistance by forming silicide in a region where a contact such as a gate and a source or a drain are formed is widely used. . Recently, nickel mono-silicide (NiSi) has been newly proposed as a new silicide material capable of overcoming problems caused by TiSi ₂ and CoSi _2, and is being applied and applied in the fabrication of next generation high performance Si devices. . Very high resistance, low resistance, possible silicide reaction at low temperature, much less silicon (Si) consumed to form NiSi of certain thickness than other silicides, especially cobalt disilicide (CoSi ₂ ) Its advantages make it a suitable silicide for applications in next-generation silicon devices with thin junctions.

However, these nickel silicides are problematic due to defects due to oxidation occurring during heat treatment and low thermal stability. In addition, in the ashing process, which is an essential process of removing the remaining PR from the contact etching process, nickel is oxidized to increase the contact Rc. Thus, ashing is omitted. Such a method is used as the remaining PR. It is a process scheme that cannot guarantee the reliability problems that may arise during subsequent integration.

1A and 1B are graphs showing Rc defects and Rs defects of a semiconductor device having a conventional nickel silicide layer only.

Referring to FIG. 1A, it is shown that the resistance of Rc exceeds about 10 ⁴ in the case of NiTa / ashing. If the ashing process is omitted or ashed with HF, the resistance decreases considerably, but the reliability problem as described above occurs. Here, the Y axis represents the distribution percentage of the resistance component, and NiTa / ashing may be regarded as NiSi / ashing.

In the case of Figure 1b shows a sheet resistance (or sheet resistance, poor), the heat treatment process through rapid thermal silicidation (RTS) or endura (endura) equipment shows a high sheet resistance of more than 100.

The increase in Rc and Rs is due to the defect caused by oxidation of Ni generated during the ashing process, which is the above-described Ni silicide heat treatment process or PR removal process.

Accordingly, an object of the present invention is to provide a semiconductor device capable of preventing oxidation of Ni even in a Ni silicide heat treatment process or a PR removal ashing process, and a manufacturing method thereof.

In order to achieve the above technical problem, the present invention provides an active layer having a source, a drain, and a channel region formed on a substrate, a gate structure including a spacer formed on the channel region, and nickel deposited on the active layer and the gate structure. Provided is a semiconductor device including a nickel silicide layer formed by a layer) and a metal silicide layer formed by a metal capping layer deposited on the nickel silicide layer.

According to a preferred embodiment of the present invention, the metal capping layer is formed by depositing cobalt thinner than the nickel layer, the cobalt mono silicide layer is formed through annealing.

In accordance with another aspect of the present invention, there is provided a gate structure including a spacer on an active layer formed on an upper surface of a substrate, and source and drain regions through ion doping the active layer using the gate structure as an anti-doping layer. Forming a nickel layer by depositing nickel on the entire surface of the resultant formed source and drain regions and depositing a metal on the nickel layer to form a metal capping layer and annealing the metal layer to form a metal silicide layer. It provides a method for manufacturing a semiconductor device comprising the step of forming.

According to a preferred embodiment of the present invention, the metal capping layer is formed at a process temperature of 300 ℃ to 400 ℃ and proceed in situ, while acting as a RTS for the silicide reaction of the nickel layer and at the same time prevent the oxidation reaction of nickel Can be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer intervening in between. In the drawings, the thickness and size of each layer are exaggerated for clarity and convenience of explanation. Like numbers refer to like elements in the figures.

2 schematically illustrates a semiconductor device in which a cobalt silicide layer is further formed on a nickel silicide layer according to a preferred embodiment of the present invention.

2, in the semiconductor device, an isolation region 200 is formed in a predetermined region of the substrate 100 to define an active region, and a gate structure 300 is formed over the active region. The active region includes a source, a drain region and a channel region. The LDD region may be included in the active region, and of course, the gate insulating layer and the spacer may be included in the gate structure.

Meanwhile, the silicide layer 400 is formed for the source and drain regions in which the silicon layer exists and the contact structure to be formed later on the gate. The silicide layer 400 according to the present invention is composed of a double silicide layer of the nickel silicide layer 420 and the cobalt silicide layer 430 unlike the conventional art. The nickel silicide layer 420 is naturally formed through a process temperature of 300 ° C. to 400 ° C. during the cobalt deposition process. In addition, since the cobalt deposition process is performed in-situ, the oxidation of nickel can be prevented. Meanwhile, in the subsequent PR removal ashing process, the cobalt silicide layer 430 may exist on the nickel silicide layer 420 to prevent the nickel oxidation reaction.

As such, by forming the cobalt silicide layer 430 on the nickel silicide layer 420, it is possible to prevent defects due to nickel oxidation in a conventional heat treatment or PR removal ashing process.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device including a cobalt silicide layer according to a preferred embodiment of the present invention.

Referring to FIG. 3A, a device isolation region 200 defining an active region is formed in a predetermined region of the substrate 100, a gate insulating layer 310 is formed over the active region, and then a conductive gate 320 is formed. . The gate can be formed of polysilicon. The LDD region 120 is formed by doping the active region using the gate 320 as an anti-doping layer, and the spacer 340 is formed on both sidewalls of the gate to complete the gate structure 300.

Referring to FIG. 3B, a source and / or drain region 130 (hereinafter referred to as a source region) is formed by high-density ion doping in the LDD region using the gate structure 300 as an anti-doping layer. The lower region of the spacer 340 is maintained as the LDD region 120a.

Referring to FIG. 3C, the nickel layer 420a is formed by depositing nickel on the entire upper surface of the resultant in which the source region 130 is formed. The nickel layer 420a is preferably formed to a thickness of about 100 kPa at a process temperature of about 50 ° C. On the other hand, before forming the nickel layer 420a, it is preferable to perform pre-cleaning to remove the oxide film and impurities in the silicide-formed portion.

Referring to FIG. 3D, cobalt is deposited on the entire upper surface of the nickel layer 420a to form a cobalt layer 430a. At this time, the process of forming the cobalt layer 430a proceeds at a process temperature of 300 ° C. to 400 ° C., and is formed thinner than the thickness of the nickel layer. Preferably at a process temperature of 350 ℃ to form a thickness of 10 to 30 kPa. Since the process temperature is a silicide reaction temperature of the nickel layer 420a, the lower nickel layer 420b includes a nickel silicide layer. That is, the nickel layer 420b forms the nickel silicide layer in the portion where silicon is present.

On the other hand, in order to prevent the oxidation of the conventional Ni cobalt layer 430a is preferably carried out in situ. This may also correspond to the in-situ RTS of the nickel layer.

Referring to FIG. 4E, the cobalt layer is annealed to form a cobalt silicide layer 430. At this time, the annealing temperature is preferably about 350 ° C to 450 ° C so that a cobalt mono silicide (CoSi) layer is formed. Meanwhile, TiN may be deposited to a thickness of 150 kPa at a process temperature of 150 ° C. before the cobalt layer annealing. The TiN layer serves to improve the surface roughness of the surface of the silicide layer and to prevent oxidation during the process. The selective wet etching then removes the unreacted metal layer, including TiN. After removal of the metal layer, a second heat treatment at the annealing temperature described above forms a final cobalt mono silicide layer. Since the metal wiring process etc. are the same as before, it abbreviate | omits below.

By forming a semiconductor element by the above process, the semiconductor element which can prevent the defect by Ni oxidation can be manufactured. That is, the nickel oxidation reaction can be prevented by advancing to the RTS process temperature of the nickel layer while the cobalt layer forming process is performed in situ, and the nickel during the subsequent PR removal ashing process due to the presence of the cobalt silicide layer 430. Oxidation reactions can also be prevented.

Figure 5 shows a comparison between the conventional silicide layer forming process and the silicide layer forming process according to the present invention.

Referring to FIG. 5, after the pre-cleaning (S100) for removing the oxide film and impurities, the nickel layer and the TiN layer were formed in the related art, and the nickel silicide layer was formed by the first RTS. However, in the present invention, the nickel layer is formed and cobalt is in situ. A layer and a TiN layer are formed (S200). At this time, the cobalt layer forming process temperature is maintained at about 350 ° C to serve as a conventional first RTS. Therefore, no separate first RTS process is required, and further, it is possible to proceed in situ to prevent the oxidation of nickel.

Thereafter, the selective wet etching process S300 and the second RTS process S400 are the same as in the related art. In addition, the thickness and process temperature of a nickel layer, a cobalt layer, etc. are the same as the above-mentioned as represented by the flowchart.

So far, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described in detail above, in the present invention, a cobalt layer is formed on the nickel layer, but the process temperature is advanced in situ at about the nickel silicide reaction temperature, thereby providing a semiconductor device by nickel oxidation during the conventional heat treatment process for forming nickel silicide. Solve the problem of defects.

In addition, the problem of nickel oxidation in the subsequent PR removal ashing process is also prevented by using a cobalt silicide layer formed on the nickel silicide layer, thereby also solving the problem of defects in semiconductor devices.

Claims (14)

An active layer having source, drain, and channel regions formed on the substrate; A gate structure including a spacer formed on the channel region; A nickel silicide layer formed by a nickel (Ni) layer deposited on the active layer and the gate structure; And And a metal silicide layer formed by a metal capping layer deposited on the nickel silicide layer. According to claim 1, The metal is a semiconductor device, characterized in that the cobalt (Co). The method of claim 2, The metal silicide layer is a cobalt monosilicide (CoSi) layer, characterized in that the semiconductor device. According to claim 1, And the metal capping layer is deposited to a thickness thinner than that of the nickel layer. Forming a gate structure including spacers over the active layer formed on the substrate; Forming a source and a drain region in the active layer by ion doping using the gate structure as an anti-doping layer; Depositing nickel on the entire surface of the resultant material on which the source and drain regions are formed to form a nickel layer; And Depositing a metal over the nickel layer to form a metal capping layer and annealing the metal layer to form a metal silicide layer. The method of claim 5, The metal deposition process is a semiconductor device manufacturing method, characterized in that in-situ (in-situ) proceeds. The method of claim 6, For rapid thermal silicidation (RTS) of the nickel layer, Method for manufacturing a semiconductor device, characterized in that the deposition of the metal proceeds between 300 ℃ to 400 ℃. The method of claim 5, The metal is cobalt (Co) manufacturing method of a semiconductor device. The method of claim 8, The annealing process is performed between 350 ° C and 450 ° C to form cobalt monosilicide (CoSi). The method of claim 5, The metal capping layer is a method of manufacturing a semiconductor device, characterized in that to form a thinner than the nickel layer. The method of claim 10, The nickel layer is formed to a thickness of 100 kHz and the metal capping layer is a method of manufacturing a semiconductor device, characterized in that formed in a thickness of 10 to 30 kHz. The method of claim 5, And pre-cleaning to remove an oxide film and impurities in a region where the nickel silicide is formed before forming the nickel layer. The method of claim 5, And depositing a TiN layer after forming the metal capping layer and before the annealing process. The method of claim 13, And removing the unreacted metal layer including the TiN layer through selective wet etching before the annealing process.

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