KR100276876B1 - How to compensate silicide lost after contact etching - Google Patents
How to compensate silicide lost after contact etching Download PDFInfo
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- KR100276876B1 KR100276876B1 KR1019980045704A KR19980045704A KR100276876B1 KR 100276876 B1 KR100276876 B1 KR 100276876B1 KR 1019980045704 A KR1019980045704 A KR 1019980045704A KR 19980045704 A KR19980045704 A KR 19980045704A KR 100276876 B1 KR100276876 B1 KR 100276876B1
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- silicide
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- lost
- etching
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 45
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000005530 etching Methods 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 238000002407 reforming Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 10
- 239000012535 impurity Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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Abstract
콘택 홀 형성을 위한 콘택 식각후 과도 식각에 의해 손실된 실리사이드를 충분히 보상해 주기 위한 것으로, 콘택의 배리어 메탈을 증착하기 전에 낮은 온도에서도 배리어 메탈과 반응하여 실리사이드 형성이 가능한 비정질 실리콘을 형성한 후 배리어 메탈을 증착하여 RTA 처리한다. 이와 같은 RTA 처리를 함으로써, 비정질 실리콘과 배리어 메탈의 접촉 부분에 실리사이드를 재형성하여 콘택 식각시 과도 식각에 의해 손실된 실리사이드를 충분히 보상해 주어 콘택 홀의 과도 식각된 부위에서 실리사이드의 균일한 두께와 균일도를 구현하여 낮은 접촉 저항을 가지게 되고, 실리사이드 재형성으로 인한 실리콘 웨이퍼의 손실을 억제할 수 있다.To sufficiently compensate for the silicide lost by the over-etching after the contact etching for forming the contact hole, the barrier metal is formed after reacting with the barrier metal even at low temperature to form silicide, before forming the barrier metal of the contact. The metal is deposited and subjected to RTA treatment. By RTA treatment, silicide is re-formed at the contact portion between amorphous silicon and the barrier metal to sufficiently compensate for the silicide lost by the over-etching during contact etching, so that the uniform thickness and uniformity of the silicide in the over-etched portion of the contact hole are achieved. It can be implemented to have a low contact resistance, it can suppress the loss of the silicon wafer due to silicide reforming.
Description
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 더욱 상세하게는 콘택 홀(contact hole) 형성을 위한 콘택 식각후 손실된 실리사이드(silicide)를 보상하는 방법에 관한 것이다.The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a method for compensating silicide lost after contact etching for forming a contact hole.
콘택의 형성은 디바이스 공정의 최종 단계로서, 수율이나 신뢰성, 특성 등을 정하는 포인트이다. 이러한 콘택 형성시 고려해야 할 사항으로 금속막의 물성, 금속막간의 합금 상태도와 물성, 금속막과 실리콘의 상호 관계, 금속막과 절연막의 상호 관계 등이 있다. 이 중에서, 콘택 형성의 최종적인 목적은 금속막과 실리콘의 접촉 부분에서 오믹 접촉을 형성하는 것이다. 이를 위한 방법 중의 하나로 실리콘과 금속막의 접촉 부분에 실리사이드를 형성하는 것이다.Formation of the contact is the final step in the device process and is the point at which yield, reliability, characteristics, and the like are determined. Considerations for forming such a contact include physical properties of the metal film, alloy state and physical properties between the metal film, mutual relationship between the metal film and silicon, and mutual relationship between the metal film and the insulating film. Among these, the final purpose of contact formation is to form ohmic contact at the contact portion of the metal film and silicon. One way to do this is to form silicide on the contact portion of silicon and the metal film.
실리사이드는 고유의 조성과 각기 다른 화학적 성질을 갖는 금속-실리콘 화합물로서, 실리콘이 부분적으로 소모되어 실리사이드-실리콘 계면은 실리콘 웨이퍼로 이동하면서 형성된다. 특히, TiSi2와 CoSi2는 매우 낮은 저항을 가지며 800℃이상에서 견디는 특징을 가지고 있다.Silicide is a metal-silicon compound having inherent composition and different chemical properties, and is formed as the silicon is partially consumed and the silicide-silicon interface moves to the silicon wafer. In particular, TiSi 2 and CoSi 2 have a very low resistance and withstand over 800 ℃.
이러한 종래의 콘택 형성을 위한 손실된 실리사이드 보상 방법을 첨부된 도 1을 참조하여 설명한다.The lost silicide compensation method for forming such a conventional contact is described with reference to FIG.
도 1에 도시한 바와 같이 실리콘 웨이퍼(1) 위에 필드 산화막(2), 게이트 산화막(3), 게이트 전극(4), 산화막 스페이스(5)를 차례로 형성한 후, 불순물을 이온 주입하여 소스/드레인 접합부(6)를 형성한다. 그리고, 실리콘 웨이퍼(1) 위에 금속막으로 티타늄(Ti)을 증착하고 가열하여 실리콘과 티타늄이 접촉된 게이트/소스/드레인 부분에 실리사이드(7)를 형성(샐리사이드 ; Salicide)한 후, 반응하지 않고 남은 티타늄을 선택적으로 제거하고, 전체 구조상에 유전층(dielectric layer)(8)을 증착한 후, 식각에 의해 유전층(8)에 소스/드레인/게이트 영역의 일부가 드러나도록 콘택 홀(9)을 만든다.As shown in FIG. 1, the field oxide film 2, the gate oxide film 3, the gate electrode 4, and the oxide film space 5 are sequentially formed on the silicon wafer 1, and impurities are ion implanted to source / drain The junction part 6 is formed. Then, titanium (Ti) is deposited on the silicon wafer 1 with a metal film and heated to form silicide 7 in the gate / source / drain portion where silicon and titanium are in contact with each other. The remaining titanium is selectively removed, and a dielectric layer 8 is deposited on the entire structure, and then the contact hole 9 is exposed to expose a portion of the source / drain / gate region in the dielectric layer 8 by etching. Make.
이때, 콘택 식각시 과도 식각(over etch)과 유전층에 비해 실리사이드의 낮은 식각 선택비로 인해 콘택 홀 부분의 실리사이드가 대부분 손실된다. 이 손실된 실리사이드를 보상하기 위해 금속막을 콘택 홀에 증착하기 전에 콘택 홀이 형성된 실리콘 웨이퍼 위에 티타늄/티타늄나이트라이드(Ti/TiN)로 된 배리어 메탈(barrier metal)(10)을 증착한 후, RTA(rapid thermal annealing) 처리함으로써 실리콘과 배리어 메탈(10)의 접촉 부분에서 손실된 실리사이드를 재형성한다. 이때, RTA 공정은 온도에 약한 유전층(8)을 보호하기 위해 낮은 온도에서 진행한다.In this case, most of the silicide in the contact hole is lost due to overetch and lower selectivity of silicide compared to the dielectric layer. In order to compensate for this lost silicide, a barrier metal 10 of titanium / titanium nitride (Ti / TiN) is deposited on the silicon wafer on which the contact hole is formed before depositing a metal film into the contact hole, followed by RTA. Rapid thermal annealing treatment rebuilds the lost silicide at the contact between silicon and barrier metal 10. At this time, the RTA process proceeds at low temperature to protect the dielectric layer 8 which is weak to temperature.
이와 같은 종래의 방법으로 실리사이드를 보상하면, 손실된 실리사이드의 보상을 위한 RTA 처리시의 온도가 유전층(8) 증착전의 실리사이드 제조시의 온도보다 낮음으로 해서 매우 얇은 실리사이드를 얻어 결과적으로 손실된 실리사이드 보상에 충분하지 않고, 과도 식각에 의해 손실된 실리사이드 재형성시 실리콘 웨이퍼의 손실로 인하여 이미 불순물 처리되어 있는 소자 특성에 영향을 줄 수 있는 인자가 부가적으로 발생할 수 있는 단점이 있다.Compensating the silicide by such a conventional method, the temperature at the time of RTA treatment for the compensation of the lost silicide is lower than the temperature at the time of silicide fabrication before the dielectric layer 8 deposition to obtain a very thin silicide resulting in loss of the silicide compensation In the case of silicide reforming lost due to excessive etching, the loss of the silicon wafer may cause additional factors that may affect the device characteristics which are already impurity treated.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 콘택 식각후 과도 식각에 의해 손실된 실리사이드를 재형성시 손실된 실리사이드를 충분히 보상해 주고 이미 불순물 처리되어 있는 소자의 특성에 영향을 주지 않도록 하는 것이다.The present invention has been made to solve such a problem, and its object is to sufficiently compensate for the lost silicide when reforming the silicide lost by the excessive etching after the contact etching and to affect the characteristics of the device which is already impurity treated. Do not give.
도 1은 종래의 콘택 식각후 손실된 실리사이드 보상 방법에 따라 형성된 반도체 소자의 일부분을 도시한 단면도이고,1 is a cross-sectional view showing a portion of a semiconductor device formed according to a silicide compensation method lost after a conventional contact etching;
도 2a 내지 도 2c는 본 발명의 일 실시 예에 따라 콘택 식각후 손실된 실리사이드 보상 방법을 도시한 공정도이다.2A to 2C are flowcharts illustrating a silicide compensation method lost after etching a contact according to an exemplary embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 콘택 홀 형성을 위한 콘택 식각후 손실된 실리사이드를 보상하기 위한 RTA 처리하기 전에, 콘택 홀이 형성된 실리콘 웨이퍼 위에 낮은 온도에서도 티타늄/티타늄나이트라이드로 된 배리어 메탈과 반응하여 실리사이드를 형성하기 쉬운 비정질 실리콘(amorphous Si ; α-Si)을 형성한 후 티타늄/티타늄나이트라이드로 된 배리어 메탈을 증착하여 RTA 처리하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a barrier of titanium / titanium nitride even at low temperatures on a silicon wafer on which contact holes are formed, prior to RTA treatment to compensate for lost silicide after contact etching for forming contact holes. After forming an amorphous silicon (a-Si) that reacts easily with the metal to form a silicide, a barrier metal of titanium / titanium nitride is deposited to perform RTA treatment.
이하, 첨부된 도면을 참조로 하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 일 실시예에 따라 콘택 식각후 손실된 실리사이드의 보상 방법을 공정 순서에 따라 도시한 실리콘 웨이퍼의 단면도이다.2A to 2C are cross-sectional views of silicon wafers in a process sequence illustrating a method of compensating for silicide lost after etching a contact according to an exemplary embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이 실리콘 웨이퍼(21) 위에 필드 산화막(22), 게이트 산화막(23)을 순차적으로 형성한 후, 폴리실리콘을 증착 및 패턴화하여 게이트 전극(24)을 형성하고, 상기 게이트 전극(24)의 측벽에 산화막 스페이스(25)를 형성한 상태에서 상기 게이트 전극(24)과 산화막 스페이스(25)를 마스크로 하여 N+또는 P+형 불순물을 이온 주입하여 소스/드레인 접합부(26)를 형성한다.First, as shown in FIG. 2A, the field oxide film 22 and the gate oxide film 23 are sequentially formed on the silicon wafer 21, and then polysilicon is deposited and patterned to form the gate electrode 24. A source / drain junction portion is formed by ion implanting N + or P + type impurities using the gate electrode 24 and the oxide film space 25 as a mask while the oxide film space 25 is formed on the sidewall of the gate electrode 24. (26) is formed.
그리고, 도 2b에 도시한 바와 같이 상기 실리콘 웨이퍼(21)에 티타늄, 텅스텐(W), 몰리브듐(Mo) 등의 금속막(27)을 증착하고 가열하여 실리콘(21)과 금속막(27)이 접촉된 게이트/소스/드레인 부분에 실리사이드(28)를 형성한다.As shown in FIG. 2B, a metal film 27, such as titanium, tungsten (W), or molybdium (Mo), is deposited and heated on the silicon wafer 21 to heat the silicon 21 and the metal film 27. ) Forms a silicide 28 in the gate / source / drain portion in contact.
이후, 도 2c에 도시한 바와 같이 반응하지 않고 남은 금속막(27)을 선택적으로 제거하고, 전체 구조상에 유전층(29)을 증착한 후, 상기 유전층(29)을 반응성 이온 에칭(RIE ; reactive ion etching)에 의해 실리사이드(28)를 식각 정지막으로 하여 소스/드레인/게이트 영역의 일부가 드러나도록 콘택 홀(30)을 만든다. 이때, 콘택 식각시 과도 식각과 유전층에 비해 실리사이드의 낮은 식각 선택비로 인해 콘택 홀 부분의 실리사이드가 대부분 손실된다.Thereafter, as illustrated in FIG. 2C, the remaining metal film 27 that is not reacted is selectively removed, the dielectric layer 29 is deposited on the entire structure, and the dielectric layer 29 is then reacted with reactive ion etching (RIE). The contact hole 30 is formed to expose a part of the source / drain / gate region by using the silicide 28 as an etch stop layer by etching. In this case, silicides in the contact hole portions are mostly lost due to the excessive etching and the low etching selectivity of the silicides compared to the dielectric layer.
그리고, 상기 콘택 홀(30) 부분에 손실된 실리사이드를 보상하기 위해 먼저, 콘택 홀이 형성된 유전층 상부에 화학 기상 증착법(CVD ; chemical vapor deposition)에 의해 비정질 실리콘(31)을 형성한 후, 티타늄/티타늄나이트라이드로 된 배리어 메탈(32)을 증착한다. 이때, 티타늄/티타늄나이트라이드 대신에 코발트(Co)나 텅스텐으로 된 배리어 메탈을 증착할 수도 있다. 그 후, 낮은 온도에서 RTA 처리하여 콘택 홀의 배리어 메탈과 비정질 실리콘의 접촉 부분에서 낮은 온도에서 배리어 메탈과 반응하기 쉬운 비정질 실리사이드에 의해 실리사이드를 재형성하여 손실된 실리사이드를 보상한다.In order to compensate for the silicide lost in the contact hole 30, first, amorphous silicon 31 is formed on the dielectric layer on which the contact hole is formed by chemical vapor deposition (CVD), and then titanium / A barrier metal 32 of titanium nitride is deposited. In this case, a barrier metal of cobalt (Co) or tungsten may be deposited instead of titanium / titanium nitride. RTA treatment is then performed at low temperatures to regenerate the silicide by amorphous silicides that are likely to react with the barrier metal at low temperatures at the contact portions of the barrier metal and the amorphous silicon in the contact holes to compensate for the lost silicide.
이와 같이 본 발명은 콘택 식각후 손실된 실리사이드를 보상하는 공정에서 비정질 실리콘을 형성한 후 배리어 메탈을 증착하여 RTA 처리함으로써, 비정질 실리콘과 배리어 메탈의 접촉 부분에 실리사이드를 재형성하여 콘택 식각시 손실된 실리사이드를 균일한 두께와 균일도(uniformity)로 구현하여 낮은 접촉 저항을 가지게 되고, 손실된 실리사이드의 재형성으로 인한 실리콘 웨이퍼의 손실을 억제할 수 있다.As described above, the present invention forms amorphous silicon in the process of compensating for the loss of silicide after contact etching, and then deposits a barrier metal to RTA to re-form silicide at the contact portion between the amorphous silicon and the barrier metal, thereby losing the contact. The silicide may be formed to have a uniform thickness and uniformity to have a low contact resistance, and to suppress the loss of the silicon wafer due to the reformation of the lost silicide.
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