KR100604916B1 - Forming method for PVD cobalt salicide layer and manufacturing method for a semiconductor device using the forming method - Google Patents

Abstract

A method of forming a PVD cobalt salicide film and a method of manufacturing a semiconductor device using the same are described. In the method of forming a PVD cobalt salicide film according to an embodiment of the present invention, a cobalt film is first formed on a semiconductor substrate on which a silicon surface is exposed using physical vapor deposition, and then a vacuum deposition or deposition process of a thin film containing impurities. Using to form a thin impurity layer on the cobalt film. Then, the silicon surface reacts with the cobalt film to form a CoSi film on the silicon surface. The first heat treatment is performed, and then a strip process of removing the unreacted cobalt film in the first heat treatment step is performed. The second heat treatment is performed such that the silicon surface and the CoSi film react to form a CoSi ₂ film, thereby forming a PVD cobalt salicide film which does not cause agglomeration.

Cobalt, Sallyside, Physical Vapor Deposition, Agglomeration

Description

Forming method for PVD cobalt salicide layer and manufacturing method for a semiconductor device using the forming method}

1 is a SEM photograph showing the disconnection of PVD cobalt salicide gate line due to agglomeration.

2A through 2E are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device including a PVD cobalt salicide layer according to a preferred embodiment of the present invention in a process sequence.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a physical vapor deposition cobalt self-aligned silicide layer and a method of manufacturing a semiconductor device using the method. .

Along with the demand for increasing the integration density of semiconductor devices, the demand for semiconductor devices operating at high speed and low power consumption is continuously increasing. The increase in the degree of integration is achieved through the miniaturization of various elements constituting the semiconductor device, such as the size of the pattern, for example, the width of the gate line, the junction depth of the source / drain regions, and the short area of the contact. However, the miniaturization of such a pattern increases the resistance of the semiconductor device. When the resistance is increased, the operation speed of the semiconductor device is slowed down, and the power consumption increases.

In order to solve this problem, a method of using a metal silicide, which is a compound of metal and silicon, has been proposed in place of the existing polysilicon wiring. Currently, tungsten silicide, titanium silicide, cobalt silicide and the like have been studied and used as metal silicides. Among them, cobalt silicide is widely used in semiconductor devices requiring high speed operation, low power consumption, and / or high integration because of its low specific resistance and thermal and chemical stability.

The method of forming the cobalt salicide film can be roughly divided into the physical vapor deposition (PVD) cobalt salicide film formation method and the chemical vapor deposition (CVD) cobalt salicide film formation method, depending on the method of forming the cobalt film. In the former case, a sputtering method, which is one of physical vapor deposition methods, is used to form a cobalt film.

In the PVD cobalt salicide film forming method according to the prior art, first, a capping film such as a cobalt film and a titanium nitride film is sequentially formed on the silicon surface of a semiconductor substrate using a sputtering method. When the resultant material is primarily heat treated, cobalt and silicon react to form a CoSi film. The stripping process is performed to remove the capping film and the unreacted cobalt film, and then a second heat treatment process is performed to form CoSi ₂ having a low specific resistance. Since the PVD cobalt salicide film forming method forms a cobalt film by sputtering a target formed of cobalt in a vacuum state, almost no impurities are present in the deposited cobalt film, and the titanium nitride film is deposited in-situ on the cobalt film. There is an advantage that almost no interfacial oxide film or the like is produced. Therefore, PVD cobalt salicide film has an advantage of having low specific resistance.

However, due to the miniaturization of the pattern due to the increase in the degree of integration, the PVD cobalt salicide layer according to the prior art has a serious problem. For example, as the width of the gate line becomes smaller than 90 nm, the PVD cobalt salicide film formed on the gate line is agglomerated in a secondary heat treatment process or a subsequent heat treatment step. When agglomeration occurs, the sheet resistance of the PVD cobalt salicide film increases, which hinders high speed operation. In addition, when the agglomeration phenomenon is severe, disconnection of the PVD cobalt salicide film may be caused. FIG. 1 is a SEM photograph showing a PVD cobalt salicide film in which disconnection is caused by agglomeration when the gate line has a width of 53 nm.

One method proposed to solve the agglomeration problem caused by the miniaturization of the pattern is to form a nickel salicide film or a nickel tantalum salicide film on the gate line instead of the PVD cobalt salicide film. . The nickel salicide film or the nickel tantalum salicide film, although formed on a gate line having a width of less than 90 nm, has the advantage that no agglomeration phenomenon occurs in a subsequent heat treatment process. However, since a phase change occurs in the NiSi film to the NiSi ₂ film in a subsequent heat treatment process, the sheet resistance of the salicide film is rather increased. Therefore, in order to use a nickel salicide film or a nickel tartalum salicide film, a change to a subsequent heat treatment process must be accompanied. If the subsequent heat treatment process is changed, it is necessary to invest a lot of time and money to apply the nickel salicide film or nickel tantalum salicide film formation method to the mass production process because re-investment for production equipment is required.

The technical problem to be achieved by the present invention is to form a PVD cobalt salicide film which can prevent the cobalt salicide film on the gate line from being agglomerated in a subsequent heat treatment process despite the miniaturization of a pattern, and a method of manufacturing a semiconductor device using the same. To provide.

Another technical problem to be achieved by the present invention is to provide a method of forming a PVD cobalt salicide film and a method of manufacturing a semiconductor device using the same, in which the manufacturing process is simple and the equipment investment cost can be reduced by using an existing production equipment.

In the method of forming a cobalt salicide film according to an embodiment of the present invention for achieving the above technical problem, first, a cobalt film is formed on the semiconductor substrate on which a silicon surface is exposed using physical vapor deposition. And impurity on the cobalt film by artificially breaking the vacuum of the process chamber to induce an oxide layer and / or a contaminant layer or to form a thin film of a material containing carbon (C) or oxygen (O) on the cobalt film. Form a layer. In the latter case, the thin film may be formed of a material containing SiOC, which is a material having a low dielectric constant. In addition, although an optional process, a capping layer may be further formed on the cobalt layer. And performing a first heat treatment process for heat treating the semiconductor substrate so that the silicon surface and the cobalt film react to form a CoSi film on the silicon surface, and then removing the cobalt film that has not reacted in the first heat treatment step. A strip process is performed. In addition, a second heat treatment process is performed to heat-treat the semiconductor substrate such that the silicon surface and the CoSi film react to form a CoSi ₂ film.

A method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above technical problem, first to form a gate electrode structure including a gate oxide film pattern, a polysilicon film pattern and sidewall spacers on a silicon substrate. A source / drain region is formed in the silicon substrate on both sides of the gate electrode structure. A cobalt film is formed on the silicon substrate and the gate electrode structure using physical vapor deposition, and an impurity layer is formed on the cobalt film in the same manner as described above. And performing a first heat treatment process for heat treating the silicon substrate to form a CoSi film on the polysilicon layer pattern and the source / drain region by reacting the polysilicon layer pattern and the silicon of the source / drain region with the cobalt layer. Next, a strip process of removing the cobalt film that has not reacted in the first heat treatment step is performed. A second heat treatment process is performed to heat-treat the silicon substrate so that the CoSi ₂ film is formed by reacting the polysilicon film pattern and the silicon in the source / drain region with the CoSi film.

Specific details of other embodiments are included in the detailed description and the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided by way of example so that the technical spirit of the present invention can be thoroughly and completely disclosed, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thickness of layers and / or the size of regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2A-2E illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention in a process sequence. In this embodiment, a process of forming a cobalt salicide film in the gate line pattern and the source / drain regions is illustrated, but the present embodiment may be similarly applied to other components of the semiconductor device including the cobalt salicide film.

Referring to FIG. 2A, a silicon substrate 100 is first provided. A silicon isolation region (not shown) defining an active region is formed in the silicon substrate 100. The device isolation region may be, for example, a shallow trench isolation (STI) region.

Subsequently, a MOS field effect transistor (MOSFET) including a gate electrode structure 110 and a source / drain region 120 is manufactured using a conventional MOS transistor forming process on the silicon substrate 100. The gate electrode structure 110 may be formed on, for example, a gate oxide layer pattern 112, a polysilicon layer pattern 114 stacked on the gate oxide layer pattern, and sidewalls of the gate oxide layer pattern 112 and the polysilicon layer pattern 114. The spacer 116 may be formed. In some cases, the gate electrode structure 110 may further include a hard mask layer pattern (not shown) formed on the polysilicon layer pattern 114. The source / drain region 120 may be formed of a lightly doped drain (LDD) structure as illustrated, but is not limited thereto.

Referring to FIG. 2B, the PVD cobalt film 130 is formed on the resultant by sputtering. The sputtering process for forming the PVD cobalt film 130 proceeds in a vacuum chamber. Before the PVD cobalt film 130 is formed, a wet cleaning process using dilute hydrofluoric acid (HF) or the like may be performed to remove impurities such as a natural oxide film. The PVD cobalt layer 130 may be formed on at least the source / drain region 120 and the polysilicon layer pattern 114. The PVD cobalt film 130 may be formed to a thickness of about 50 to about 200 microns.

An impurity layer 140 is formed on the PVD cobalt film 130. The impurity layer 140 is preferably formed as thin as possible. For example, the impurity layer 140 may be formed to a thickness of about 5-30 kPa. In addition, the impurity layer 140 may be uniformly formed on the entire surface of the PVD cobalt layer 130 so as to effectively prevent agglomeration in a subsequent heat treatment process or a subsequent heat treatment process.

One method of forming the impurity layer 140 is to artificially break the vacuum after forming the PVD cobalt film 130. When the vacuum is broken, the PVD cobalt film 130 is exposed to the atmosphere. As a result, a thin film of cobalt oxide film and / or contaminants in the atmosphere is formed on the PVD cobalt film 130. The thin film by the cobalt oxide film and / or contaminants serves as the impurity layer 140.

Another method of forming the impurity layer 140 is to form a thin film 140 containing an impurity such as carbon and / or oxygen on the PVD cobalt film 130, i.e., an impurity layer, while maintaining a vacuum. will be. Carbon and / or oxygen serve as an inhibitor to prevent agglomeration from occurring while remaining in the cobalt salicide film. For example, the thin film 140 may be formed of a low dielectric constant SiOC-based material.

Another method of forming the impurity layer 140 is to form the impurity layer 140 by implanting impurities into the PVD cobalt film 130 using an ion implantation process. The implanted impurities may be, for example, materials such as carbon (c) or nitrogen (N) or mixtures thereof.

2B, a capping film 150 is formed on the impurity layer 140. The capping film 150 forming process is an optional process. For example, when the impurity layer 140 forming process and the subsequent primary heat treatment process are performed in-situ in a vacuum state, the capping film 140 forming process may be omitted. The capping film 150 may be formed of a single film of a titanium film or a titanium nitride film, or a composite film of a titanium film and a titanium nitride film. More preferably, the capping film 150 is formed of a single film of a titanium film. The titanium film 150 may be, for example, formed to a thickness of about 50 kPa to about 300 kPa.

Referring to FIG. 2C, a first heat treatment process is performed to heat-process a semiconductor device on which a PVD cobalt film 130, an impurity layer (not shown), and a titanium film 150 are deposited. The first heat treatment process may be performed by performing an RTS process while continuously purging an atmosphere gas such as nitrogen gas or an inert gas, or by performing an RTS process in an ultra-high vacuum state without an atmosphere gas. In some cases, the RTS process may be performed in a stacked anneal oven. Since the impurity layer is included in the first cobalt silicide layer 135 formed as a result of the first heat treatment process, the illustration of the impurity layer is omitted in FIG. 2C.

The first heat treatment step may be performed at a temperature of about 300 ° C. to 600 ° C., more preferably at about 400 ° C. to 500 ° C. for about 90 seconds. The temperature at which cobalt and silicon react to cause phase transition to Co ₂ Si or CoSi is known to be between about 400 ° C and 450 ° C. In addition, the temperature causing the phase transition to CoSi ₂ is known to be at least about 600 ℃. Therefore, when the heat treatment is performed under the above-described temperature conditions, the PVD cobalt and the silicon 114 and 120 react with each other to form a Co ₂ Si film or a CoSi film 135 (hereinafter referred to as a 'first cobalt silicide film'). do.

Referring to FIG. 2D, a strip process of removing the titanium film 150 and the unreacted PVD cobalt film 130a is performed. The strip process may be performed using a wet etching method using a metal etchant such as phosphoric acid, acetic acid and / or nitric acid. As a result, the first cobalt silicide layer 135 and the spacer 116 of the gate electrode structure are exposed on the surface of the silicon substrate 100.

Referring to FIG. 2E, a second cobalt silicide (CoSi ₂ ) film 135a is formed by performing a second heat treatment on the silicon substrate 100. The secondary heat treatment step is performed for about 30 seconds at a temperature of about 600 ℃ to 900 ℃, preferably about 800 ℃ to 900 ℃. By the second heat treatment, the first cobalt silicide layer 135 and the polysilicon pattern 114a of the gate line structure 110a and the silicon 120a of the source / drain regions react to form a CoSi ₂ layer 135a. Causes a phase transition. At this time, not all of the silicon of the source / drain region 120b should be consumed by the newly formed CoSi ₂ film 135a. That is, as shown, a portion of the source / drain region 120b must remain under the CoSi ₂ film 135a. As a result of the above process, a second cobalt silicide (CoSi ₂ ) film 135a is formed on the top surface of the gate electrode structure and the top surface of the source / drain region. Although not shown, since all or part of the impurity layer remains inside the second cobalt silicide layer 135a, it is possible to prevent a phenomenon in which particles of the second cobalt silicide layer 135a grow and agglomerate. .

Thereafter, a semiconductor device such as a high speed memory device is completed by performing a conventional semiconductor device manufacturing process.

According to the present invention, after the PVD cobalt film is formed, an impurity layer is artificially formed thereon, whereby agglomeration phenomenon can be prevented from occurring in the cobalt salicide film. Therefore, the sheet resistance of the gate line due to the agglomeration of the cobalt salicide film or the disconnection of the cobalt salicide gate line can be prevented.

Further, according to the present invention, after forming the PVD cobalt film, the vacuum is broken to form a thin film of an oxide film or a contaminant on the PVD film, or a thin film of a material containing C or O using a conventional thin film forming method. Agglomeration phenomenon can be prevented. Therefore, according to the present invention, since the material widely used and the conventional semiconductor manufacturing process are applied as it is, the manufacturing process is simple and the equipment investment cost can be reduced.

Claims (17)

Forming a cobalt film on the semiconductor substrate having the silicon surface exposed by using physical vapor deposition; Forming an impurity layer on the cobalt film; A first heat treatment step of heat treating the semiconductor substrate such that a CoSi film is formed on the silicon surface by reacting the silicon surface with the cobalt film; A stripping step of removing the cobalt film not reacted in the first heat treatment step; And And heat treating the semiconductor substrate such that the silicon surface and the CoSi film react to form a CoSi ₂ film. The method of claim 1, wherein the impurity layer is a surface oxide layer formed by breaking a vacuum around the semiconductor substrate on which the cobalt film is formed and / or a contaminant layer formed by an atmospheric material. The method of claim 1, wherein the impurity layer is a thin film formed of a material containing carbon or oxygen. 4. The method of claim 3, wherein the thin film is formed to a thickness of 5 to 30 GPa. The method of claim 3, wherein the thin film is formed of a low-k SiOC (SiOC) -based material having a small dielectric material. delete The method of claim 1, Forming a capping layer on the impurity layer after the impurity layer forming step; And removing the capping layer together in the stripping step. The method of claim 1, wherein the cobalt layer is formed to a thickness of 50 to 200 kPa. The method of claim 1, wherein the first heat treatment step and the second heat treatment step are performed by a Rapid Thermal Silicidation (RTS) process, The RTS process is performed by a rapid thermal annealing process or a furnace process performed in a stacked anneal oven, which is performed by purging an inert gas or in a super vacuum atmosphere. A method of forming a cobalt salicide film. The method of claim 9, And the first heat treatment step and the second heat treatment step are performed in an atmosphere in which an inert gas is present or in an ultra-vacuum state in which there is no atmosphere gas. The method of claim 9, The first heat treatment step is carried out at a temperature of 300-600 ℃, the second heat treatment step is carried out at a temperature of 600-900 ℃, the method of forming a cobalt salicide film. Forming a gate electrode structure including a gate oxide pattern, a polysilicon layer pattern, and sidewall spacers on the silicon substrate; Forming a source / drain region in the silicon substrate on both sides of the gate electrode structure; Forming a cobalt film on the silicon substrate and the gate electrode structure by using physical vapor deposition; Forming an impurity layer on the cobalt film; A first heat treatment step of heat treating the silicon substrate such that a CoSi film is formed on the polysilicon layer pattern and the source / drain region by reacting the polysilicon layer pattern and the silicon of the source / drain region with the cobalt layer; A stripping step of removing the cobalt film not reacted in the first heat treatment step; And And heat treating the silicon substrate to form a CoSi ₂ film by reacting the polysilicon layer pattern and the silicon in the source / drain region with the CoSi layer. The method of claim 12, wherein the impurity layer is a surface oxide layer formed by breaking a vacuum around the silicon substrate on which the cobalt film is formed, and / or a contamination layer formed by an atmospheric material. The method of claim 12, wherein the impurity layer is a thin film formed of a material containing carbon or oxygen. The method of manufacturing a semiconductor device according to claim 14, wherein the thin film is formed to a thickness of 5 to 30 GPa. The method of claim 14, wherein the thin film is formed of a low-k SiOC (SiOC) -based material having a small dielectric material. delete

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