CN100414675C - Gap wall removing method and method for mfg. MOS - Google Patents
Gap wall removing method and method for mfg. MOS Download PDFInfo
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- CN100414675C CN100414675C CNB2005100082835A CN200510008283A CN100414675C CN 100414675 C CN100414675 C CN 100414675C CN B2005100082835 A CNB2005100082835 A CN B2005100082835A CN 200510008283 A CN200510008283 A CN 200510008283A CN 100414675 C CN100414675 C CN 100414675C
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Abstract
The present invention relates to a method for removing a gap wall, which is suitable for using after a metal oxide semiconductor transistor is formed, wherein the metal oxide semiconductor transistor comprises a grid arranged on a substrate, a gap wall positioned on one side wall of the grid, and a source region and a drain region which are arranged in the substrate on one side of the gap wall. The method for removing a gap wall adopts wet type etching process in dark environment, and thereby, the source region and the drain region of the metal oxide semiconductor transistor can not be damaged when the gap wall is removed. The present invention also relates to a method for manufacturing the metal oxide semiconductor transistor.
Description
Technical field
The present invention relates to a kind of process for manufacture of semiconductor device, particularly relate to a kind of method that removes and transistorized manufacture method of metal-oxide semiconductor (MOS) (metal-oxide-semiconductor transistor is hereinafter to be referred as " MOS ") of clearance wall.
Background technology
Metal oxide semiconductor transistor is one of important semiconductor element.Figure 1A illustrates the generalized section into existing a kind of metal oxide semiconductor transistor.Please refer to Figure 1A, metal oxide semiconductor transistor 120 generally is disposed in the substrate 100 (for example being P-Si), and this metal oxide semiconductor transistor 120 comprises grid structure 122, source area 124s, drain region 124d and clearance wall 126.Wherein, grid structure 122 is positioned in the substrate 100, and grid structure 122 is gate dielectric layer 122a and grid layer 122b by substrate 100 in regular turn.Source area 124s and drain region 124d are arranged in grid structure 122 substrate on two sides 100, and clearance wall 126 is positioned on the sidewall of grid structure 122.
On the other hand; in order effectively to improve the electron hole mobility (mobility) in channel region (zones of grid structure 122 belows); after metal oxide semiconductor transistor 120 completes; usually also can utilize phosphoric acid to carry out wet etching so that clearance wall 126 is removed; and in metal oxide semiconductor transistor 120 and substrate 100, cover one deck strained layer 130 (strain layer), to adjust the lattice structure (shown in Figure 1B) of substrate 100.
Yet, because transmission can be gone up on the PN composition surface (PN junction) of source area 124s and drain region 124d and substrate 100 in the electron hole, so when using phosphoric acid to remove clearance wall 126, the electron hole on phosphoric acid and PN composition surface, under the environment that light exists, can produce photochemical reaction (photo-electrochemical reaction), and then cause the damage of source area 124s and drain region 124d, this phenomenon is especially even more serious with nmos pass transistor.Fig. 2 is a nmos pass transistor under the environment that light exists, when using phosphoric acid to remove clearance wall, and the photo figure of the scanning type electron microscope (SEM) that source area and drain region are damaged.As shown in Figure 2, above-mentioned source area 124s that has completed and drain region 124d, when removing clearance wall 126 under the environment that light exists, source area 124s and drain region 124d can wreck because of photochemical reaction, and form cavity 128 as shown in Figure 2.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of method that removes of clearance wall is being provided, and can avoid when removing clearance wall, and the source area and the drain region of metal oxide semiconductor transistor are damaged.
Another object of the present invention provides a kind of manufacture method of metal oxide semiconductor transistor, and the method for utilizing above-mentioned clearance wall to remove can avoid source area and drain region to be damaged.
The present invention proposes a kind of method that removes of clearance wall, is suitable for after the metal oxide semiconductor transistor formation.Metal oxide semiconductor transistor comprises source area and the drain region that is arranged in suprabasil grid structure, is positioned at the clearance wall on the grid structure sidewall and is positioned at the substrate of clearance wall side.The method that removes of clearance wall is carried out wet etch process under unglazed environment.
In an embodiment of the present invention, the material of clearance wall for example is a silicon nitride.
In an embodiment of the present invention, the employed etchant of wet etch process for example is a phosphoric acid.
The present invention proposes a kind of manufacture method of metal oxide semiconductor transistor, at first forms grid structure in substrate, and this grid structure is gate dielectric layer and grid layer by substrate in regular turn.Then, the sidewall in grid structure forms clearance wall.Come again, in the substrate of clearance wall side, form source area and drain region.Continue it, under unglazed environment, carry out wet etch process, to remove the clearance wall that is positioned on the grid structure sidewall.Afterwards, form strained layer with overlies gate structure and substrate in substrate, wherein when forming strained layer, this strained layer is in order to adjust the lattice arrangement of substrate.
In an embodiment of the present invention, the material of clearance wall for example is a silicon nitride.
In an embodiment of the present invention, the employed etchant of wet etch process for example is a phosphoric acid.
In an embodiment of the present invention, the material of strained layer for example is silica, silicon nitride.
In an embodiment of the present invention, after forming grid structure and before forming clearance wall, also can in the substrate of grid structure side, form lightly mixed drain area (LDD).
Because the present invention is removing the clearance wall that is positioned on the grid structure sidewall under the unglazed environment, thus can avoid producing photochemical reaction at source area and drain region, and then avoid source area and drain region to be damaged.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and the conjunction with figs. formula elaborates.
Description of drawings
Figure 1A is the generalized section of existing a kind of metal oxide semiconductor transistor.
Figure 1B is for being coated with the generalized section of the metal oxide semiconductor transistor of strained layer on it.
Fig. 2 is a nmos pass transistor under the environment that light exists, when using phosphoric acid to remove clearance wall, and the photo figure of the scanning type electron microscope (SEM) that source area and drain region are damaged.
Fig. 3 A is the manufacturing process generalized section of a kind of metal oxide semiconductor transistor in the embodiments of the invention to Fig. 3 F.
Fig. 4 be nmos pass transistor under unglazed environment, use phosphoric acid to remove clearance wall, the transistorized scanning type electron micrograph of the metal-oxide semiconductor of gained figure.
The simple symbol explanation
100: substrate
120: metal oxide semiconductor transistor
122: grid structure
122a: gate dielectric layer
122b: grid layer
124s: source area
124d: drain region
126: clearance wall
128: the cavity
130: strained layer
200: substrate
220: grid structure
222: gate dielectric layer
224: grid layer
240: clearance wall
260s: source area
260d: drain region
262: light doping section
280: strained layer
300: no luminous environment
Embodiment
Fig. 3 A is the manufacturing process generalized section of a kind of metal oxide semiconductor transistor in the embodiments of the invention to Fig. 3 F.Please refer to Fig. 3 A, at first, in substrate 200, form grid structure 220, this grid structure 220 is gate dielectric layer 222 and grid layer 224 by substrate 200 in regular turn, wherein, the formation method of grid structure 220 for example be in substrate 200, form earlier the grid dielectric materials layer with gate material layers after, produce grid structure 220 with little shadow and engraving method again.Wherein, the material of gate dielectric layer 222 for example is a silica, and the material of grid layer for example is polysilicon or metal silicide.
Afterwards, please refer to Fig. 3 B, in the substrate 200 of grid structure 220 sides, form light doping section 262.The method that forms for example can be utilized thermal diffusion method or ion implantation, will be injected into the substrate 200 of grid structure 220 sides with the alloy of substrate 200 different dopant profile.In one embodiment, substrate for example is a p type silicon, and alloy for example is n type alloy (for example being phosphorus or arsenic).
Then, please refer to Fig. 3 C, sidewall in grid structure 220 forms clearance wall 240, the formation method of above-mentioned clearance wall 240 for example is to cover a spacer material layer earlier on grid structure 220, make clearance wall 240 with the anisotropic etching legal system again, this anisotropic etching rule is as for utilizing plasma etching.In addition, the material of clearance wall 240 for example is a silicon nitride.
Come, please refer to Fig. 3 D, form source area 260s and drain region 260d in the substrate 200 of clearance wall 240 sides, the light doping section 262 that be positioned at clearance wall 240 belows this moment is that a lightly mixed drain area (LDD) is to prevent short-channel effect.Wherein, the formation method of source area 260s and drain region 260d for example for utilizing thermal diffusion method or ion implantation, will diffuse into the substrate 200 of clearance wall 240 sides with the alloy (dopant) of substrate 200 different kenels.In one embodiment, substrate for example is a p type silicon, and alloy for example is n type alloy (for example being phosphorus or arsenic).
Then, in order effectively to improve the electron hole mobility (mobility) in channel region (zones of grid structure 220 belows), can adjust the lattice arrangement of substrate 200, it is described in detail as follows.
Please refer to Fig. 3 E, can carry out a wet etch process 300 times, to remove the clearance wall 240 that is positioned on grid structure 220 sidewalls in no luminous environment.In a preferred embodiment of the present invention, the etchant that wet etch process is used for example is a phosphoric acid, and do not have luminous environment 300 for example for to carry out above-mentioned wet etch process, or in other can block the space of light or install, carry out above-mentioned wet etch process at a dark place.
At this moment, utilize the scanning type electron microscope to take under unglazed environment, use phosphoric acid to remove clearance wall, the transistorized photo figure of the metal-oxide semiconductor of gained as shown in Figure 4.As shown in Figure 4, when using phosphoric acid to remove clearance wall 240, photochemically reactive generation no luminous environment 300 times, can not facilitated in the PN interface electrons transmitted hole between source area 260s and drain region 260d and the substrate 200.Therefore, in removing the process of clearance wall, source area 260s and drain region 260d still can be kept perfectly and not be destroyed.Compared to existing result (as shown in Figure 2), remove clearance wall 240 for 300 times at no luminous environment and can effectively solve existing problem.
Afterwards, please refer to Fig. 3 F, form strained layer 280 with overlies gate structure 220 and substrate 200 in substrate 200, wherein when forming strained layer 280, strained layer 280 is in order to adjust the lattice arrangement of substrate 200.In a preferred embodiment of the present invention, the material of strained layer 280 for example is silica (SiO), silicon nitride (SiN) or other suitable material.Because the lattice distance of silica or silicon nitride strained layer is big than the lattice distance of the p type silicon of substrate 200, so when forming strained layer 280, the p type silicon crystal lattice of substrate 200 can be a benchmark with the lattice of strained layer 280, carries out the adjustment of lattice structure.And when the lattice distance of the p of substrate 200 type silicon increases along with the lattice distance of strained layer 280, can make the electron hole promote in the mobility (mobility) of substrate 200, and then increasing electric current, and the operating characteristic of promotion metal oxide semiconductor transistor.
Certainly, the above embodiments are the wherein a kind of application that removes the method for clearance wall of the present invention, are not in order to limit application category of the present invention.In addition, though disclose the manufacturing process of the metal oxide semiconductor transistor with lightly mixed drain area in the above-described embodiments, the present invention also is suitable for not having the manufacturing process of the metal oxide semiconductor transistor of lightly mixed drain area.
In sum, the present invention has following advantage at least:
When (1) the present invention used wet etch process to remove clearance wall under no luminous environment, source area and drain region can not damaged, and can promote the rate of finished products of making metal oxide semiconductor transistor.
(2) the present invention utilizes strained layer to adjust the lattice distance of substrate, can promote the electron mobility of electronics in substrate, and then promotes the operating characteristic of metal oxide semiconductor transistor.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (8)
1. the method that removes of a clearance wall, after being applicable to that a metal oxide semiconductor transistor forms, this metal oxide semiconductor transistor comprises an one source pole district and a drain region that is arranged in a suprabasil grid structure, is positioned at the clearance wall on this grid structure sidewall and is positioned at this substrate of this clearance wall side; The method that removes of this clearance wall is carried out a wet etch process under unglazed environment.
2. the method that removes of clearance wall as claimed in claim 1, wherein the material of this clearance wall comprises silicon nitride.
3. the method that removes of clearance wall as claimed in claim 2, wherein the employed etchant of this wet etch process comprises phosphoric acid.
4. the manufacture method of a metal oxide semiconductor transistor comprises:
Form a grid structure in a substrate, this grid structure is a gate dielectric layer and a grid layer by this substrate in regular turn;
Sidewall in this grid structure forms a clearance wall;
In this substrate of this clearance wall side, form an one source pole district and a drain region;
Under unglazed environment, carry out a wet etch process, to remove this clearance wall that is positioned on this grid structure sidewall; And
Form a strained layer in this substrate, cover this grid structure and this substrate, wherein when forming this strained layer, this strained layer is in order to adjust the lattice arrangement of this substrate.
5. the manufacture method of metal oxide semiconductor transistor as claimed in claim 4, wherein the material of this clearance wall comprises silicon nitride.
6. the manufacture method of metal oxide semiconductor transistor as claimed in claim 5, wherein the employed etchant of this wet etch process comprises phosphoric acid.
7. the manufacture method of metal oxide semiconductor transistor as claimed in claim 4, wherein the material of this strained layer comprises silica or silicon nitride.
8. the manufacture method of metal oxide semiconductor transistor as claimed in claim 4 wherein after forming this grid structure and before this clearance wall of formation, also is included in this substrate of this grid structure side and forms lightly mixed drain area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100082835A CN100414675C (en) | 2005-02-21 | 2005-02-21 | Gap wall removing method and method for mfg. MOS |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100082835A CN100414675C (en) | 2005-02-21 | 2005-02-21 | Gap wall removing method and method for mfg. MOS |
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| CN100414675C true CN100414675C (en) | 2008-08-27 |
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| CN100466195C (en) * | 2006-09-21 | 2009-03-04 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4908326A (en) * | 1988-01-19 | 1990-03-13 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
| CN1393915A (en) * | 2001-06-26 | 2003-01-29 | 旺宏电子股份有限公司 | Process for preparing MOS transistor |
| US6727155B1 (en) * | 2002-12-18 | 2004-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for spin etching sidewall spacers by acid vapor |
| US6777299B1 (en) * | 2003-07-07 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removal of a spacer |
-
2005
- 2005-02-21 CN CNB2005100082835A patent/CN100414675C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4908326A (en) * | 1988-01-19 | 1990-03-13 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
| CN1393915A (en) * | 2001-06-26 | 2003-01-29 | 旺宏电子股份有限公司 | Process for preparing MOS transistor |
| US6727155B1 (en) * | 2002-12-18 | 2004-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for spin etching sidewall spacers by acid vapor |
| US6777299B1 (en) * | 2003-07-07 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removal of a spacer |
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| CN1825550A (en) | 2006-08-30 |
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