KR100541154B1 - Method of manufacturing capacitor in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. In forming a capacitor of an MPDL device in a system on chip (SOC), a plurality of protrusion patterns are formed on a semiconductor substrate in a capacitor region, and then a capacitor bottom is formed. The plate electrode is simultaneously formed of the same conductive layer as the gate electrode, but in contact with the semiconductor substrate, the capacitor dielectric film is formed on the bottom plate electrode, and the capacitor top plate electrode is formed on the dielectric film, thus requiring a complicated capacitor manufacturing process. It is highly compatible with the manufacturing process of logic devices, easily adjusts and increases the capacitance value of capacitors, and increases the refresh time by reducing leakage current.

SOC, MPDL, Capacitors

Description

Method of manufacturing capacitor in semiconductor device             

1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a conventional semiconductor device.

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21: semiconductor substrate

11C, 25C; Capacitor bottom plate electrode

12, 22: device isolation film 13, 23: oxide film

13G, 23G: gate oxide film 13C, 29: capacitor dielectric film

14, 25, 30: conductive layer 14G, 25G: gate electrode

14C, 30C: capacitor top plate electrode

15, 24, 26, 31: photoresist pattern

16, 27: LDD spacer 17D, 28D: drain

17S, 28S: source 18, 32: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, to improve the performance of a capacitor while increasing the effective surface area of a capacitor bottom plate electrode in a mixed semiconductor memory device in which logic and memory devices are mixed. The present invention relates to a capacitor manufacturing method of a semiconductor device.

In order to achieve thin, small, high performance, and low power of a system using a semiconductor device, a MRAM is a memory device such as a DRAM and a logic suitable for the memory device. It refers to a system on chip (SOC) that is implemented on a chip. Among the SOC devices, MPDL (Merged Planar DRAM & Logic) devices adopt a planar method instead of a stack method to form a capacitor at the same time when forming a gate. Therefore, the process scheme is simple and excellent compatibility with the logic device manufacturing process is one of the devices recently attracting attention.

1A to 1C are cross-sectional views of a device for explaining a capacitor manufacturing method of a conventional semiconductor device. The cell region of the MPDL device is illustrated, and the manufacturing process is compatible with the logic area, but the manufacturing process is performed in the cell area. do.

Referring to FIG. 1A, a semiconductor device 11 in which a transistor region G and a capacitor region C are defined may be used to separate an active region from an inactive region by using a conventional device isolation method such as trench isolation (STI). An element isolation film 12 is formed. The oxide film 13 is formed by performing a gate oxidation process on the surface of the semiconductor substrate 11 on which the device isolation film 12 is formed.

Referring to FIG. 1B, the conductive layer 14 is formed on the oxide film 13, and the photoresist pattern 15 is formed on the conductive layer 14. The photoresist pattern 15 defines a gate electrode region and a capacitor top plate electrode region.

Referring to FIG. 1C, the conductive layer 14 and the oxide film 13 are patterned by an etching process using the photoresist pattern 15 as an etching mask, and thus, the gate oxide film 13G and the gate electrode are formed in the transistor region C. Referring to FIG. 14G is formed, and in the capacitor region C, a capacitor dielectric film 13C and a capacitor top plate electrode 14C are formed. The photoresist pattern 15 is removed. Thereafter, a source / drain ion implantation process is performed, a lightly drain doped spacer (16) is formed on the patterned sidewall, and an LDD ion implantation process is performed to perform the drain 17D and the source 17S of the LDD structure. To form. As a result of the above process, a cell transistor including a gate electrode 14G, a drain 17D, and a source 17S is completed in the transistor region G, and the capacitor top plate electrode 14C and the capacitor dielectric material are formed in the capacitor region C. The cell capacitor consisting of the capacitor bottom plate electrode 11C made of the film 13C and the semiconductor substrate 11 is completed. An interlayer insulating film 18 is formed over the entire structure including the cell transistors and the cell capacitors. After that, a general process such as a wiring process is performed.

According to the conventional method, since the semiconductor substrate 11 is used as the capacitor bottom plate electrode 11C, a space capable of receiving charge is limited to the surface of the semiconductor substrate 11 under the capacitor dielectric film 13C. Not only there is a limit to increase the capacitance of the capacitor, but also a lot of leakage current is generated in the lower portion of the semiconductor substrate 11, there is a problem that the refresh time is short. In addition, since the same material as that of the gate oxide film 13G, for example, a thermal oxide film, is used as the capacitor dielectric film 13C, it is difficult to secure a larger capacity capacitor.

Therefore, the present invention can easily adjust and increase the capacitance value of a capacitor in a mixed semiconductor memory device in which a logic device and a memory device are mixed, and improve the performance of the capacitor by reducing the leakage current to increase the refresh time. An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: providing a semiconductor substrate in which a transistor region and a capacitor region are defined; Forming an isolation layer on the semiconductor substrate to define an active region and an inactive region; Forming at least one protrusion pattern on the semiconductor substrate in the capacitor region; Forming a gate oxide film on the semiconductor substrate in the transistor region; Forming a gate electrode on the gate oxide layer, and forming a capacitor bottom plate electrode on a semiconductor substrate of the capacitor region in which the protruding pattern is formed; Forming a source and a drain, thereby forming a transistor in the transistor region; And forming a capacitor dielectric layer and a capacitor top plate electrode on the capacitor bottom plate electrode, thereby forming a capacitor in the capacitor region.

In the protruding pattern, an oxide film is formed to a thickness of 100 to 300 kPa, a nitride film is formed to a thickness of 1000 to 3000 kPa, and the nitride film is formed using a CF ₄ / CHF ₃ / O ₂ / Ar mixed gas. The oxide layer is patterned and formed by etching the wet layer using a wet etching method using an HF solution or a BOE solution.

The gate electrode and the capacitor bottom plate electrode are formed of the same conductive layer and are in contact with the semiconductor substrate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

2A to 2D are cross-sectional views of a device for describing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention. The cell region of the MPDL device is illustrated, and the manufacturing process is compatible with the logic area but is performed in the cell area. It demonstrates centering on a manufacturing process.

Referring to FIG. 2A, a semiconductor device 21 in which a transistor region G and a capacitor region C are defined may be used to separate an active region and an inactive region by using a conventional device isolation method such as trench isolation (STI). The element isolation film 22 is formed. At least one protruding pattern 200 is formed on the semiconductor substrate 21 in the capacitor region C. The protruding pattern 200 sequentially forms the oxide film 210 and the nitride film 220, and then first patterns the nitride film 220 using a CF ₄ / CHF ₃ / O ₂ / Ar mixed gas, and then forms an HF solution or a BOE. The oxide layer 210 is removed by a wet etching method using a solution or the like to minimize etching damage of the semiconductor substrate 21. The oxide film 210 is formed to a thickness of 100 to 300 kPa, and the nitride film 220 is formed to a thickness of 1000 to 3000 kPa. As will be described later, the protruding pattern 200 serves to increase the effective surface area of the capacitor bottom plate electrode, and therefore, the thickness of these films 210 and 220 that make up the protruding pattern 200 is the capacitance required for the operation of the device. Can be adjusted in consideration of. The oxide film 23 is formed by performing a gate oxidation process on the surface of the semiconductor substrate 21 on which the device isolation film 22 and the protruding pattern 200 are formed. The oxide film 23 may typically be formed only on the surface of the semiconductor substrate 21 by a thermal oxidation process, or may be formed along the entire structure surface by an oxide deposition process. The first photoresist pattern 24 having the capacitor region C opened is formed on the oxide film 23.

Referring to FIG. 2B, the oxide layer 23 of the capacitor region C is removed by an etching process using the first photoresist pattern 24 as an etching mask, and thus, the oxide layer 23 remains only in the transistor region G. It becomes the gate oxide film 23G. The oxide layer 23 is removed by a wet etching method using an HF solution, a BOE solution, or the like to minimize the etching damage of the semiconductor substrate 21. A first conductive layer 25 is formed on the entire structure of the exposed semiconductor substrate 21 of the capacitor region C including the gate oxide film 23G and the protruding pattern 200 of the transistor region G. The second photoresist pattern 26 is formed on the layer 25. The second photoresist pattern 26 defines a gate electrode region and a capacitor bottom plate electrode region.

Referring to FIG. 2C, the first conductive layer 25 and the gate oxide film 23G are patterned by an etching process using the second photoresist pattern 26 as an etch mask, and thus, the gate oxide film ( 23G) and a gate electrode 25G are formed, and in the capacitor region C, a capacitor bottom plate electrode 25C having a concave-convex surface is formed by the protruding pattern 200 while directly contacting the semiconductor substrate 21. The second photoresist pattern 26 is removed. Thereafter, a source / drain ion implantation process is performed, a lightly drain doped spacer 27 is formed on the patterned sidewall, and an LDD ion implantation process is performed to drain the 28D and the source 28S of the LDD structure. To form. As a result of the above process, a cell transistor including a gate electrode 25G, a drain 28D, and a source 28S is completed in the transistor region G. The capacitor dielectric film 29 and the second conductive layer 30 are formed on the entire structure including the cell transistors. The second conductive layer 30 is formed to a thickness of 700 to 1500 kPa using all materials used for the electrode of the capacitor such as polysilicon. The third photoresist pattern 31 is formed on the second conductive layer 30. The third photoresist pattern 31 defines a capacitor top plate electrode region.

Referring to FIG. 2D, the second conductive layer 30 and the dielectric film 29 are patterned by an etching process using the third photoresist pattern 31 as an etching mask, thereby forming the capacitor top plate electrode 30C. do. When the second conductive layer 30 is formed of polysilicon, the second conductive layer 30 is etched with a Cl ₂ / HBr / HeO ₂ mixed gas using the dielectric film 29 as an etch stop. As a result of the process, in the capacitor region C, a capacitor top plate electrode 30C made of the second conductive layer 30, a capacitor dielectric film 29, and a capacitor bottom plate electrode 25C made of the first conductive layer 30 are formed. The cell capacitor made is completed. After removing the third photoresist pattern 31, the interlayer insulating layer 32 is formed on the entire structure including the cell transistor and the cell capacitor. After that, a general process such as a wiring process is performed.

The method according to the embodiment of the present invention increases the effective surface area by the protruding pattern 200 while using the first conductive layer 25 in direct contact with the semiconductor substrate 21 as the capacitor bottom plate electrode 25C. According to the present invention, the space for accommodating charges can be increased, the capacitance value of the capacitor can be easily adjusted and increased, and leakage current from the lower portion of the semiconductor substrate 21 can be reduced. You can increase the refresh time. In addition, the capacitor dielectric film 29 is not limited to the material used as the gate oxide film 23G, and various materials such as materials having a high dielectric constant value, for example, an oxide-nitride-oxide (ONO) structure, can be used. More and more capacitors can be obtained.

As described above, the present invention can easily adjust and increase the capacitance value of a capacitor by increasing the effective surface area of a capacitor bottom plate electrode in a composite semiconductor memory device in which logic and memory devices are mixed, and reduce leakage current. By increasing the refresh time, the performance of the capacitor can be improved, and the high integration of the device can be realized, which can be applied to SOC products requiring 1M to 16M DRAM.

Claims (8)

Providing a semiconductor substrate defining a transistor region and a capacitor region; Forming an isolation layer on the semiconductor substrate to define an active region and an inactive region; Forming at least one protrusion pattern on the semiconductor substrate in the capacitor region; Forming a gate oxide film on the semiconductor substrate in the transistor region; Forming and patterning a conductive layer on the resultant product on which the gate oxide film is formed, forming a gate electrode on the gate oxide film of the transistor region, and forming a capacitor bottom plate electrode on the semiconductor substrate of the capacitor region where the protruding pattern is formed. Forming; Forming a source and a drain, thereby forming a transistor in the transistor region; And And forming a capacitor dielectric layer and a capacitor top plate electrode on the capacitor bottom plate electrode, thereby forming a capacitor in the capacitor region. The method of claim 1, The protruding pattern is formed by forming an oxide film with a thickness of 100 to 300 kPa, forming a nitride film with a thickness of 1000 to 3000 kPa, and patterning the nitride film using a CF ₄ / CHF ₃ / O ₂ / Ar mixed gas, A method for manufacturing a capacitor of a semiconductor device, wherein the oxide film is etched by a wet etching method using an HF solution or a BOE solution. The method of claim 1, The gate oxide film is formed by forming an oxide film on the semiconductor substrate of the transistor region and the capacitor region in which the protruding pattern is formed, and then removing the oxide film of the capacitor region by a wet etching method. The method of claim 2, The wet etching method of manufacturing a capacitor of a semiconductor device using HF solution or BOE solution. delete The method of claim 1, The drain is a capacitor manufacturing method of a semiconductor device to form an LDD structure using an LDD spacer. The method of claim 1, And the capacitor bottom plate electrode is in contact with the semiconductor substrate. The method of claim 1, And the dielectric film is formed of an ONO structure material.

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