KR20010011638A - Structure of semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to remarkably reduce parasitic capacitance between a bit line and a gate, by forming an air gap between a space of a gate electrode and a plug poly. CONSTITUTION: A gate insulating layer is formed in an active region of a semiconductor substrate(10) and a conductive material and a hard mask nitride layer(18) are stacked and patterned to form a gate electrode. The first/the second insulating layers are stacked and etched to form the first and second spacer on a sidewall of the gate electrode. Impurity ions are implanted to form a source/drain region(28) by using the spacers and the gate electrode as a mask. A plug poly(30) connected to the source/drain region between the gate electrodes is formed. After the resultant structure is polished until the second spacer is exposed, the second spacer only is selectively eliminated to form an air gap(31) between a space of the gate electrode and the plug poly.

Description

Structure of semiconductor device and its manufacturing method {Structure of semiconductor device and method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor device that reduces parasitic capacitance between a gate electrode and a bit line so as to increase the operation speed of a device of a highly integrated semiconductor device, and a method of manufacturing the same.

Higher integration of semiconductor devices requires research on lithography, cell structure, new materials related to wiring, and physical property limits related to insulating films. In addition, as the cell area is also reduced due to the high integration of semiconductor devices, the reduction of the contact hole area is also essential.

In 64M DRAM devices with a design rule of about 0.3 ?? m to 0.4 ?? m, even if the contact hole is formed to a feature size of about 0.5 ?? m, it is caused by misalignment of the mask or the like. The structure, that is, the exposure of the gate electrode or the bit line is frequently generated, which causes a contact between the gate electrode and the storage electrode and the bit line and the storage electrode, which is a significant factor in the reliability of the memory device.

Accordingly, many methods for reliably achieving miniaturization of contact holes without exposure of peripheral structures due to misalignment of masks, etc. have been researched and developed, and one of them is a method of forming a self-aligned contact. to be. That is, the self-aligned contact method is suitable for realizing a semiconductor device which is miniaturized by high integration because a contact of various sizes can be obtained by the height of the surrounding structure, the thickness of the insulating material on which the contact is to be formed, and the etching method.

Recently, a self-aligned contact method has been applied to form contact between bit lines and capacitors. This uses a hard mask layer on the top surface of the gate electrode and a spacer on the sidewall thereof. In particular, the doped polysilicon is embedded in a contact hole in which the active region of the substrate is exposed while self-aligning by the spacer insulating layer of the gate electrode. The plug poly is formed. Then, the aspect ratio of the fine contact hole can be reduced by performing the vertical hole process of the bit line and the storage electrode by performing the contact hole process connected to the plug poly to the interlayer insulating layer without performing the contact hole manufacturing process between the narrow gate electrodes. have.

However, when the source / drain area is continuously reduced due to the high integration of the semiconductor device, it is difficult to secure the area of the plug poly, thereby reducing the thickness of the spacer film. Then, the thickness of the nitride film or the oxide film, which is mainly used as the spacer film, becomes thin and the gap between the gate electrode and the plug poly is close, so that the spacer serves as a dielectric and the parasitic capacitance increases.

As a result, the capacitance between the bit line and the gate increases, resulting in a slower cell operation and a large increase in the capacity of the cell capacitor by the parasitic capacitance.

An object of the present invention is to provide a structure of a semiconductor device that can greatly reduce the parasitic capacitance between the bit line and the gate by placing an air gap between the spacer of the gate electrode and the plug poly in order to solve the above problems of the prior art. have.

Another object of the present invention is to form a spacer of two layers on the sidewalls of the gate electrode and to form a plug poly between the gate electrode spacers to selectively remove only the outer spacers in the air gap with a lower dielectric constant than other insulating films. The present invention provides a method of manufacturing a semiconductor device which reduces capacitance of bit lines and gates.

1 to 7 are process flowcharts illustrating a method of manufacturing a semiconductor device with reduced parasitic capacitance between the gate and the bit line according to the present invention.

* Description of the symbols for the main parts of the drawings *

10 silicon substrate 12 gate oxide film

14: doped polysilicon film 16: tungsten silicide film

18: hard mask nitride film 20: LDD oxide film

22: LDD region 24: first insulating film

26: second insulating film 24 ': first spacer

26 ': second spacer 28: source / drain regions

30: plug pulley 31: air gap

32: interlayer insulating film

In order to achieve the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate having a conductive plug poly for vertically connecting a region of a substrate exposed between an insulating film surrounding a gate electrode of a semiconductor device and an upper wiring and a lower electrode of a capacitor; A gate insulating film formed in the active region of the gate insulating film, a conductor formed on the upper surface of the gate insulating film, a gate electrode having a hard mask nitride film formed thereon, and an insulating spacer formed on the sidewall, and a conductive impurity formed in the substrate exposed under the gate electrode edge. And a gap filled with air between the plug source and the drain region, the plug poly connected to the source / drain region between the gate electrode, and the spacer of the plug poly and the gate electrode.

In order to achieve the above another object, the present invention is to form a semiconductor device having an air gap between the plug poly and the spacer of the side wall of the gate electrode, forming a gate insulating film in the active region of the semiconductor substrate, the conductor and the hard mask thereon Stacking and patterning a nitride film to form a gate electrode, stacking and etching first and second insulating films on the substrate, and forming first and second spacers on sidewalls of the gate electrode, Forming a source / drain region by performing an impurity ion implantation process in the substrate using the gate electrode as a mask; forming a plug poly connected to the source / drain region between the gate electrodes; After polishing until exposed, selectively remove only the second spacer to remove the gate electrode And forming an air gap between the stand and the plug polyester.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are process flowcharts illustrating a method of manufacturing a semiconductor device having reduced parasitic capacitance between a gate and a bit line according to the present invention. Here, the present embodiment takes an NMOS transistor as an example.

First, referring to FIG. 1, in the manufacturing process of the present invention, a gate insulating film 12 is formed in an active region of a silicon substrate 10 as a semiconductor substrate, on which doped polysilicon 14 and tungsten silicide are formed. After stacking the 16 and the hard mask nitride film 18, a photomask and an etching process using a gate mask are performed to pattern the films 18, 16, and 14 to form gate electrodes. After the oxide thin film 20 is formed on the entire surface of the substrate to serve as a screen of the substrate during LDD ion implantation, an n-impurity ion implantation process is performed to form the LDD region 22 near the substrate exposed between the gate electrode edges. .

2 and 3, a nitride film is deposited as the first insulating film 24 on the entire surface of the substrate, and an oxide film is laminated as the second insulating film 26 thereon.

Next, as illustrated in FIG. 3, the first and second insulating layers 24 and 26 are etched by performing an etch back process, so that the first and second spacers 24 ′, 26 '). In this case, since the second spacer 26 ′ is a space in which the air gap is to be removed in a subsequent process, the second spacer 26 ′ has a thickness of 100 μm or less so that the insulating film is not buried in the air gap during the deposition of the interlayer insulating film.

The source / drain region 28 is formed by performing an n + impurity ion implantation process in the substrate using the spacers 24 'and 26' and the gate electrode as masks.

Next, as shown in FIG. 4, a plug poly 30 is formed to be connected to the source / drain regions 28 exposed between the spacers 24 'and 26' of the gate electrode. In this case, the plug poly 30 uses a selective polysilicon process. Here, the gate oxide film 12 and the LDD oxide film 20 on the source / drain region 28 are already removed when the spacer is formed.

Next, the resultant is polished by performing a mechanical mechanical polishing (CMP) process as shown in FIG. 5. In this case, the etching height h is determined as the height until the second spacer 26 'is exposed to some extent.

Then, as shown in FIG. 6, the second spacer 26 'with the HF-based solution (NH ₄ + HF, HF + H ₂ O) using the excellent wet etching selectivity with the polysilicon and the nitride film in the resultant. ) Is optional. Then, an air gap 31 filled with air is formed between the first spacer 24 'of the gate electrode and the plug poly 30'. Here, the air gap 31 has a lower dielectric constant (about 1) than that of the nitride film and the oxide film, thereby greatly reducing the capacitance between the gate electrode and the plug poly.

Subsequently, as shown in FIG. 7, TEOS (Tetra-Etly-Ortho-Silicate) is deposited as the interlayer insulating film 32 on the resultant, in which case the air gap 31 is 100 μm or less in thickness. ) Is not filled with an insulating film.

Then, according to the above-described manufacturing process of the present invention, the semiconductor device of the present invention includes an air gap 31 filled with air between the sidewall spacer 24 'of the gate electrode and the plug poly 30 for the bit line. And the capacitance of the gate can be greatly reduced.

Therefore, as described above, the present invention provides an air gap between the spacer and the plug poly of the gate electrode to greatly reduce the parasitic capacitance between the bit line and the gate, thereby speeding up the cell operation of the highly integrated semiconductor memory device, and thereby between the bit line and the gate. The parasitic capacitances present prevent the cell capacitors from increasing in capacity.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.

Claims (5)

A semiconductor device having a conductive plug poly for vertically connecting a region of a substrate exposed between an insulating film surrounding a gate electrode of a semiconductor device, and an upper wiring and a lower electrode of a capacitor. A gate insulating film formed in the active region of the semiconductor substrate; A gate electrode having a conductor formed on an upper surface of the gate insulating layer and an insulating spacer formed on a sidewall of the hard mask nitride film; Source / drain regions in which conductive impurities are implanted into the substrate exposed under the gate electrode edges; A plug poly connected to the source / drain regions between the gate electrodes; And And a gap filled with air between the plug poly and the spacer of the gate electrode. The structure of a semiconductor device according to claim 1, wherein the thickness of said air gap is 100 kPa or less. In forming a semiconductor device having an air gap between a plug poly and a spacer of a sidewall of a gate electrode, Forming a gate insulating film in an active region of the semiconductor substrate, stacking and patterning a conductor and a hard mask nitride film thereon to form a gate electrode; Stacking first and second insulating layers on the substrate and etching the first and second insulating layers to form first and second spacers on sidewalls of the gate electrodes; Forming a source / drain region by performing an impurity ion implantation process in the substrate using the spacers and the gate electrode as masks; Forming a plug poly connected to the source / drain regions between the gate electrodes; And Polishing the resultant until the second spacer is exposed and selectively removing only the second spacer to form an air gap between the spacer of the gate electrode and the plug poly. . 4. A method according to claim 3, wherein the first insulating film is a nitride film and the second insulating film is formed of an oxide film. 4. The method of claim 3, wherein the removal of the second spacer uses a wet etching process.