KR100289490B1 - Method of forming semiconductor device having stepped insulating film - Google Patents

Abstract

The present invention relates to a method of forming a semiconductor device having different gate insulating thicknesses in a first region and a second region of a semiconductor substrate, and in particular, the method sequentially forms a first gate insulating layer and a first conductive layer on the entire surface of the substrate. Stacking, patterning the conductive layer on the first active region to form a gate electrode, forming a spacer on the sidewall of the gate electrode, and then forming a first active region and a first impurity implantation region to be formed. Removing the gate insulating layer of the second active region, and forming a second gate insulating layer and a second conductive layer having a predetermined thickness difference with the first gate insulating layer on upper surfaces of the first active region and the second active region except for the spacer, respectively. Laminating sequentially. Therefore, when the gate insulating layer is formed in the second active region or during the previous etching process, the first gate insulating layer is stabilized by spacers of the first active region and is formed in the first active region and the second active region requiring different voltages. The reliability of the device can be improved by stably securing the quality of the stepped gate insulating film.

Description

Method of forming semiconductor device having stepped insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a semiconductor device having different insulating layers having different thicknesses for reliability and performance of a device.

Recent semiconductor devices use semiconductor devices in which the memory cell array unit and the peripheral circuit unit are one-chip by improving multimedia functions, and maintain high integration and high speed of the peripheral circuit unit without sacrificing the performance of each device. Research and development is ongoing to ensure that.

Since the semiconductor device has different external power voltages applied to the memory cell array unit and the peripheral circuit unit, the thickness of each gate insulating layer is determined differently in the design rule. For example, the gate insulating film corresponding to the memory cell array unit is weak because the DRAM cell array unit boosts a voltage higher than the word line plus the array voltage and the threshold voltage when data is written to increase the amount of charge accumulated in the cell. It is formed to a thickness of 100Å. However, since the peripheral circuit portion according to the 0.35 탆 design rule applies a power supply voltage of 3.3 V to the gate electrode without boosting, the gate insulating film corresponding to the peripheral circuit portion is formed to a thickness of about 70 kHz for high speed and excellent driving ability.

In addition, in the case of logic circuits, insulating layers are formed to have different thicknesses during the manufacturing process to interface between chips using different power supply voltages. The thickness of the insulating film is made thick, and in other circuit parts, the thickness of the insulating film under the gate electrode is made smaller for the performance of the device.

On the other hand, a semiconductor device having a gate insulating film having a different thickness as described above requires a manufacturing process different from the conventional manufacturing process. That is, after a gate insulating film having a thickness corresponding to a high voltage and a low voltage difference is grown on the entire surface of the substrate, the first active region to which a high voltage is applied is masked and the gate insulating film of the second active region to which a low voltage is applied is etched. A gate insulating film is then formed to the required thickness of the insulating film in the region where the low voltage is applied to the entire surface of the substrate. As a result, a thick gate insulating layer is formed in the first active region, whereas a thin gate insulating layer is formed in the second active region, so that the gate insulating layers of the two regions have a step difference. Here, in order to secure a desired level of the gate insulating film, it is most important to determine the thickness of the gate insulating film formed primarily.

However, the stepped gate insulating film formed by the above process is damaged. The photoresist pattern used in the process of masking the first active region is directly contacted with the gate insulating film, so that the surface of the insulating film is removed by the etching solution when the photoresist pattern is removed. This is damaged.

In addition, when the dry etching process is used in the etching process, the surface of the substrate is eroded, and thus, the quality of the gate insulating layer to be formed on the eroded substrate is degraded. In addition, when wet etching is used, design rules need to be changed between devices having a thin gate insulating layer and devices having a thick gate insulating layer according to isotropic etching, and there is a problem that the chip size must be increased.

SUMMARY OF THE INVENTION An object of the present invention is to form a gate insulating film and a gate electrode having a predetermined thickness at a first position where a first voltage level is supplied or output to solve an interface problem between chips of logic circuits using different voltages, and the gate electrode sidewalls. After the spacer is formed in the gate electrode, an insulating film is deposited on the gate electrode and a gate insulating film having a thickness different from that of the gate insulating film in the first position is formed at a second position of the portion to which the second voltage level is supplied or output. The semiconductor device has a stepped insulating film which can stably form a gate insulating film between two positions in which the spacer suppresses the gate insulating film erosion at the first position during the etching process.

Another object of the present invention is to form a lower gate electrode of a memory cell array region and a spacer on sidewalls of the lower gate electrode in order to solve the problem of a semiconductor device having a memory cell array portion and a peripheral circuit portion. By forming an inter-gate insulating film on the electrode and forming a gate insulating film in the peripheral circuit area, the gate insulating film erosion of the memory cell array area is suppressed by the spacers when forming the gate insulating film of the peripheral circuit between the two areas where the step is generated. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a semiconductor device having a stepped insulating film capable of stably forming an insulating film and improving the reliability and characteristics of the semiconductor device.

Another object of the present invention is to form a gate insulating film having a predetermined thickness in the active region in order to solve the interface problem between transistors and capacitors using different voltages, the gate electrode and the lower electrode in the active region and the device isolation region, respectively After forming the spacers on the sidewalls of the gate electrode and the lower electrode, by depositing an insulating film on the gate electrode and the lower electrode, the erosion of the gate insulating film generated during the etching process is suppressed by the spacers so that the step The present invention provides a method for forming a semiconductor device having a stepped insulating film capable of stably forming an insulating film between two generated devices, thereby improving reliability and characteristics of the semiconductor device.

1A to 1J are process flowcharts for forming a semiconductor device having a stepped insulating film according to an embodiment of the present invention.

2A to 2D are process flowcharts for forming a semiconductor device having a stepped insulating film according to another embodiment of the present invention.

3A to 3F are process flowcharts for forming a semiconductor device having a stepped insulating film according to still another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10,50,100: silicon substrate 12,52,102: field oxide film

14 ', 54, 62b, 104': gate insulating film 16 ', 28b, 106a: gate electrode

17,29,31,109,115: photoresist pattern

22,32,58,66,110: low concentration impurity implantation zone

24, 60, 108: first spacer 28a, 68a, 114a: second spacer

34a: third spacer 34b, 68b: spacer

56: lower gate electrode 64a: upper gate electrode

62a: inter-poly insulating film 106b: lower electrode

112b: dielectric film 114b: upper electrode

In order to achieve the above object and other objects, the present invention is to form a semiconductor device having a different gate insulating film thickness in the first active region and the second active region of the semiconductor substrate, the first gate insulating film and the first gate Sequentially stacking conductive layers, forming a gate electrode by patterning the conductive layer on the first active region, forming a spacer on the sidewalls of the gate electrode, and then forming an impurity implantation region. Removing a gate insulating layer between the first active region and the second active region, and a second gate insulating layer having a predetermined thickness difference between the first gate insulating layer and the upper surface of the second active region except for the spacer, respectively; Sequentially stacking a second conductive layer.

In the method of the present invention, after forming the gate electrode by patterning the conductive layer, the method may further include depositing a polysilicon oxide film on the entire surface of the substrate on which the gate electrode is formed. In addition, after sequentially stacking the second gate insulating layer and the second conductive layer, the second conductive layer is etched to form a second spacer on the spacer and a second gate corresponding to the second active region. Forming a gate electrode patterned with a second conductive layer on the insulating film, forming an impurity implantation region into which a high concentration of impurities are implanted in a first active region near the bottom of the second spacer edge, and forming the second active region Forming a spacer on the gate electrode sidewalls of the gate electrode and simultaneously forming a third spacer on the second spacer, and forming an impurity implantation region in which impurities are implanted at a high concentration in the second active region near the lower edge of the gate electrode; It further includes.

In the method of the present invention, after sequentially stacking the second gate insulating layer and the second conductive layer, the second conductive layer is patterned to form an upper gate electrode on the second gate insulating layer over the first active region. Forming a gate electrode on the second gate insulating layer of the second active region and forming a second spacer on the spacer of the first active region, and simultaneously forming a gate electrode on the second active region Forming a spacer on the sidewall, and forming an impurity implantation region in which impurities are implanted at a high concentration in a first active region near the bottom of the second spacer edge and in a second active region near the bottom of the gate electrode edge of the second active region; It includes a step.

In order to achieve the above another object, the present invention provides a method for forming a semiconductor device having a gate insulating film and a dielectric film having different thicknesses in an active region and an isolation region of a semiconductor substrate, the method comprising: forming an insulating layer in an active region of the substrate; Forming a conductive layer over the active region and the isolation region; patterning the stacked conductive layer and the first insulating layer to form a gate electrode and a gate insulation layer in the active region, and simultaneously forming a lower electrode in the isolation region; Simultaneously forming spacers on sidewalls of the gate electrode and the lower electrode, and simultaneously forming a thinner insulating layer pattern and a dielectric layer pattern on the gate electrode and the lower electrode than the insulating layer aligned with the electrodes and formed in the active region; To form a conductive layer over the entire substrate on which the insulating film pattern and the dielectric film pattern are formed. Forming a second spacer on the sidewalls of the first spacer by etching the conductive layer and the conductive layer, and forming an upper electrode on the dielectric layer pattern of the device isolation region, and implanting impurities at a high concentration into the lower active region near the second spacer. Forming an impurity implantation region.

Therefore, in the present invention, a gate insulating film and a gate electrode are formed in a first region of a substrate to form different insulating film thicknesses in areas requiring different voltage levels, and silicon nitride films are formed on the sidewalls of the gate electrodes. After forming the spacer, the gate insulating film having a different thickness from the gate insulating film of the first region is formed on the entire surface of the substrate, so that the gate insulating film of the first region is eroded during the etching process for the gate insulating film of the second region. It prevents it.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1J are process flowcharts for forming a semiconductor device having a stepped insulating film according to an embodiment of the present invention. Referring to this, the semiconductor device of the present invention is a logic circuit formed according to the following manufacturing process sequence and having devices requiring different voltage levels.

First, a field oxide film 12 for isolation between devices is formed on a silicon substrate 10 using a conventional LOCOS (LOCal Oxidation Silicon) formation method. Next, as shown in FIG. 1A, polysilicon doped with silicon oxide film as the first gate insulating film 14 as the first gate insulating film 14 and polysilicon doped with P (Phosphorus) as the first conductive layer 16 as 1000-3000Å as shown in FIG. 1A. Laminate sequentially.

Subsequently, as illustrated in FIG. 1B, the first conductive layer 16 is patterned by a gate masking process and an etching process to form the gate electrode 16 ′ in the first active region A of the substrate 10.

Then, as illustrated in FIG. 1C, a photolithography process is performed to mask the substrate of the second active region B with the photoresist pattern 17, and to ion implant the active region and other conductivity-type impurities at low concentration to form the first active region. A low concentration impurity region 22 into which impurities are injected is formed between the edge of the gate electrode 16 'and the field oxide film 12 in (A). After the photoresist pattern 17 is removed, silicon oxide films 20a and 20b are deposited as a thin insulating film on the entire substrate 10.

Subsequently, as shown in FIG. 1D, a silicon nitride film is deposited as an insulating film on the entire surface of the substrate 10 and a blanket etching process is performed to form the first spacers 24 on the sidewalls of the gate electrodes 16 ′ of the first active region A. FIG. do.

As shown in FIG. 1E, a wet etching process is performed on the entire surface of the substrate 10 to form a first active region A and a second active region corresponding to a portion where a top surface of the gate electrode 16 ′ and a source / drain region are to be formed. The oxide films 20a and 20b on the surface (B) are removed to open the surface of the second active region B. FIG.

Next, as shown in FIG. 1F, a silicon oxide film is deposited to a thickness of 50 기판 on the entire surface of the substrate 10 as a second gate insulating film. As a result, the silicon oxide layer 26a deposited on the upper surface of the first active region A and the gate electrode 16 'of the portion where the source / drain is to be formed serves as a buffer in a subsequent process, and the second active region B The silicon oxide film 26b deposited on the upper surface serves as a gate insulating film. Subsequently, P-doped polysilicon layer 28 is deposited to a thickness of 1000 to 3000 Å on the entire surface of the resultant as a second conductive layer.

Then, the polysilicon layer 28 is etched by a photograph and an etching process, and the second spacer 28a and the second active region are formed on the sidewalls of the first spacers 24 of the first active region A, as shown in FIG. 1G. The gate electrode 28b is simultaneously formed on the silicon oxide film 26b of (B). The second spacer 28a serves to separate the low concentration impurity region 22 and the source / drain region 30 to be formed later.

Next, as shown in FIG. 1H, a photoresist pattern 29 is formed on the resultant to mask the second active region B by a photolithography process, and ion implantation is performed at a high concentration with other conductive type impurities different from the first active region A. As a result, the source / drain region 30 is formed as an impurity implantation region in which impurities are injected into the first active region A near the edge of the first spacer 24.

The photoresist pattern 29 is removed, and a next photolithography process is performed to form a photoresist pattern 31 on the resultant, which masks the first active region A. FIG. As shown in FIG. 1I, a low concentration impurity region 32 in which impurities are implanted into the second active region B near the edge of the gate electrode 28b by ion implantation at a low concentration with other conductive type impurities different from the second active region B is shown. ).

Subsequently, the photoresist pattern 31 is removed, and a silicon oxide film is deposited on the entire surface of the resultant product in which the low concentration impurity region 32 of the second active region B is formed, as shown in FIG. 1J. In the dry etching process, the deposited silicon oxide layer is etched to form a third spacer 34a on the second spacer 28a of the first active region A, and at the same time, the gate electrode 28b of the second active region B is formed. The spacer 34b is also formed on the side wall.

Next, a source / drain region as an impurity implantation region in which impurities are implanted into the second active region B near the edge of the spacer 34b by ion-implanting the second active region B and another conductive type impurity at a high concentration. Form 36).

According to the present invention according to the manufacturing process sequence as described above, when the gate electrode 16 'of the first active region A to which a relatively high voltage is applied, the gate insulating layer 14' of the region is secured to a high thickness. Since the spacers 24 of the silicon nitride film are formed on the gate electrode 16 ', the gate insulating film 14' of the first active region A is applied to the second active region (for which a relatively low voltage is applied). It is protected by the spacer 24 during an etching process for removing the native oxide film of B). Next, since the manufacturing process of the present invention forms a gate electrode after forming a thin gate insulating film in the second active region, it is possible to improve the quality of the gate insulating film in the two regions A and B where the step occurs. Can be obtained.

2A to 2D are process flowcharts for forming a semiconductor device having a stepped insulating film according to another exemplary embodiment of the present invention, which includes a memory cell array unit and peripheral circuits having different voltage levels required. It relates to a step of forming a semiconductor device.

The manufacturing method of this invention proceeds the same process sequence as FIG. 1A-1E. Then, as shown in FIG. 2A, the gate insulating layer 54, the lower gate electrode 56, the low concentration impurity implantation region 58, and the first spacer 60 having a tunnel in the first active region M in which the memory cell array unit is to be formed are formed. ) Are sequentially formed, and the surface of the second active region L on which the peripheral circuit region is to be formed is opened.

Next, as shown in FIG. 2B, a silicon oxide film is deposited on the entire surface of the substrate 50 to have a thickness thinner than that of the gate insulating film of the first active region M, so that the first active region surface corresponding to the portion where the source / drain is to be formed. The silicon oxide layers 62a, 62a ′ and 62b are deposited on the upper surface of the lower gate electrode 56 and the entire surface of the second active region L. FIG. In this case, the silicon oxide film 62a ′ deposited on the upper surface of the lower gate electrode 56 serves as an interpoly insulating film, and the silicon oxide film 62b deposited on the entire surface of the second active region L serves as a gate insulating film. do. On the other hand, the gate insulating film of the first active region M is formed to have a thickness of 90 to 120 kV, while the gate insulating film of the second active region L is formed to have a thickness of 60 to 80 kPa. Then, the second active region is masked and a low concentration impurity ion implantation process is performed in the first active region M to form a low concentration impurity implantation region 58 in the active region near the edge of the lower gate electrode 56. The conductive layer 64 is formed over the entire surface of the substrate 50.

Subsequently, as illustrated in FIG. 2C, the conductive layer 64 is patterned by a photolithography and an etching process to form an upper gate electrode 64a aligned over the lower gate electrode 56 of the first active region M. The normal gate electrode 64b is formed on the gate insulating film 62b of the active region L. As a result, the gate electrode G of the memory cell including the lower gate electrode 56, the inter-poly insulating layer 62a ′, and the upper gate electrode 64a is formed in the first active region.

Next, as shown in FIG. 2D, the first active region M is masked and a low concentration impurity ion implantation process is performed to form a low concentration impurity implantation region 66 in the second active region near the edge of the normal gate electrode 64b. . Subsequently, a silicon oxide film is deposited as an insulating film over the entire surface of the substrate 50, and the silicon oxide film is etched by an etching process to form a second spacer 68a on the first spacer 60 in the first active region M. The spacer 68b is formed on the sidewall of the gate electrode 64b.

Subsequently, a high concentration of impurity ions are implanted to implant impurities into the first active region near the edge of the second spacer 68a and the second active region near the edge of the spacer 68b of the sidewall of the normal gate electrode. Regions 70a and 70b are formed, respectively. In this case, the impurity implantation regions 70a and 70b are source / drain regions of each transistor.

Therefore, the first insulating film 60 formed on the sidewall of the lower gate electrode 56 of the memory cell not only protects the gate insulating film 54 of the cell from etching later, but also the film quality of the gate insulating film 62b of the peripheral circuit portion. Can be obtained in a stable state.

3A to 3F are process flowcharts for forming a semiconductor device having a stepped insulating film according to still another embodiment of the present invention. Referring to this, the semiconductor device of the present invention is formed according to the following manufacturing process sequence, and includes a transistor and a capacitor requiring different voltage levels.

First, a field oxide film 103 is formed on the silicon substrate 100 using a conventional LOCOS (LOCal Oxidation Silicon) manufacturing method for isolation between devices. Next, as shown in FIG. 3A, a silicon oxide film is deposited as a gate insulating film 104 in the active region C of the substrate 100 on which the transistor is to be formed. Then, polysilicon 106 doped with P (Phosphorus) as a conductive layer is deposited on the entire surface of the substrate 100 to a thickness of 1000 Å.

Subsequently, as shown in FIG. 3B, the gate electrode 106a and the gate insulating layer 014 'self-aligned to the gate electrode 106a are formed in the active region C by a photo and etching process. At this time, the lower electrode 106b is formed in the device isolation region 102 where the capacitor is to be formed later by the above process.

Next, a silicon oxide film is deposited on the entire surface of the substrate 100 on which the gate electrode 106a and the lower electrode are formed, and a dry etching process is performed to form a sidewall of the gate electrode 106a corresponding to the active region C as shown in FIG. 3C. The first spacer 108 is formed, and the spacer 108 is formed on sidewalls of the lower electrode 106b corresponding to the device isolation region 102.

Next, a photoresist pattern 109 is formed on the resultant by performing a photolithography process to mask the device isolation region 102, and ion implantation of the active region and other conductive impurities is carried out at low concentration. As a result, a low concentration impurity region 110 is formed in the active region between the lower edge of the gate electrode 106a and the device isolation region 102. Next, the photoresist pattern 109 is removed.

Subsequently, as shown in FIG. 3D, an insulating film having a thin thickness and a high dielectric constant is deposited on the entire surface of the resultant, and the insulating film deposited by photolithography and etching processes is patterned to form a buffer film 112a on the gate electrode 106a. The dielectric film 112b is formed on the electrode 106b.

Then, as shown in FIG. 3E, polysilicon doped with P as a conductive layer is deposited on the entire surface of the resultant to a thickness of 1000 to 3000 GPa.

Subsequently, as illustrated in FIG. 3F, the polysilicon is selectively etched by a photolithography and etching process to form a second spacer 114a on the sidewalls of the first spacers 108 of the active region C, and the upper electrode on the dielectric layer 112b. Form 114b. After the device isolation region 102 is masked by a photolithography process, the active region and other conductive impurities are ion-implanted at high concentration, and thus, between the active region and the device isolation region 102 near the edge of the first spacer 108. Source / drain regions 116 implanted with impurities are formed.

According to the manufacturing process sequence of the present invention as described above, since the lower electrode of the capacitor is simultaneously formed while forming the gate electrode of the transistor, and spacers are formed on the sidewalls of the gate electrode and the lower electrode, the film quality of the gate insulating film of the transistor is removed from the etching process. I can stabilize it. Furthermore, the present invention simplifies the manufacturing process of the semiconductor device because the dielectric film of the capacitor is simultaneously formed while the buffer film over the gate electrode is formed with the insulating film, and the upper electrode of the capacitor is formed together with the spacer formation of the gate electrode.

The present invention provides a semiconductor device in which a memory cell array part and a peripheral circuit part are applied differently, or a gate insulating layer of a logic circuit that receives or outputs different power supply voltages. The insulating film can be ensured to a uniform thickness.

In addition, the present invention can form the gate insulating film stably has the effect of improving the reliability and characteristics of the semiconductor device.

Claims (9)

In forming a semiconductor device having different gate insulating film thicknesses in a first active region and a second active region of a semiconductor substrate, Sequentially stacking a first gate insulating film and a first conductive layer on the entire surface of the substrate; Patterning the conductive layer on the first active region to form a gate electrode; Forming a spacer on sidewalls of the gate electrode; Thereafter removing a gate insulating layer between the first active region and the second active region where the impurity implantation region is to be formed; And And sequentially stacking a second gate insulating layer and a second conductive layer having a predetermined thickness difference with the first gate insulating layer on upper surfaces of the first active region and the second active region except for the spacer, respectively. A method of forming a semiconductor device having a stepped insulating film. The method of forming a semiconductor device having a stepped insulating film according to claim 1, wherein said spacer uses a silicon nitride film. The method of claim 1, further comprising forming a gate electrode by patterning the conductive layer. And depositing a polysilicon oxide film on the entire surface of the substrate on which the gate electrode is formed. The method of claim 1, wherein after sequentially stacking the second gate insulating layer and the second conductive layer, Etching the second conductive layer to form a second spacer on the spacer, and simultaneously forming a gate electrode on which the second conductive layer is patterned on the second gate insulating layer corresponding to the second active region; Forming an impurity implantation region in which impurities are implanted at a high concentration in a first active region near the bottom of the second spacer edge; Forming a spacer on the sidewalls of the gate electrode of the second active region and simultaneously forming a third spacer on the second spacer; And And forming an impurity implantation region in which impurities are implanted at a high concentration in the second active region near the bottom edge of the gate electrode. The method of claim 4, wherein the spacers of the third spacer and the second active region use any one selected from a silicon oxide film and a silicon nitride film. The method of claim 1, wherein after sequentially stacking the second gate insulating layer and the second conductive layer, Patterning the second conductive layer to form an upper gate electrode on the second gate insulating layer in the first active region, and simultaneously forming a gate electrode on the second gate insulating layer in the second active region; Forming a spacer on a sidewall of the gate electrode of the second active region while forming a second spacer on the spacer of the first active region; And And forming an impurity implantation region in which impurities are implanted at a high concentration in a first active region near the lower portion of the second spacer edge and in a second active region near the gate electrode edge lower portion of the second active region. A method of forming a semiconductor device having a stepped insulating film. 7. The method of claim 6, wherein the second spacer of the first active region and the spacer of the second active region use any one selected from a silicon oxide film and a silicon nitride film. In forming a semiconductor device having a gate insulating film and a dielectric film having different thicknesses in an active region and an element isolation region of a semiconductor substrate, Forming an insulating film in an active region of the substrate; Forming a conductive layer over the active region and the device isolation region; Patterning the stacked conductive layer and the first insulating layer to form a gate electrode and a gate insulating layer in the active region and simultaneously forming a lower electrode in the device isolation region; Simultaneously forming spacers on the gate electrode sidewalls and the lower electrode sidewalls; Simultaneously forming an insulating layer pattern and a dielectric layer pattern on the gate electrode and the lower electrode that are aligned with the electrodes and are thinner than the insulating layer formed in the active region; Forming a conductive layer on an entire surface of the substrate on which the insulating film pattern and the dielectric film pattern are formed; Etching the conductive layer to form a second spacer on a sidewall of the first spacer and forming an upper electrode on the dielectric film pattern of the device isolation region; And And forming an impurity implantation region in which impurities are implanted at a high concentration in an active region near the lower portion of the second spacer. The method of forming a semiconductor device with a stepped insulating film according to claim 1, wherein said first spacer uses a silicon nitride film.