KR100451463B1 - Method for fabricating semiconductor device having double gate oxide - Google Patents
Method for fabricating semiconductor device having double gate oxide Download PDFInfo
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- KR100451463B1 KR100451463B1 KR10-2000-0086635A KR20000086635A KR100451463B1 KR 100451463 B1 KR100451463 B1 KR 100451463B1 KR 20000086635 A KR20000086635 A KR 20000086635A KR 100451463 B1 KR100451463 B1 KR 100451463B1
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
본 발명은 이중 게이트산화막을 가진 반도체소자의 제조방법에 있어서, 상대적으로 얇은 게이트산화막을 가진 트랜지스터영역과 상대적으로 두꺼운 게이트산화막을 가진 트랜지스터영역을 포함하는 기판 전면에 N-이온주입을 행하여 트랜지스터의 게이트 양측의 기판부위에 N-영역을 형성하는 단계와; 기판 전면에 스페이서용 제1절연막을 얇게 형성하는 단계; 상기 얇은 게이트산화막을 가진 트랜지스터영역의 상기 제1절연막을 선택적으로 제거하는 단계; 상기 남아 있는 제1절연막을 건식식각하여 두꺼운 게이트산화막을 가진 트랜지스터의 게이트 측면에만 1차 LDD스페이서를 형성하는 단계; 기판 전면에 스페이서 형성용 제2절연막을 형성하는 단계; 상기 제2절연막을 건식식각하여 상기 얇은 게이트산화막을 가진 트랜지스터와 상대적으로 두꺼운 게이트산화막을 가진 트랜지스터의 게이트의 측면에 2차 LDD스페이서를 형성하는 단계; 및 기판 전면에 N+이온주입을 행하여 상기 N-영역의 양측에 N+영역을 형성함으로써 LDD구조를 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention provides a method of manufacturing a semiconductor device having a double gate oxide film, wherein the gate of a transistor is formed by performing N-ion implantation on the entire surface of a substrate including a transistor region having a relatively thin gate oxide film and a transistor region having a relatively thick gate oxide film. Forming N-regions on both sides of the substrate; Forming a thin first insulating film for a spacer on the entire surface of the substrate; Selectively removing the first insulating film in the transistor region having the thin gate oxide film; Dry etching the remaining first insulating layer to form a primary LDD spacer only at a gate side of a transistor having a thick gate oxide layer; Forming a second insulating film for forming a spacer on the entire surface of the substrate; Dry etching the second insulating layer to form a secondary LDD spacer on a side of a gate of the transistor having the thin gate oxide film and the transistor having a relatively thick gate oxide film; And forming an LDD structure by performing N + ion implantation on the entire surface of the substrate to form N + regions on both sides of the N− region.
Description
본 발명은 이중 게이트산화막을 가진 반도체소자의 제조방법에 관한 것으로, 특히 얇은 게이트산화막을 가진 트랜지스터와 두꺼운 게이트산화막을 가진 트랜지스터를 구비한 반도체소자의 제조시 마스크의 추가없이 얇은 게이트산화막을 가진 트랜지스터와 두꺼운 게이트산화막을 가진 트랜지스터의 LDD구조 형성을 위한 LDD스페이서를 각각 다르게 형성함으로써 얇은 게이트산화막을 가진 트랜지스터의 특성은 그대로 유지하면서 두꺼운 게이트산화막을 가진 트랜지스터의 핫캐리어특성은 개선시킬 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device having a double gate oxide film, and more particularly, to a transistor having a thin gate oxide film without the addition of a mask in the manufacture of a semiconductor device having a transistor having a thin gate oxide film and a transistor having a thick gate oxide film; By fabricating different LDD spacers for LDD structure formation of transistors with thick gate oxide films, the semiconductor device can improve the hot carrier characteristics of transistors with thick gate oxide films while maintaining the characteristics of transistors with thin gate oxide films. It is about a method.
트랜지스터에 있어서, 핫캐리어(hot carrier)는 채널영역에 인가되는 전계로 인하여 발생하기 때문에 LDD(Lightly Doped Drain)와 같은 경사진 드레인 구조를 구현하여 채널내의 피크 전계영역을 감소시키거나 드레인쪽으로 이동시켜 핫캐리어의 발생을 줄이고 있다. 종래 기술 가운데 N- 이온주입을 사용하여 피크 전계영역을 드레인 쪽으로 쉬프트시키는 방법을 설명하면 다음과 같다.In a transistor, since a hot carrier is generated by an electric field applied to a channel region, an inclined drain structure such as a lightly doped drain (LDD) is implemented to reduce or move the peak field region in a channel to a drain side. It is reducing the occurrence of hot carriers. A method of shifting the peak electric field region toward the drain using N-ion implantation in the prior art is as follows.
먼저, 도1에 나타낸 바와 같이 LDD형성전에 얇은 게이트산화막(A)(예컨대, 68Å)과 두꺼운 게이트산화막(B)(예컨대, 125Å)별로 N-이온의 주입량을 다르게 하여 N-이온주입을 게이트(1) 양측의 기판부위에 N-영역(2)을 형성한다.First, as shown in FIG. 1, before the LDD formation, the N-ion implantation is performed by varying the amount of N-ion implantation for each of the thin gate oxide film A (e.g., 68 mu s) and the thick gate oxide film B (e.g., 125 mu s). 1) N-regions 2 are formed on the substrates on both sides.
이어서 도2에 나타낸 바와 같이 기판 전면에 절연막(3)으로서 HLD를 증착한 후, 건식식각하여 도3에 나타낸 바와 같이 게이트 양측면에 스페이서(4)를 형성한다. 다음에 N+이온주입을 행하여 기판에 N+영역(5)을 형성함으로써 LDD구조를 완성한다.Subsequently, as shown in FIG. 2, HLD is deposited as an insulating film 3 on the entire surface of the substrate, followed by dry etching to form spacers 4 on both sides of the gate as shown in FIG. Next, N + ion implantation is performed to form the N + region 5 on the substrate to complete the LDD structure.
이러한 종래 기술은 두꺼운 게이트산화막을 가진 트랜지스터의 핫캐리어 특성을 낮추기 위하여 이 트랜지스터 영역의 N-이온주입량을 얇은 게이트산화막을 가진 트랜지스터 영역의 N-이온주입량보다 높여 줌으로써 채널의 피크 채널전계를 드레인영역으로 밀어내는 효과를 가져오도록 유도한다. 이렇게 되면 게이트산화막내로 캐리어주입이 줄어 들어 브레이크다운 전압은 증가하고 기판전류는 줄어드는 개선 효과를 가져올 수 있다.In order to reduce the hot carrier characteristics of a transistor having a thick gate oxide film, the related art increases the N-ion implantation amount of the transistor region to a drain region by increasing the N-ion implantation amount of the transistor region with a thin gate oxide film. Induces a repelling effect. As a result, carrier injection into the gate oxide film may be reduced, resulting in an improvement effect of increasing breakdown voltage and decreasing substrate current.
그러나 상기 종래 기술은 얇은 게이트산화막을 가진 트랜지스터영역과 두꺼운 게이트산화막을 가진 트랜지스터영역의 N-영역을 별도로 형성하기 위하여 N-영역 이온주입 마스크를 얇은 게이트산화막용과 두꺼운 게이트산화막용으로 제작해야 하는 부담이 있다. 또한, 게이트산화막이 두꺼운 트랜지스터 영역에 N-이온주입량을 높여 줌으로써 핫캐리어효과를 개선할 수는 있으나, 두터운 채널영역에 전류가 증가하여 숏채널 마진을 충분히 검토해야 하는 문제가 있다.However, the prior art has a burden to produce an N-region ion implantation mask for a thin gate oxide film and a thick gate oxide film in order to form N-regions of a transistor region having a thin gate oxide film and a transistor region having a thick gate oxide film separately. have. In addition, the hot carrier effect can be improved by increasing the amount of N-ion implanted in the transistor region with a thick gate oxide, but there is a problem in that the short channel margin should be sufficiently examined due to the increase in current in the thick channel region.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 두꺼운 게이트산화막을 가진 트랜지스터와 얇은 게이트산화막을 가진 트랜지스터의 LDD구조 형성시 각각의 LDD 스페이서를 따로 구현함으로써 두꺼운 게이트산화막을 가진 트랜지스터의 핫캐리어특성을 좀더 안전하게 개선시킬 수 있도록 하는 이중 게이트산화막을 가진 트랜지스터 제조방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by implementing each LDD spacer separately when forming a LDD structure of a transistor having a thick gate oxide film and a transistor having a thin gate oxide film, the hot carrier characteristic of the transistor having a thick gate oxide film is further improved. It is an object of the present invention to provide a transistor manufacturing method having a double gate oxide film which can be safely improved.
도1 내지 도3은 종래 기술에 의한 이중 게이트산화막을 가진 반도체소자의 LDD구조 제조방법을 나타낸 공정순서도.1 to 3 are process flowcharts showing a method for manufacturing an LDD structure of a semiconductor device having a double gate oxide film according to the prior art.
도4 내지 도8는 본 발명에 의한 이중 게이트산화막을 가진 반도체소자의 LDD구조 제조방법을 나타낸 공정순서도.4 to 8 are process flowcharts showing a method for manufacturing an LDD structure of a semiconductor device having a double gate oxide film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 게이트 2 : N-영역1: gate 2: N-region
3 : 스페이서 형성용 절연막 4 : LDD형성용 스페이서3: insulating film for spacer formation 4: spacer for LDD formation
5 : N+영역 13 : 스페이서 형성용 제1절연막5: N + region 13: first insulating film for spacer formation
14 : 포토레지스트 15 : 1차 LDD스페이서14 photoresist 15 primary LDD spacer
16 : 스페이서 형성용 제2절연막 17 : 2차 LDD스페이서16 second insulating film for spacer formation 17 secondary LDD spacer
상기 목적을 달성하기 위한 본 발명은, 이중 게이트산화막을 가진 반도체소자의 제조방법에 있어서, 상대적으로 얇은 게이트산화막을 가진 트랜지스터영역과 상대적으로 두꺼운 게이트산화막을 가진 트랜지스터영역을 포함하는 기판 전면에 N-이온주입을 행하여 트랜지스터의 게이트 양측의 기판부위에 N-영역을 형성하는 단계와; 기판 전면에 스페이서용 제1절연막을 얇게 형성하는 단계; 상기 얇은 게이트산화막을 가진 트랜지스터영역의 상기 제1절연막을 선택적으로 제거하는 단계; 상기 남아 있는 제1절연막을 건식식각하여 두꺼운 게이트산화막을 가진 트랜지스터의 게이트 측면에만 1차 LDD스페이서를 형성하는 단계; 기판 전면에 스페이서 형성용 제2절연막을 형성하는 단계; 상기 제2절연막을 건식식각하여 상기 얇은 게이트산화막을 가진 트랜지스터와 상대적으로 두꺼운 게이트산화막을 가진 트랜지스터의 게이트의 측면에 2차 LDD스페이서를 형성하는 단계; 및 기판 전면에 N+이온주입을 행하여 상기 N-영역의 양측에 N+영역을 형성함으로써 LDD구조를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device having a double gate oxide film, comprising: a transistor region having a relatively thin gate oxide film and a transistor region having a relatively thick gate oxide film on the entire surface of the substrate; Performing ion implantation to form N-regions on substrate portions on both sides of the gate of the transistor; Forming a thin first insulating film for a spacer on the entire surface of the substrate; Selectively removing the first insulating film in the transistor region having the thin gate oxide film; Dry etching the remaining first insulating layer to form a primary LDD spacer only at a gate side of a transistor having a thick gate oxide layer; Forming a second insulating film for forming a spacer on the entire surface of the substrate; Dry etching the second insulating layer to form a secondary LDD spacer on a side of a gate of the transistor having the thin gate oxide film and the transistor having a relatively thick gate oxide film; And forming an LDD structure by performing N + ion implantation on the entire surface of the substrate to form N + regions on both sides of the N− region.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도4 내지 도8을 참조하여 본 발명에 의한 이중 게이트산화막을 가진 반도체소자의 제조방법을 공정순서에 따라 설명하면 다음과 같다.Referring to FIGS. 4 to 8, a method of manufacturing a semiconductor device having a double gate oxide film according to the present invention will be described according to a process sequence.
먼저, 도5에 나타낸 바와 같이 얇은 게이트산화막(A)(예컨대, 68Å)을 가진 트랜지스터영역과 두꺼운 게이트산화막(B)(예컨대, 125Å)을 가진 트랜지스터영역에 N-이온주입을 행하여 게이트(1) 양측의 기판부위에 N-영역(2)을 형성한다.First, as shown in FIG. 5, N-ion implantation is performed in a transistor region having a thin gate oxide film A (e.g., 68 mu s) and a transistor region having a thick gate oxide film B (e. N-regions 2 are formed in the substrate portions on both sides.
이어서 도6에 나타낸 바와 같이 기판 전면에 스페이서용 제1절연막으로서 예컨대, HLD(13)를 얇게 증착한 후, 상기 서로 다른 두께의 게이트산화막 형성시 사용하였던 마스크를 다시 사용하여 두꺼운 게이트산화막을 가진 트랜지스터영역을 포토레지스트(14)로 마스킹한 후, 얇은 게이트산화막을 가진 트랜지스터영역의 상기 HLD막(3)을 어느 정도 제거한다.Subsequently, as shown in FIG. 6, a thin film of HLD 13 is deposited as a first insulating film for spacers on the entire surface of the substrate, and then a mask having a thick gate oxide film is used again by using a mask used when the gate oxide films having different thicknesses are formed. After masking the region with the photoresist 14, the HLD film 3 of the transistor region with a thin gate oxide film is removed to some extent.
이어서 도7에 나타낸 바와 같이 상기 두꺼운 게이트산화막을 가진 트랜지스터영역을 덮고 있는 포토레지스트(14)를 제거한 다음, 상기 남아 있는 HLD막(13)을 건식식각하여 두꺼운 게이트산화막을 가진 트랜지스터의 게이트 측면에 1차 LDD스페이서(15)를 형성한다. 이때, 얇은 게이트산화막을 가진 트랜지스터의 게이트 측면에는 상기에서 HLD를 어느 정도 제거했기 때문에 스페이서가 형성되지 않고 상기 두꺼운 게이트산화막을 가진 트랜지스터의 게이트 측면에만 1차 LDD스페이서가 형성된다.Subsequently, as shown in FIG. 7, the photoresist 14 covering the transistor region having the thick gate oxide film is removed, and then the remaining HLD film 13 is dry etched to remove the photoresist 14 from the gate side of the transistor having the thick gate oxide film. The difference LDD spacer 15 is formed. At this time, since the HLD is removed to some extent on the gate side of the transistor having the thin gate oxide layer, no spacer is formed, and the primary LDD spacer is formed only on the gate side of the transistor having the thick gate oxide layer.
다음에 도8에 나타낸 바와 같이 상술한 종래 공정과 마찬가지로 기판 전면에 다시 스페이서 형성용 제2절연막(16)으로서 예컨대, HLD를 증착한 후, 건식식각하여 도9에 나타낸 바와 같이 게이트 양측면에 2차 LDD스페이서(17)를 형성한 다음 N+이온주입을 행하여 상기 N-영역(2)의 양측에 N+영역(5)을 형성함으로써 LDD구조를 완성한다. 이때, 두꺼운 게이트산화막을 가진 트랜지스터의 게이트 측면에는 1차 LDD스페이서(15)와 2차 LDD스페이서(17)가 모두 형성되므로 얇은 게이트산화막을 가진 트랜지스터의 게이트 측면의 스페이서보다 두꺼운 스페이서를 얻을 수 있다. 이와 같이 두꺼운 게이트산화막을 가진 트랜지스터의 LDD형성용 스페이서가 두껍게 형성되므로 이 부분의 채널의 피크 전계영역이 드레인쪽으로 밀려나는 효과를 얻을 수 있다.Next, as shown in FIG. 8, the HLD is deposited as a second insulating film 16 for spacer formation on the entire surface of the substrate as in the above-described conventional process, followed by dry etching and secondary etching on both sides of the gate as shown in FIG. After forming the LDD spacer 17, N + ion implantation is performed to form the N + region 5 on both sides of the N-region 2, thereby completing the LDD structure. In this case, since both the primary LDD spacer 15 and the secondary LDD spacer 17 are formed on the gate side of the transistor having the thick gate oxide film, a spacer thicker than the spacer of the gate side of the transistor having the thin gate oxide film may be obtained. As described above, since the LDD-forming spacer of the transistor having a thick gate oxide film is formed thick, the peak field region of the channel of this portion is pushed toward the drain.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 얇은 게이트산화막을 가진 트랜지스터와 두꺼운 게이트산화막을 가진 트랜지스터를 구비한 반도체소자의 제조시 마스크의 추가없이 얇은 게이트산화막을 가진 트랜지스터보다 두꺼운 게이트산화막을 가진 트랜지스터의 LDD구조 형성을 위한 LDD스페이서를 더 두껍게 형성함으로써 얇은 게이트산화막을 가진 트랜지스터의 특성은 그대로 유지하면서 두꺼운 게이트산화막을 가진 트랜지스터의 핫캐리어특성을 개선시킬 수 있다.The present invention provides an LDD spacer for forming an LDD structure of a transistor having a thicker gate oxide film than a transistor having a thin gate oxide film without the addition of a mask in the manufacture of a semiconductor device having a transistor having a thin gate oxide film and a transistor having a thick gate oxide film. By forming it thicker, the hot carrier characteristics of the transistor having a thick gate oxide film can be improved while maintaining the characteristics of the transistor having a thin gate oxide film.
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| JPH05315604A (en) * | 1992-05-13 | 1993-11-26 | Matsushita Electron Corp | Manufacture of semiconductor device |
| KR19990057380A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Manufacturing method of MOS field effect transistor |
| KR20000007209A (en) * | 1998-07-01 | 2000-02-07 | 김영환 | Fabricating method of semiconductor device having stepped insulating layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05315604A (en) * | 1992-05-13 | 1993-11-26 | Matsushita Electron Corp | Manufacture of semiconductor device |
| KR19990057380A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Manufacturing method of MOS field effect transistor |
| KR20000007209A (en) * | 1998-07-01 | 2000-02-07 | 김영환 | Fabricating method of semiconductor device having stepped insulating layer |
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