KR100357173B1 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistor Download PDFInfo
- Publication number
- KR100357173B1 KR100357173B1 KR1019960031673A KR19960031673A KR100357173B1 KR 100357173 B1 KR100357173 B1 KR 100357173B1 KR 1019960031673 A KR1019960031673 A KR 1019960031673A KR 19960031673 A KR19960031673 A KR 19960031673A KR 100357173 B1 KR100357173 B1 KR 100357173B1
- Authority
- KR
- South Korea
- Prior art keywords
- active region
- insulating layer
- thin film
- gate electrode
- film transistor
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Abstract
Description
본 발명은 박막 트랜지스터에 관한 것으로, 특히 소자가 집적화 됨에따라 소자간 격리나 펀치 스루우(punch-through)를 방지하는데 적합하도록한 박막 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly, to a method for manufacturing thin film transistors suitable for preventing isolation between devices and punch-through as devices are integrated.
이하 첨부 도면을 참조로 종래의 박막 트랜지스터의 제조 방법에 대해 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional thin film transistor will be described with reference to the accompanying drawings.
도 1은 종래 박막 트랜지스터의 제조 과정을 나타낸 공정 단면도이다.1 is a cross-sectional view illustrating a manufacturing process of a conventional thin film transistor.
먼저 도 1a에 도시한 바와 같이 제 1 도전형 기판(1) 내에 제 2 도전형 물질을 이온 주입하고 어닐링하여 제 2 도전형 우물(2)을 형성한다.First, as shown in FIG. 1A, a second conductivity type material is ion-implanted and annealed in the first conductivity type substrate 1 to form a second conductivity type well 2.
그리고 도 1b에 도시한 바와 같이 제 2 도전형 우물(2) 상에 필드 산화막(6)을 형성하기 위한 마스크로 사용할 수 있는 물질을 증착한다. 예를 들면 버퍼 폴리(3)와 나이트 라이드층(4)을 적층하여 형성하고 활성 영역이 형성될 영역만 남기고 선택적으로 제거한다. 이후에 드러난 제 1 도전형 기판(1)과 제 2 도전형 우물(2)내에 N-field물질(5)이나 P-field 물질을 이온 주입하여 필드 산화막(6) 아래로 인접한 소자간에 누설 전류가 생기는 것을 감소시킨다.As shown in FIG. 1B, a material that can be used as a mask for forming the field oxide film 6 is deposited on the second conductivity type well 2. For example, the buffer poly 3 and the nitride layer 4 are stacked and selectively removed, leaving only the region where the active region is to be formed. N-field material (5) or P-field material is ion-implanted into the first conductive substrate 1 and the second conductive well 2, which are later revealed, so that a leakage current is generated between adjacent elements under the field oxide film 6. Reduces the occurrence.
다음으로 도 1c에 도시한 바와 같이 드러난 제 1 도전형 기판(1)과 제 2 도전형 우물(2)을 열공정하여 필드 산화막(6)을 형성한다.Next, as shown in FIG. 1C, the first conductive substrate 1 and the second conductive well 2 are thermally processed to form a field oxide film 6.
이어서 도 1d에 도시한 바와 같이 필드 산화막(6) 형성을 위한 마스크로 사용된 버퍼 폴리(3)나 나이트 라이드층(4)을 제거한후에 활성 영역에 문턱 전압 제어용 이온을 주입하여 활성 영역 표면내에 문턱 전압 제어 영역(14)을 형성한다. 그리고 전면에 게이트 산화막(8a)을 형성하기 위한 산화막(8)과 게이트 전극(9a)을 형성하기 위하여 폴리 실리콘층(9)을 증착한다.Subsequently, as shown in FIG. 1D, after removing the buffer poly 3 or the nitride layer 4 used as a mask for forming the field oxide film 6, the threshold voltage control ions are implanted into the active region to form a threshold within the surface of the active region. The voltage control region 14 is formed. The polysilicon layer 9 is deposited to form the oxide film 8 and the gate electrode 9a for forming the gate oxide film 8a on the entire surface.
이어서 도 1e에 도시한 바와 같이 전면에 감광막을 도포하고 노광 및 현상 공정을 통해 선택적으로 제거하여 제거되고 남은 감광막을 마스크로 이용하여 폴리실리콘 층(9)과 산화막(8)을 제거하여 게이트 전극(9a)과 게이트 산화막(9a)을 형성한다. 이후에 도 1f에 도시된 바와 같이 게이트 전극(9a)을 마스크로 이용하여 게이트 전극(8a) 양측의 제 2 도전형 우물(2)내에 저농도의 제 1 도전형 불순물을 주입하여 저 농도 소오스/드레인 영역(10)을 형성한다. 그리고 전면에 절연막을 증착하여 이방성 식각에 의해서 게이트 전극(9a) 양 측면에 측벽 절연막(11)을 형성한다. 다음에 게이트 전극(9a)과 측벽 절연막(11)을 마스크로 이용하여 고농도 제 1 불순물 이온을 이온 주입하여 고농도 소오스/드레인 영역(12)을 형성한다.Subsequently, as shown in FIG. 1E, a photoresist film is applied to the entire surface and selectively removed through an exposure and development process, and the polysilicon layer 9 and the oxide film 8 are removed using the remaining photoresist film as a mask to remove the gate electrode ( 9a and a gate oxide film 9a are formed. Subsequently, as shown in FIG. 1F, a low concentration source / drain is injected by injecting a low concentration of first conductivity type impurities into the second conductivity type wells 2 on both sides of the gate electrode 8a using the gate electrode 9a as a mask. The region 10 is formed. An insulating film is deposited on the entire surface to form sidewall insulating films 11 on both sides of the gate electrode 9a by anisotropic etching. Next, a high concentration source / drain region 12 is formed by ion implanting high concentration of first impurity ions using the gate electrode 9a and the sidewall insulating film 11 as a mask.
종래 박막 트랜지스터는 다음과 같은 문제점이 있다.Conventional thin film transistors have the following problems.
첫째, 소오스/드레인 영역을 LDD 구조로 형성하므로 트랜지스터의 동작 전류가 감소된다.First, since the source / drain regions are formed in the LDD structure, the operating current of the transistor is reduced.
둘째, 박막 트랜지스터의 격리를 위한 필드 산화막 형성 두께에 한계가 있다. 이에 따라 필드 산화막을 형성하기 전에 필드 산화막 아래에 N-field나 P-field 이온을 깊게 형성하는 필드 스톱층 형성 공정이 추가된다.Second, there is a limit in the thickness of field oxide film formation for isolation of the thin film transistor. Thereby, a field stop layer forming step of forming N-field or P-field ions deeply under the field oxide film is added before the field oxide film is formed.
세째, 소오스와 드레인의 공핍층이 채널에서 맞닿는 펀치-스루우(punch-through)가 발생하여 원하지 않는 영역에서 누설전류가 생길 가능성이 높다.Third, there is a high possibility that punch-through occurs in which the depletion layers of the source and the drain abut on the channel, causing leakage current in an unwanted region.
네째, 소자간 격리를 위한 필드 산화막의 형성에 의해 공정시 토포로지(topology) 발생의 한 원인이 되며 또한 소자의 평탄화에 문제가 된다.Fourth, the formation of a field oxide film for isolation between devices is a cause of topologies in the process and also a problem in planarization of devices.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로써 집적화된 소자간의 격리가 쉽고 펀치 스루우 방지에 적합한 박막 트랜지스터를 제조하는데그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to manufacture a thin film transistor which is easy to isolate between integrated devices and is suitable for punch through prevention.
도 1a내지 1f는 종래 박막 트랜지스터의 제조 과정을 나타낸 공정 단면도1A to 1F are cross-sectional views illustrating a manufacturing process of a conventional thin film transistor.
도 2a 내지 2e는 본 발명 박막 트랜지스터의 제조 과정을 나타낸 공정 단면도2A to 2E are cross-sectional views illustrating a process of manufacturing the thin film transistor of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10: 기판 11: 절연층10: substrate 11: insulating layer
12: 감광막 13: 활성 영역12: photosensitive film 13: active region
14: 문턱 전압 제어 영역 15: 산화막14: threshold voltage control region 15: oxide film
15a: 게이트 산화막 16: 폴리 실리콘층15a: gate oxide film 16: polysilicon layer
16a: 게이트 전극 17: 소오스/드레인 영역16a: gate electrode 17 source / drain region
18: 측벽 절연막18: sidewall insulating film
본 발명 박막 트랜지스터의 제조 방법은 기판 준비하는 단계, 상기 기판 전면에 절연층을 형성하는 단계, 상기 절연층 상의 소정 영역 내에 활성 영역을 형성하는 단계, 상기 활성 영역상에 게이트 절연막과 게이트 전극을 형성하는 단계, 상기 게이트 전극 양측의 활성 영역 내에 불순물 영역 형성하는 단계를 포함하여 제조되는 것을 특징으로 한다.A method of manufacturing a thin film transistor according to the present invention includes preparing a substrate, forming an insulating layer on the entire surface of the substrate, forming an active region in a predetermined region on the insulating layer, and forming a gate insulating film and a gate electrode on the active region. And forming an impurity region in active regions on both sides of the gate electrode.
이하 첨부 도면을 참조하여 본 발명의 박막 트랜지스터의 제조 방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a thin film transistor of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명의 박막 트랜지스터의 제조 방법을 나타낸 공정 단면도이다.2 is a process sectional view showing the manufacturing method of the thin film transistor of the present invention.
먼저 도 2a에 도시한 바와 같이 기판(10) 상에 절연층(11)을 형성한다.First, as shown in FIG. 2A, the insulating layer 11 is formed on the substrate 10.
그리고 도 2b에 도시한 바와 같이 절연층(11) 상에 감광막(12)을 도포하고 노광 및 현상 공정으로 활성 영역으로 사용할 부분 상의 감광막을 선택적으로 제거한다. 이후에 드러난 절연층(11) 내에 실리콘을 5KeV∼200MeV의 에너지로 20∼4000Å 정도의 두께가 되도록 이온 주입하여 활성 영역(13)을 형성한다. 여기서 활성 영역(13) 형성을 위한 물질로써 실리콘 대신 반도체 물질 또는 반도체 물질의 화합물이거나 반도체 물질과 다른 물질의 중간 매개 작용을 하는 물질을 이온 주입하여 형성할 수 있다.As shown in FIG. 2B, the photosensitive film 12 is applied onto the insulating layer 11, and the photoresist film on the portion to be used as the active region is selectively removed in the exposure and development processes. Thereafter, silicon is implanted into the insulating layer 11 exposed to form an active region 13 by ion implantation so as to have a thickness of about 20 to 4000 kV with an energy of 5 KeV to 200MeV. The active region 13 may be formed by ion implantation as a material for forming the active region 13 instead of silicon, or a compound of a semiconductor material or a semiconductor material or an intermediate mediator between the semiconductor material and another material.
다음으로 도 2c에 도시한 바와 같이 이온 주입되어 형성된 활성 영역(13)을 250∼1350℃ 범위의 온도에서 어닐링한다.Next, the active region 13 formed by ion implantation as shown in FIG. 2C is annealed at a temperature in the range of 250 to 1350 ° C.
그리고 도 2d에 도시한 바와 같이 활성 영역(13)에 문턱 전압 제어용 이온을 주입하여 주고 절연층(11) 상에 게이트 산화막을 형성하기 위하여 산화막(15)을 증착하고 상기 산화막(15) 상에 게이트 전극을 형성하기 위하여 폴리 실리콘층(16)을 증착한다.As shown in FIG. 2D, an oxide film 15 is deposited to inject a threshold voltage control ion into the active region 13, and a gate oxide film is formed on the insulating layer 11. A polysilicon layer 16 is deposited to form the electrode.
다음으로 도 2e에 도시한 바와 같이 상기 폴리 실리콘층(16) 상에 감광막을 도포하여 노광 및 현상 공정을 통해 선택적으로 감광막을 제거한 후에 제거되고 남은 감광막을 마스크로 이용하여 폴리 실리콘층(16)과 산화막(15)을 제거하여 게이트 전극(16a)과 게이트 산화막(15a)을 형성한다. 이후에 게이트 전극(16a)을 마스크로 이용하여 게이트 전극(16a) 양측의 활성 영역(13)에 소오스/드레인 영역(17)을 형성한다. 그리고 전면에 절연막을 증착하고 이방성 식각하여 게이트 전극(16a) 측면에 측벽 절연막(18)을 형성한다. 여기서 측벽 절연막(18)은 소오스/드레인 영역의 형성 방법에 따라서 제조할 수도 있고 제조하지 않을 수도 있다.Next, as shown in FIG. 2E, the photoresist film is applied onto the polysilicon layer 16 to selectively remove the photoresist film through an exposure and development process, and then the remaining photoresist film is used as a mask. The oxide film 15 is removed to form the gate electrode 16a and the gate oxide film 15a. Thereafter, the source / drain regions 17 are formed in the active regions 13 on both sides of the gate electrode 16a using the gate electrode 16a as a mask. The sidewall insulating film 18 is formed on the side of the gate electrode 16a by depositing and anisotropically etching the insulating film over the entire surface. The sidewall insulating film 18 may or may not be manufactured according to the method of forming the source / drain regions.
본 발명 박막 트랜지스터의 제조 방법은 다음과 같은 효과가 있다.The manufacturing method of the thin film transistor of the present invention has the following effects.
첫째, 소자간 격리를 위한 필드 산화막을 형성하지 않아도 되고 이 필드 산화막 대신에 절연층을 형성하여 주므로 소자간 격리 거리를 현저히 줄일 수 있다.First, it is not necessary to form a field oxide film for isolation between devices, and an insulation layer is formed instead of this field oxide film, so that the isolation distance between devices can be significantly reduced.
둘째, 소자의 활성 영역을 이온 주입을 통해서 얇게 형성 할 수 있으므로 소오스/드레인의 공핍 영역이 맞닿는 펀치 스루우(punch-through)를 방지할 수 있다.Second, since the active region of the device can be formed thin through ion implantation, punch-through of the depletion region of the source / drain can be prevented.
세째, 소자간 격리를 위한 필드 산화막의 형성 공정을 하지 않으므로써 공정시 발생하는 토포로지(topology)가 거의 없어서 격리 공정의 난점이 줄어들고 또한소자의 평탄화 문제가 줄어든다.Third, by not forming a field oxide film for inter-device isolation, there is almost no topology generated during the process, which reduces the difficulty of the isolation process and reduces the problem of planarization of the device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960031673A KR100357173B1 (en) | 1996-07-31 | 1996-07-31 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960031673A KR100357173B1 (en) | 1996-07-31 | 1996-07-31 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980012135A KR980012135A (en) | 1998-04-30 |
| KR100357173B1 true KR100357173B1 (en) | 2003-01-24 |
Family
ID=37490329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960031673A KR100357173B1 (en) | 1996-07-31 | 1996-07-31 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100357173B1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950004584A (en) * | 1993-07-12 | 1995-02-18 | 이헌조 | Manufacturing method of polycrystalline silicon thin film transistor with offset structure |
| KR950007148A (en) * | 1993-08-03 | 1995-03-21 | 이헌조 | Polycrystalline Silicon Thin Film Transistor |
| KR950010121A (en) * | 1993-09-24 | 1995-04-26 | 이헌조 | Method of manufacturing polycrystalline silicon thin film transistor |
| KR950012755A (en) * | 1993-10-15 | 1995-05-16 | 이헌조 | Method of manufacturing thin film transistor |
| KR960019782A (en) * | 1994-11-30 | 1996-06-17 | 엄길용 | Manufacturing method of low leakage thin film transistor |
| KR960026967A (en) * | 1994-12-23 | 1996-07-22 | 양승택 | Polycrystalline Thin Film Transistor and Manufacturing Method Thereof |
-
1996
- 1996-07-31 KR KR1019960031673A patent/KR100357173B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950004584A (en) * | 1993-07-12 | 1995-02-18 | 이헌조 | Manufacturing method of polycrystalline silicon thin film transistor with offset structure |
| KR950007148A (en) * | 1993-08-03 | 1995-03-21 | 이헌조 | Polycrystalline Silicon Thin Film Transistor |
| KR950010121A (en) * | 1993-09-24 | 1995-04-26 | 이헌조 | Method of manufacturing polycrystalline silicon thin film transistor |
| KR950012755A (en) * | 1993-10-15 | 1995-05-16 | 이헌조 | Method of manufacturing thin film transistor |
| KR960019782A (en) * | 1994-11-30 | 1996-06-17 | 엄길용 | Manufacturing method of low leakage thin film transistor |
| KR960026967A (en) * | 1994-12-23 | 1996-07-22 | 양승택 | Polycrystalline Thin Film Transistor and Manufacturing Method Thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980012135A (en) | 1998-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20020067795A (en) | Method of fabricating Metal Oxide Semiconductor transistor with Lightly Doped Drain structure | |
| EP0465045B1 (en) | Method of field effect transistor fabrication for integrated circuits | |
| KR19980084215A (en) | Method of manufacturing transistor of semiconductor device | |
| US6008100A (en) | Metal-oxide semiconductor field effect transistor device fabrication process | |
| KR100357173B1 (en) | Method for manufacturing thin film transistor | |
| KR0167301B1 (en) | Method for fabricating mosfet | |
| JP3298483B2 (en) | Manufacturing method of high voltage MOSFET | |
| KR20030034956A (en) | method for manufacturing of semiconductor device | |
| KR100485004B1 (en) | Soi semiconductor device and method for manufacturing the same | |
| KR100311177B1 (en) | A method of fabricating semiconductor device | |
| KR100588784B1 (en) | Fabricating method of semiconductor device | |
| KR100333356B1 (en) | A method of fabricating a semiconductor device | |
| KR100271801B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100503745B1 (en) | Method for fabricating semiconductor device | |
| KR100334968B1 (en) | Method for fabricating buried channel type PMOS transistor | |
| KR100531105B1 (en) | Fabricating method of semiconductor device | |
| KR20030002774A (en) | Method for manufacturing a transistor of a semiconductor device | |
| KR100657754B1 (en) | Method for fabricating the shallow junction of semiconductor device | |
| KR100790264B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100511095B1 (en) | Method for forming source/drain structure of semiconductor | |
| KR100448591B1 (en) | Method of manufacturing a transistor in a semiconductor | |
| JPH0964361A (en) | Manufacture of semiconductor device | |
| KR20040056033A (en) | Method for manufacturing a semiconductor device | |
| KR20000004535A (en) | Method for forming isolating insulator of semiconductor devices | |
| KR20020056638A (en) | method for manufacturing of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| N231 | Notification of change of applicant | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |