KR950012755A

KR950012755A - Method of manufacturing thin film transistor

Info

Publication number: KR950012755A
Application number: KR1019930021434A
Authority: KR
Inventors: 양명수
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-10-15
Filing date: 1993-10-15
Publication date: 1995-05-16
Also published as: KR100304910B1

Abstract

본 발명은 LDD구조의 폴리실리콘 박막트랜지스터 제조방법에 관한 것으로, 온전류의 감소를 최소화하여 박막트랜지스터의 특성을 개선하기 위해 투명절연기판(1)상에 버퍼층(2)을 형성하는 공정과, 상기 버퍼층(2)상에 폴리실리콘 활성층(3)을 형성하는 공정, 상기 폴리실리콘 활성층(3) 상부에 게이트절연막(4)을 형성하는 공정, 상기 게이트절연막(4)상에 게이트전극 형성을 위한 도전층(5)을 형성하는 공정, 상기 도전층(5)상에 포토레지스트를 도포하고 이를 게이트전극패턴으로 패터닝하는 공정, 상기 포토레지스트패턴(10)을 마스크로하여 상기 도전층을 등방성식각에 의한 테이퍼에치하는 공정, n형 불순물을 고농도로 이온주입하여 상기 폴리실리콘 활성층(3) 소정영역에 n⁺영역 (6)을 형성하는 공정, 상기 포토레지스패턴(10)을 마스크로 하여 상기 도전층을 이방성식각하여 게이트전극(5)을 형성하는 공정, n형 불순물을 저농도로 이온주입하여 상기 폴리실리콘 활성층(3) 소정영역에 n^-영역(6)을 형성하는 공정을 포함하여 이루어지는 박막트랜지스터 제조방법을 제공한다.The present invention relates to a polysilicon thin film transistor manufacturing method of the LDD structure, the process of forming a buffer layer (2) on the transparent insulating substrate (1) to improve the characteristics of the thin film transistor by minimizing the reduction of on current Forming a polysilicon active layer 3 on the buffer layer 2, forming a gate insulating film 4 on the polysilicon active layer 3, and forming a gate electrode on the gate insulating film 4 Forming a layer (5), applying a photoresist on the conductive layer (5) and patterning it with a gate electrode pattern, and using the photoresist pattern (10) as a mask to form the conductive layer by isotropic etching the taper is praised by the process, n-type by ion implanting impurities at a high concentration the process of forming the polysilicon active layer (3) n ⁺ region 6 in a predetermined region, the photoresist pattern 10 as a mask FIG. A thin film transistor comprises a step of forming a region ⁽⁶⁾ a gate electrode (5), n in the process, n-type impurity predetermined area of the ion-implanted at a low concentration the polysilicon active layer 3, which forms a by anisotropically etching the layer It provides a manufacturing method.

Description

Method of manufacturing thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 LDD구조의 폴리실리콘 박막트랜지스터 제조방법을 도시한 공정 순서도.2 is a process flowchart showing a method for manufacturing a polysilicon thin film transistor of an LDD structure according to the present invention.

Claims

Forming a buffer layer (2) on the transparent insulating substrate (1), forming a polysilicon active layer (3) on the buffer layer (2), and forming a gate insulating film (4) over the polysilicon active layer (3) Forming a conductive layer (5) for forming a gate electrode on the gate insulating film (4), applying a photoresist to the conductive layer (5), and patterning the conductive layer (5) into a gate electrode pattern; Tapering etching the conductive layer by isotropic etching using the resist pattern 10 as a mask, and ion + implantation with high concentration of n-type impurities to form n ⁺ region 6 in a predetermined region of the polysilicon active layer 3 And forming a gate electrode 5 by anisotropically etching the conductive layer using the photoresist pattern 10 as a mask, and ion-implanting n-type impurities at low concentration to a predetermined region of the polysilicon active layer 3. the n ^- region 6 Thin bit register method characterized in that comprises a step of forming.

The method of claim 1. And isotropically etching the conductive layer so that the etched angle of the tapered etched portion of the conductive layer is 45 ° or less.

※ Note: The disclosure is based on the initial application.