KR970053042A - Most transistor manufacturing method - Google Patents
Most transistor manufacturing method Download PDFInfo
- Publication number
- KR970053042A KR970053042A KR1019950057127A KR19950057127A KR970053042A KR 970053042 A KR970053042 A KR 970053042A KR 1019950057127 A KR1019950057127 A KR 1019950057127A KR 19950057127 A KR19950057127 A KR 19950057127A KR 970053042 A KR970053042 A KR 970053042A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- electrode material
- ion implantation
- gate electrode
- manufacturing
- Prior art date
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
반도체 기판상에 게이트 산화막, 게이트 전극 물질을 차례로 증착하는 단계; 상기 결과물에 패터닝된 감광막을 사용하여 상기 게이트 산화막 및 게이트 전극 물질을 식각하여 게이트를 형성하는 단계; 및 이온주입시 쇄도잉(Showing)현상을 방지하기 위해 상기 감광막을 적정한 두께로 낮추어 이온 주입 공정을 실시하는 단계를 포함하는 것을 특징으로 하는 LDD(Lightly Doped Drain) 구조의 MOSFET(Metal Oxide Semiconductor Field Effect Transistor) 제조방법이다.Sequentially depositing a gate oxide film and a gate electrode material on the semiconductor substrate; Etching the gate oxide layer and the gate electrode material by using the photoresist patterned on the resultant to form a gate; And performing an ion implantation process by lowering the photosensitive film to an appropriate thickness in order to prevent the phenomenon of rushing during ion implantation (Metal Oxide Semiconductor Field Effect) of LDD (Lightly Doped Drain) structure Transistor) manufacturing method.
본 발명에 의한 LDD 구조의 MOSFET 제조 방법은 소오스/드레인 영역에 저농도의 이온주입시 발생하는 감광막 쇄도잉 현상을 억제함으로써 MOSFET의 중요 특성인 문턱전압(Vth) 및 전류(IDS) 특성을 향상시켜 미세 패턴 소자 형성을 가능하게 한다.The MOSFET manufacturing method of the LDD structure according to the present invention improves the threshold voltage (Vth) and current (I DS ) characteristics, which are important characteristics of the MOSFET, by suppressing the photoresist film flooding phenomenon generated when low concentrations of ions are injected into the source / drain regions. It is possible to form a fine pattern element.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2A도 내지 제2C도는 본 발명에 의한 LDD 구조의 MOSFET 제조방법을 순차적으로 도시한 단면도이다.2A to 2C are cross-sectional views sequentially showing a method for manufacturing a MOSFET having an LDD structure according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057127A KR970053042A (en) | 1995-12-26 | 1995-12-26 | Most transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057127A KR970053042A (en) | 1995-12-26 | 1995-12-26 | Most transistor manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970053042A true KR970053042A (en) | 1997-07-29 |
Family
ID=66618355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950057127A KR970053042A (en) | 1995-12-26 | 1995-12-26 | Most transistor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970053042A (en) |
-
1995
- 1995-12-26 KR KR1019950057127A patent/KR970053042A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |