KR960019768A - Transistor Manufacturing Method - Google Patents

Transistor Manufacturing Method Download PDF

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Publication number
KR960019768A
KR960019768A KR1019940028661A KR19940028661A KR960019768A KR 960019768 A KR960019768 A KR 960019768A KR 1019940028661 A KR1019940028661 A KR 1019940028661A KR 19940028661 A KR19940028661 A KR 19940028661A KR 960019768 A KR960019768 A KR 960019768A
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KR
South Korea
Prior art keywords
film
forming
oxide film
etching
polysilicon film
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KR1019940028661A
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Korean (ko)
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KR0170436B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940028661A priority Critical patent/KR0170436B1/en
Publication of KR960019768A publication Critical patent/KR960019768A/en
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Publication of KR0170436B1 publication Critical patent/KR0170436B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures

Abstract

본 발명은 트랜지스터 제조방법에 관한 것으로, 반도체기판(11) 상부에 소정 두께의 게이트산화막(13) 및 게이트전극용 폴리실리콘막(14)을 형성하는 제1단계; 상기 폴리실리콘막(14)의 표면에 자연적으로 형성되는 자연산화막(15) 및 폴리실리콘막(14)을 차례로 선택식각하여 게이트전극 패턴을 형성하되, 상기 폴리실리콘막(14)이 소정 정도 잔류하도록 식각하는 제2단계; 전체구조 상부에 소정 두께의 절연막을 형성한 후, 비등방성 식각하여 상기 폴리실리콘막(14') 측벽에 절연막 스페이서(18)를 형성하는 제3단계; 및 상기 절연막 스페이서(18)를 식각마스크로 이용하여 하부의 상기 폴리실리콘막(14) 및 게이트산화막(13)을 식각하여, 활성영역의 상기 실리콘기판(11)을 노출시키는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a transistor manufacturing method, comprising: a first step of forming a gate oxide film 13 and a gate silicon polysilicon film 14 having a predetermined thickness on a semiconductor substrate 11; The natural oxide film 15 and the polysilicon film 14 naturally formed on the surface of the polysilicon film 14 are sequentially etched to form a gate electrode pattern, so that the polysilicon film 14 remains to a predetermined degree. Etching a second step; A third step of forming an insulating film spacer 18 on the sidewall of the polysilicon film 14 'by anisotropic etching after forming an insulating film having a predetermined thickness over the entire structure; And etching the lower polysilicon layer 14 and the gate oxide layer 13 by using the insulating layer spacer 18 as an etching mask to expose the silicon substrate 11 in the active region. Characterized in that made.

Description

트랜지스터 제조방법Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2F도는 본 발명의 일실시예에 따른 트랜지스터 제조과정을 나타내는 공정 단면도,2A through 2F are cross-sectional views illustrating a process of manufacturing a transistor according to an embodiment of the present invention;

제3도는 본 발명의 다른 실시예에 따라 형성된 트랜지스터의 단면도.3 is a cross-sectional view of a transistor formed in accordance with another embodiment of the present invention.

Claims (7)

트랜지스터 제조방법에 있어서, 반도체기판 상부에 소정 두께의 게이트산화막 및 게이트전극용 폴리실리콘막을 형성하는 제1단계; 상기 폴리실리콘막의 표면에 자연적으로 형성되는 자연산화막 및 폴리실리콘막을 차례로 선택식각하여 게이트전극 패턴을 형성하되, 상기 폴리실리콘막이 소정정도 잔류하도록 식각하는 제2단계; 전체구조 상부에 소정 두께의 절연막을 형성한 후, 비등방성 식각하여 상기 폴리실리콘막 측벽에 절연막 스페이서틀 형성하는 제3단계; 및 상기 절연막 스페이서를 식각마스크로 이용하여 하부의 상기 폴리실리콘막 및 게이트산화막을 식각하여, 활성영역의 상기 실리콘기판을 노출시키는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.A transistor manufacturing method, comprising: a first step of forming a gate oxide film and a polysilicon film for a gate electrode on a semiconductor substrate with a predetermined thickness; A second step of forming a gate electrode pattern by selectively etching a natural oxide film and a polysilicon film naturally formed on the surface of the polysilicon film, and etching the polysilicon film so that the polysilicon film remains to a predetermined degree; A third step of forming an insulating film spacer on the sidewall of the polysilicon film by anisotropic etching after forming an insulating film having a predetermined thickness on the entire structure; And etching the lower polysilicon film and the gate oxide film by using the insulating film spacer as an etching mask to expose the silicon substrate in the active region. 제1항에 있어서, 제1단계에서, 게이트산화막 형성전에 반도체기판 상부를 사진식각법으로 소정의 돌출부위를 형성하는 제5단계; 전체구조 상부에 소정두께의 열산화막을 형성하고, 문턱전압 조절용 불순물을 이온주입한 후, 상기 열산화막을 제거하는 제6단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The semiconductor device of claim 1, further comprising: in the first step, forming a predetermined protrusion on the semiconductor substrate by photolithography before forming the gate oxide film; And a sixth step of forming a thermal oxide film having a predetermined thickness on the entire structure, ion implantation of a threshold voltage adjustment impurity, and then removing the thermal oxide film. 제2항에 있어서, 상기 제2단계 수행후, 활성영역에 불순물을 이온주입하되, 음과 양의 서로 상반되는 소정각도로 경사지게 하여 2회 반복 주입하는 제7단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.3. The method of claim 2, further comprising a seventh step of implanting impurities into the active region after the second step, and repeatedly injecting twice by inclining at a predetermined angle opposite to each other. Transistor manufacturing method. 제3항에 있어서, 상기 제4단계 수행 후, 노출된 상기 실리콘기판에 불순물을 주입하여 소스/드레인영역을 형성하는 제8단계; 노출된 실리콘기판 상부에 전이금속막을 형성한 후, 실리사이드화하는 제9단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 3, further comprising: forming an source / drain region by implanting impurities into the exposed silicon substrate after performing the fourth step; And forming a transition metal film on the exposed silicon substrate, followed by a silicide process. 제3항에 있어서, 상기 제8단계 수행 후, 전체구조 상부에 열산화막을 형성하는 제10단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.4. The method of claim 3, further comprising a tenth step of forming a thermal oxide film on the entire structure after performing the eighth step. 제3항에 있어서, 제8단계 수행중, 상기 절연막 스페이서 및 자연산화막 상부에 불필요한 전이금속막이 형성될 경우 황산과 과산화수소의 혼합용액으로 제거하는 제11단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The transistor manufacturing method of claim 3, further comprising an eleventh step of removing an unnecessary transition metal film on the insulating film spacer and the natural oxide film with a mixed solution of sulfuric acid and hydrogen peroxide during the eighth step. Way. 제3항에 있어서, 제8단계 실시중, 상기 절연막 스페이서 및 자연산화막 상부에 불필요한 전이금속막 형성될 경우 상기 전이금속막을 산화시키는 제12단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.4. The method of claim 3, further comprising a twelfth step of oxidizing the transition metal film when an unnecessary transition metal film is formed on the insulating film spacer and the natural oxide film during the eighth step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028661A 1994-11-02 1994-11-02 Method of manufacturing mosfet KR0170436B1 (en)

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KR1019940028661A KR0170436B1 (en) 1994-11-02 1994-11-02 Method of manufacturing mosfet

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KR960019768A true KR960019768A (en) 1996-06-17
KR0170436B1 KR0170436B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100835522B1 (en) * 2006-12-27 2008-06-04 동부일렉트로닉스 주식회사 Semiconductor device and method for manufacturing thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542943B1 (en) * 1998-12-30 2006-05-09 주식회사 하이닉스반도체 Repair etching method of semiconductor device
KR20030044340A (en) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 Method of forming a transistor in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100835522B1 (en) * 2006-12-27 2008-06-04 동부일렉트로닉스 주식회사 Semiconductor device and method for manufacturing thereof

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