JPS62112375A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high speed operation by a method wherein impurity layers which have lower concentrations than a substrate are formed with good controllability with respect to a drain region to reduce a parasitic capacitance between the drain region and the substrate. CONSTITUTION:A conductive polycrystalline Si gate electrode 6 and P<->type layers 7 are formed on a P-type Si substrate 1 with insulating isolation layers 2 by using a gate oxide film 3 and an Si3N4 mask 5 as predetermined. P doped polycrystalline Si 8 is applied and removed by RIE except remaining parts on the side surfaces and ions are implanted by using the gate electrode as a mask and a heat treatment is performed to form N<-> layers 10a and 11a. After the mask 5 is removed, a resist mask 12 is applied and an ion implantation and a heat treatment are performed to form N<+>type layers 10b and 11b. After the resist 12 is removed, SiO2 13 is applied and apertures are selectively formed and electrodes 15 are attached. With this constitution, the layers which have lower concentrations than the substrate can be formed at predetermined positions in a self-alignment manner and a depletion layer is significantly extended toward the substrate 1 side in the drain region 11 side so that the parasitic capacitance between the drain region and the substrate can be reduced and high speed operation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly improves the vicinity of the drain 1lfi.

[Technical background of the invention]

As is well known, for example, MO3 type field effect transistor (F
With the miniaturization of elements, the electric field near the drain becomes stronger in ET), which causes the generation of photocarriers, which has an adverse effect. yD oped D ra
in) the technology is known. This technology alleviates electric field concentration by forming a low concentration diffusion layer in the drain region near the channel and extending the depletion layer toward the train region (Reference: 5eiki Oc+ura e
tal, IEEE Trans, onEl
ectron Devices, VO+ED
-27, N08, p1359 (1980)). Also,
As another means, in order to reduce the parasitic resistance of the N-type drain region of the LDD 1111 structure, a patent proposal has been made in which the side wall formation on the drain region is formed of the same material as the gate electrode.

[Problems with background technology]

Incidentally, in LDD IN transistors, even when the same material as the gate is used for the gate sidewalls, the electric field is alleviated by forming a low S degree layer on the drain side. However, with the miniaturization of elements, the source
In order to prevent punch-through between drain regions and for reasons such as threshold control, the substrate concentration must be increased. Therefore, the depletion layer extending in the channel direction at the end of the drain region becomes smaller, which also causes electric field concentration. the result,
This electric field concentration accelerates the gear, and impact ionization causes gear rift.

Particularly in the NMO8+- transistor, holes flow through the substrate and cause fluctuations in the substrate potential, while electrons are injected into the Goo1- insulator, and due to the generation of the Elek1 Heron trap and the $1-3iQ2 interface level, the threshold value is and a decrease in phase H conductance.

Furthermore, since the drain region is surrounded by the highly doped substrate, the depletion layer between the drain region and the substrate does not extend, increasing the capacitance. As a result, this capacitance becomes anomalous FJffi, which impedes high-speed operation of the device.

(Object of the Invention) The present invention has been made in view of the above circumstances, and it is possible to form an impurity layer of the first conductivity type at a lower concentration than the semiconductor substrate in a predetermined position in a self-aligned manner, and to An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the parasitic capacitance between the semiconductor device and the device and increase the speed of operation of the device.

(Summary of the Invention) The present invention includes a step of forming a conductive pattern on a semiconductor substrate of a first conductivity type via a gate oxide film, and using the conductive pattern as a mask to inject impurities of a second conductivity type onto the surface of the substrate. A step of introducing an impurity layer of the first conductivity type with a lower concentration than that of the substrate, and forming a conductive film on the entire surface and then etching it by reactive ion etching to form a conductive film on the conductive pattern. At least drain rjI Ii
A step of forming a gate electrode from a conductive pattern remaining on the wall to be formed before i formation, and introducing an impurity of a second conductivity type into the impurity layer using the gate electrode as a mask. The method is characterized by comprising a step of forming a region. Therefore, in a normal MOSFET, 1
~Since the source/drain regions are formed by ion-implanting impurities of the opposite conductivity type to the substrate using the N pole as a mask, it is not possible to form a low concentration layer of the conductivity type of the substrate on the channel side in a self-aligned manner. . In contrast, according to the present invention, since impurities are introduced into the substrate using the conductive pattern as a mask, the impurity layer can be formed in a self-aligned manner with respect to the conductive pattern and can be formed in a controlled manner with respect to the drain region. Along with Train rRIJi! The parasitic capacitance between the substrate and the substrate can be reduced.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1(a) to (e).

(1) 1:f, not11i1171al12X 101
A field oxide film 2 was formed on the surface of a single-crystal silicon substrate 1 with a thickness of 1 cm'f''!! by a selective oxidation method using a silicon nitride film. A gate oxide film 3 with a thickness of 150 μm was formed in the device region.Next, a polycrystalline silicon film with a thickness of 5000 μm and a silicon nitride film (not shown) with a thickness of 200 μm were deposited on the entire surface, and then photolithography was performed. Using the resist (4) as a mask, the silicon nitride film and polycrystalline silicon pattern are etched by reactive ion etching (RYE),
A nitride film pattern 5 and a polycrystalline silicon pattern 6 were formed, respectively. However, the resistance of the polycrystalline silicon film is lowered by a POCQ3 diffusion layer before the silicon nitride film is deposited, so that it can be used as a metallic conductor.

Furthermore, using the photoresist 1- as a mask, phosphorus was applied to the element region at an acceleration voltage of 100 KeV at a dose! l 2 X
Two-stage ion implantation was performed under the conditions of 10" rtm2, acceleration voltage 200 KeV, and dose ff12X10"Can'.
After removing the photoresist, heat treatment was performed. As a result, a P- region 7.7 was formed which was fairly flat and whose peak concentration did not exceed the impurity concentration of the substrate 1. Furthermore, a phosphorus-doped polycrystalline silicon film 8 having a thickness of 3000 nm was deposited over the entire surface (as shown in FIG. 1(b)).

(2) Next, the polycrystalline silicon film 8 was etched by RIE, leaving this polycrystalline silicon gI8 on the sidewalls of the polycrystalline silicon pattern 6.

As a result, a gate electrode 9 was formed from the polycrystalline silicon pattern 6 and the remaining polycrystalline silicon film 8. Next, the gate 1! Using tfi9 as a mask, phosphorus was applied to the element region at an acceleration voltage of 40KeV and a dose of ff15X10.
Ion implantation was performed under the conditions of 13α, N”iJ[10a, 1
1a (as shown in FIG. 1(C)). Next, after peeling off the nitride film pattern 4 using hot phosphoric acid, a photoresist 12 was formed so as to cover the front gate 1 and the electrode 9. Furthermore, using the photoresist 12 as a mask, arsenic is applied to the element region at an acceleration voltage of 40 KeV and a dose of I! 15
Ion implantation was performed under the conditions of xlo"2, heat treated, and N"f
IAljtlob, 11b was formed. Kono result, N″
'r4' r4 region 1N" flu region l Ob forms the source region 10, N-Gi[11a, N4" region b
A drain region 11 was formed using xiib (FIG. 1 (d>disclosure). After that, the resist 12 was peeled off, and the entire surface was coated with S!02M1 as a passivation layer.
13 was formed. Continuing with the source/drain order 11i! After selectively removing the 5iOz film 13 corresponding to 10.11 and forming a contact hole 14, an Afi wiring 15 was formed here to form an N-channel MOS transistor (as shown in FIG. 1(e)). .

According to the present invention, the source/drain regions 10.11 are made of P
Since the depletion layer is provided on the surface of the -gA region 7, the depletion layer extends considerably toward the substrate, and the parasitic capacitance between the drain order 1 or 11 and the substrate 1 can be reduced. Therefore, the device can be operated at high speed. Further, the P- region is formed by ion-implanting phosphorus into the substrate 1 using the polycrystalline silicon pattern 6 as a mask, and the P- region is formed by ion-implanting phosphorus into the substrate 1 using the polycrystalline silicon pattern 6 as a mask. N-region [11a,
The N+ regions 1j111b are also formed by ion implantation using the gate electrode 9 and )A resist 12 as masks, respectively.
Therefore, the drain/in region M11 can be formed in the P layer 7 with good controllability.

Next, the operation of the N-channel MOS l-transistor according to the present invention will be explained with reference to FIGS. 2 and 3 while comparing it with that of the conventional one. Here, FIG. 2 shows the conventional case, and FIG. 3 shows the case of the present invention. Furthermore, in order to represent the extension of the depletion layer 21 near the drain region 11, a case is shown in which 5V is applied to the drain region 11 and the gate electrode 9, and Ov is applied to the source region 10 and the substrate 1. That is, in the conventional case, the depletion layer 21 of the drain region 11 does not extend much because the impurity concentration of the M temporary 1 is high. In contrast, in the case of the present invention, since the drain latall is provided in the low 1 degree impurity layer (P-1), the depletion layer 21 extends considerably toward the substrate side. Furthermore, an inversion layer 22 induced by the Goo 1-electric current J'f (5v) is formed on the channel surface. Furthermore, the potential at the pinch-off point 23 (pinch-off voltage Vp) is influenced by the impurity concentration below it, and in the conventional case, vp is low;
In the case of the present invention, Vρ becomes high. Since 5V is applied to the drain region 11, the electric field between the pinch-off point 23 of the depletion layer 22 on the surface and the drain region 11 is smaller in the present invention.

Further, in the case of the present invention, since the concentration near the toilet-in region is low, the depletion layer 21 tends to extend toward the channel side, and the width of the surface depletion layer increases, and the electric field applied to both ends becomes further smaller. Furthermore, the inside of the inversion 8122 is the source region tJ.
Electrons running toward the drain region 11 from 10 are accelerated by the electric field in the depletion layer 21 on the surface, and
Hot carriers are generated by ionization of the rays. However, in the present invention, since the electric field in the depletion layer 21 is small, it is possible to obtain a highly reliable device in which invacuum 1-ionization is less likely to occur.

In the above embodiment, the gate electrode was formed by leaving the polycrystalline silicon film as a conductive film on the sidewall of the polycrystalline silicon pattern. However, the present invention is not limited to this. A polycrystalline silicon pattern 31 may be formed to cover the polycrystalline silicon pattern 6 as shown in the figure.

Alternatively, as shown in FIG. 5, it may be formed to cover the polycrystalline silicon pattern 6 on the drain region 11 side.

Further, in the above embodiment, a polycrystalline silicon film is used as the conductive film, but the present invention is not limited to this, and a metal film such as MO may also be used.

Furthermore, in the above embodiment, when forming the N+ region, FIG.
Although ions were implanted using a photoresist as a mask as shown in d), the present invention is not limited thereto. For example, S i 0 on the entire surface
After depositing 2 m, it may be left on the sidewalls of the polycrystalline silicon pattern using RIE, and ions may be implanted using this as a mask.

[Efficacy of invention]

As detailed above, according to the present invention, the a
lllf impurity layer to the drain region! To those who can form illumination easily, we provide a method for manufacturing a semiconductor device that reduces the parasitic capacitance between the drain region and the semiconductor substrate and enables high-speed operation of the device.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing method of an N-channel MO8l-transistor according to an embodiment of the present invention in the order of steps, and FIG. 2 shows the operation of a conventional N-channel MO8l-transistor. FIG. 3 is a cross-sectional view for explaining the operation of the N-channel MOS transistor according to the present invention, and FIGS. 4 and 5 are respectively for explaining the method of forming a conductive film according to the present invention. FIG. DESCRIPTION OF SYMBOLS 1... P-type single crystal silicon substrate, 2... Field oxide film, 3... Gate oxide film, 5... Nitride film pattern, 6... Polycrystalline silicon pattern, 7... P one layer, 8.31... polycrystalline silicon film, 9... goo j
'-electronic (↓, 10... source region, 10a, 11a,
...N- region, 11...Drain region, 10b, 11
b...N+ region 12...To the follow register 1, 13
... S i 02 film, 14 ... contact hole, 15 ... A ° C wiring, 21 ... depletion layer, 22 ...
Inversion layer, 23...pinch-off point. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (3)

[Claims] (1) A step of forming a conductive pattern on a semiconductor substrate of a first conductivity type via a gate oxide film, and using this conductive pattern as a mask, impurities of a second conductivity type are introduced into the surface of the substrate. forming a low concentration impurity layer of the first conductivity type; depositing a conductive film on the entire surface; etching it by reactive ion etching; a step of forming a gate electrode from the conductive pattern left on the side wall thereof; and using the gate electrode as a mask, introducing a second conductivity type impurity into the surface of the impurity layer to form a second conductivity type impurity region. A method for manufacturing a semiconductor device, comprising the steps of: (2) The method of manufacturing a semiconductor device according to claim 1, wherein the second conductivity type impurity region is a source/drain region. (3) After introducing a second conductivity type impurity into the impurity layer using the gate electrode as a mask to form a second conductivity type low concentration impurity region, a mask material is applied to cover at least the side where the drain region is formed of the gate electrode. A method for manufacturing a semiconductor device according to claim 1, characterized in that a second conductivity type impurity is introduced into the low concentration impurity region to form a high concentration impurity region. .