GB2038088A - Semiconductor structures - Google Patents

Semiconductor structures Download PDF

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GB2038088A
GB2038088A GB7941941A GB7941941A GB2038088A GB 2038088 A GB2038088 A GB 2038088A GB 7941941 A GB7941941 A GB 7941941A GB 7941941 A GB7941941 A GB 7941941A GB 2038088 A GB2038088 A GB 2038088A
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semiconductor
masking layer
region
layer
doped region
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Raytheon Co
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Raytheon Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

In a semiconductor structure a masking layer 12 is formed to cover a portion of a surface of a semiconductor 10, a first doped region 36 is formed by ion implantation in a portion of the semiconductor exposed by the masking layer 12, a chemical etchant is brought into contact with the masking layer 12, reducing the area of the masking layer covering the semiconductor and thereby exposing a second, different portion 47 of the semiconductor contiguous to the first exposed portion 36 of the semiconductor, and particles capable of establishing a doped region in the semiconductor layer are introduced by ion implantation into the second exposed portion 47 of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, the chemically etched masking layer 12 inhibiting the particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self- aligned gate region (second region) may be formed in a field effect device having a small channel length. In the complete device regions 36 and 38 are the source and drain and a drift region underlies the mask 12. <IMAGE>

Description

SPECIFICATION Semiconductor structures The present invention relates generally to semiconductor structures and manufacturing methods. In particular it relates to short channel metal-oxide-semiconductor (MOS) field-effect transistor structures and manufacturing methods.
Known high performance MOS field-effect transistors generally require channel lengths below 3 lim and even as short as 0.5 to 1.0 m. It is very difficult to obtain these small dimensions with present photolithographic techniques. This difficulty has lead to the development of several types of transistors having channel lengths defined by means other than photolithography. One such device is generally referred to as a D-MOS transistor, where two diffusions of dopants of opposite type conductivity are driven to different depths in a silicon substrate through one, noncritical mask opening, resulting in a channel length equal to the difference in the depth of the electrical junctions formed.Here, however, since the doping concentration varies along the channel, the "turn-on" voltage, which is a function of doping, is critically dependent on the location in the channel and the concentration at which the two diffusion profiles intersect. In practice, therefore, the "turn-on", or threshold voltage, will exhibit relatively large fluctuations because of the difficulty in controlling the two diffusions.
Other types of transistors wherein the channel width is controlled by means other than photolithography are the so-called "V-MOS" and "D-V-MOS" transistors. With the V-MOS transistor the channel length is generally defined by the up-diffusion of an implant of boron from an n-type substrate into a ptype epitaxial layer formed on the substrate, in combination with the intersection of the implant with the walls of a V-shaped groove which is etched through the epitaxial layer, down into the substrate. In the D-V-MOS transistor the channel is generally defined by the diffusion of an implant of boron from the top surface, through an n + layer forming the source and drain, and again the intersection of the implanted zone with the walls of a Vshaped groove.
According to the present invention, there is provided a method of forming a semiconductor structure, wherein a first masking layer is formed to cover a portion of a surface of a semiconductor having a first type conductivity, a first doped region is formed in a portion of the semiconductor exposed by the first masking layer, a chemical etchant is brought into contact with the first masking layer, reducing the area of the masking layer covering the semi-conductor and exposing a second, different portion of the semi-conductor contiguous to the first exposed portion of the semiconductor, and particles are introduced into the second exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, the chemically etched masking layer inhibiting the particles from becoming introduced into the portion of the semi-conductor disposed beneath the etched masking layer.
In a preferred embodiment of the present invention a second masking layer is formed over the first masking layer, the second masking layer remaining over the first-mentioned masking layer while an edge of the first masking layer is chemically etched. The second masking layer restricts the chemical attack of the etchant to the edge of the first masking layer.
Furthermore, the structure is formed in a mesa-shape with side walls of the structure being oxidized for device isolation. The first and second masking layers may be silicon dioxide and silicon nitride respectively. During the oxidation process the second masking layer remains over the first masking layer, enabling the selective oxidation of the walls of the silicon semiconductor, but preventing oxidation of the first masking layer.
In a further embodiment of the present invention the masking layer is used to form source and drain regions of a field effect device. The particles are ion implanted to form a gate region continuous to one of the source and drain regions. The channel length of this gate region is accurately controlled by the chemical etching process. The masking layer used to form the source and drain regions is, after being chemically etched, used as an ion implantation mask for forming the gate region. In this way the process is selfaligning since the mask used to form the source and drain regions is, after being etched, used to form the gate region. The masking layer includes a layer of silicon dioxide. A drift channel is formed in the silicon layer disposed beneath the silicon dioxide masking layer, to electrically connect the ion implanted gate region to the source and drain regions.
With such techniques the field effect device has a uniformly doped short channel formed by ion implantation. Furthermore, the channel length depends on an accurately controlled chemical etching process. Still further, a relatively thick oxide or insulator layer is formed over the drift region so that when a gate electrode is formed over this oxide layer, any parasitic capacitance between the electrode and the drift region is reduced by this thick oxide layer.
The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figures 1-9 are diagrammatic cross-sectional views of a portion of a field effect device at various stages of manufacture, and Figure 10 is a diagrammatic cross-sectional view# of a portion of the field effect device according to an alternative embodiment of the invention, at an intermediate stage of manufacture.
Referring now to Figs. 1-9, the fabrication of a field effect device will be described. As shown in Fig. 1, a p-type silicon substrate 10, preferably having a surface parallel to the < 100 > cyrstallographic plane and having a doping concentration in the range of 5 X 10'4 to 1015 atoms per cm3, is coated with a 1500 to 3000 A thick silicon dioxide layer 12 by conventional thermal oxidation, or chemical vapour deposition, or a combination of both.
Next the silicon dioxide layer 12 is coated with a silicon nitride layer 14, here in the order of 1500 A thick, using conventional chemical vapour deposition. A photoresist layer 16 is formed over the silicon nitride layer 14 and is selectively removed using conventional photolithography to form a mask 18, as shown. The photoresist mask 18 is used to remove exposed portions of the silicon nitride layer 14 and the then exposed silicon dioxide layer 12 adjacent the mask 18, using any conventional technique. For example, the exposed portions of the silicon nitride layer 14 and the then exposed portions of the silicon dioxide layer 12 may be removed by conventional plasma etching.Alternatively the exposed silicon dioxide layer 12 may be removed using a chemical etchant, i.e. hydrofluoric acid, as will become apparent hereinafter, the composite silicon dioxide layer 12 and silicon nitride layer 14 are etched away from the field, or isolation region, while they are retained over the mesa shaped region shown in Fig. 2. The remaining portions of the composite silicon dioxide layer 12 and silicon nitride layer 12 and silicon nitride layer 14 form an etch resistant mask 20, as shown.
The portions of the silicon substrate 10 exposed by the mask 20 are brought into contact with a suitable etchant, either an isotropic or anisotropic etchant, to etch the exposed portions of the silicon substrate 10 to a depth in the order of 3000 to 4000 A, as shown.
The surface of the structure thus formed is exposed to ion implanted particles 22, here boron atoms, with a dosage of 5 X 1013 atoms per cm2 to 5 X 10'4 atoms/cm2 and an implant energy in the order of 40 Kev. The structure is then heated in a conventional manner to anneal any implant damage and to activate the implanted boron atoms to form ptype conductivity regions 24, as shown.
Referring now to Fig. 3, the structure is then oxidised to form a 6000-8000A thick silicon dioxide layer 26 on the side walls of the mesa-shaped silicon substrate 10 thereby forming a surface in the isolation regions which is substantially co-planar with the device surface. (It should be noted that during the oxidation the boron dopant is driven further into the silicon substrate 10.) The boron implant, i.e. p-type conductivity regions 24 (Fig. 2), prevents the formation of an inversion layer on the surface of the high resistivity silicon substrate 10 which would destroy de-- vice isolation.
A photoresist layer 28 is deposited over the surface of the structure and then suitably masked and etched, using conventional photolithographic-chemical etching techniques, to form a mask 30, as shown in Fig. 3. The portions of the silicon nitride layer 14 and silicon dioxide layer 12, exposed by the photoresist mask 30, are removed in any conventional manner, similar to that described in connection with Figs. 1 and 2, to expose portions of the underlying surface of the silicon substrate 10, wherein the source and drain regions 36 and 38 of the device will be formed, as shown in Fig. 4. The remaining portions of the composite silicon nitride layer 14 and silicon dioxide layer 12 form an ion implantation mask 32, as shown in Fig. 4.
Particles, here aresenic atoms, are ion implanted into the portions of the silicon substrate 10 exposed by the ion implantation mask 32. Here a dosage of 5 X 1014 atoms/cm2 an an implant energy level of 140 Kev is used. The structure is heated to anneal any implant damage and to activate the implanted arsenic atoms to form the n-type conductivity source and drain regions 36 and 38 respectively, as shown, in the regions of the silicon substrate 10 which are adjacent the region of the substrate 10 covered by the ion implantation mask 32. The depth of the source and drain regions 36 and 38 is in the order of 1000 A.
Referring now to Fig. 5, a photoresist layer 40 is formed over the surface of the structure, using conventional photolithographic techniques to form an etch resistant mask 42, as shown. It is noted that a window 44 is formed in the photoresist layer 40 to expose a portion of the silicon substrate 10 having the source region'36 formed therein, the side portions of the silicon nitride layer 12, the side portions of the silicon dioxide layer 14 adjacent the source region 36, and a portion of the upper surface of the silicon nitride layer 14. The purpose of the mask 42 is to expose only the edge of the source region 36, while covering the drain region 38. This masking step is then relatively noncritical. A chemical etchant, here a hydrofluoric acid solution, which selectively etches silicon dioxide without attacking either silicon, silicon nitride or photoresist, is brought into contact with the surface of the structure. The chemical etchant passes through the window 44 to attack the exposed side portions of the silicon dioxide layer 12 and thereby selectively etch away and remove the exposed portion of the silicon dioxide layer 12. The chemical etchant there fore reduces the area of the silicon substrate 10 which is disposed beneath the chemically etched silicon dioxide layer 12, exposing a gate region 47 (Fig. 6) which is contiguous to the source region 36. As will be described, the remaining portion of the silicon dioxide layer 12 will provide an ion implantation mask for forming gate region 47 of the field effect device.The silicon dioxide layer 12 is therefore etched back a length L, here in the order of 0.5 to 2.5 ym, the length L, being the channel length of the field effect device. It is noted that the length L of the gate region is determined by the amount of chemical etching provided to the silicon dioxide layer 12.
This chemical etching process is readily controllable by the etching time duration and chemical etchant strength which is itself controllable by proper dilution. Furthermore, the etching processes may be monitored using a high powered measuring microscope. The resulting structure, after photoresist layer 40 is removed, is shown in Fig. 6.
Referring now to Fig. 7, the silicon nitride layer 14 is removed in any conventional manner, and a thin silicon dioxide layer 46 is thermally grown over the surface of the structure. The thin silicon dioxide layer 46 is here in the order of 300 to 1000 A thick and, as will be shown, provides the gate oxide for the device. (It is noted that the silicon dioxide layer 46 is thicker over the surface of the silicon substrate 10 than over the silicon dioxide layer 12.) Following this thermal oxidation, particles, here boron atoms, are ion implanted into the surface of the structure. It is noted that the thicker silicon dioxide layer 12 serves as an ion implantation mask so that the boron atoms become implanted only into the portion of the silicon substrate 10 which is disposed beneath the thinner oxide layer 46.The silicon dioxide layer 12 inhibits boron atoms from becoming implanted in the portions of the silicon substrate 10 disposed beneath the silicon dioxide layer 12. The concentration of boron atoms in the silicon substrate 10 is here in the order of 3 X 1012 atoms/cm2 and hence, after annealing, a ptype conductivity region is formed in the gate region 47, as shown in Fig. 7. It is noted that the concentration of n-type dopant in the source and drain regions 36 and 38 is in the order of 3 x 10'9 atoms/cm3 or higher and hence is not substantially affected by the boron implant which results in a concentration several orders of magnitude less than 3 X 10'9 atoms/cm3.
Referring now to Fig. 8, a photoresist layer 50 is deposited over the surface of the structure and patterned into a source/drain contact mask 52, as shown, using conventional photolithographic-chemical etching techniques. A suitable chemical etchant is then brought into contact with the mask 52 and the portions of the silicon dioxide layer 46 exposed by the windows 51 and 53 formed in the mask 52, to selectively remove such exposed portions of the silicon dioxide layer 46 which are disposed over portions of the source and drain regions 36 and 38, respectively, as shown in Fig. 9.After the photoresist layer 50 has been removed, in any conventional manner, a suitable metallisation layer 54 is deposited over the surface of the structure, i.e. over the remaining portions of the silicon dioxide layer 46 and, through the windows 51 and 53 formed therein, onto the exposed surfaces of the silicon substrate 10 which are disposed over portions of the source and drain regions 36 and 38 to form ohmic contact with the regions 36 and 38.
The metallisation layer 54 is then patterned, in any conventional manner, i.e. by photolithographic-chemical etching processing, into source, drain and gate electrodes S, D and G, respectively, as shown in Fig. 9. It should be noted that although the gate electrode G overlaps the source region 36 and the drain region 38 as well as the gate region 47 and a drift region 56, the gate electrode G is separated from the drift region 56 by the thick insulating layer of silicon dioxide 12, which is in the order of 1500 A to 3000 A thick.
In the MOS field effect device thus formed, and shown in Fig. 9, the drift region 56, which is disposed beneath the thick silicon dioxide layer 12, connects the gate region 47 to the drain region 38. The drift region 56 is an n-type conductive region formed at the surface of the silicon substrate 10 adjacent the silicon dioxide layer 12 because of fixed positive charge, generally referred to as Q55 present in the silicon dioxide layer 12, and also as a result of the positive gate voltage which turns the drift region 56 "on" to a greater degree when the short channel is biased "on". Also, as is known, when the silicon dioxide layer 12 is initially thermally grown over the surface of the silicon substrate 10, as discussed in connection with Fig. 1, and then cooled in an oxygen environment, positive charges are created in the silicon dioxide layer 12 to create a strong inversion on the surface of the contiguous high resistivity p-type conductivity silicon substrate 10 to form an n-type conductivity drift region 56.
Alternatively, the drift region 56 may be formed by ion implanting a suitable n-type dopant, i.e. phosphorus atoms, into the surface of the structure either prior to or subsequent to the ion implantation of the boron atoms discussed in connection with Fig. 7.
That is, referring to Fig. 10, after the thin silicon dioxide layer 46 is deposited over the surface of the structure, phosphorus atoms are ion implanted into the silicon substrate 10 which is disposed beneath the silicon dioxide layer 12, as shown, to form, after annealing, the drift region 56'. The boron atoms are then ion implanted to form the gate region 47; however, the depth of the implanted boron atoms is less than the depth of the implanted phosphorus atoms and such implanted boron atoms do not enter the drift region 56'.
Furthermore, it should be noted that the implanted phosphorus atoms are disposed beneath the source, drain and gate regions 36, 38 and 47 because the silicon dioxide layer 46 disposed over the regions 36, 38 and 47 is thinner than the thick silicon dioxide layer 12 disposed over the drift region 56'. The phosphorus implant serves to reduce the impedance of the drift region 56' and may also serve to form a buried channel in the drift region 56' to reduce gate electrode capacitance. The structure is then processed as described in connection with Figs. 8 and 9 to complete the MOS field effect device.
The length of the drift region 56 (or 56') may be adjusted to suit the desired circuit conditions and may range from about one micrometer to five micrometers. The drift region 56 (or 56') eliminates the short channel effects (i.e. punch through from'drain to source and dependance of the gate threshold voltage on the drain voltage), which affect many short channel devices, without much additional expenditure in wafer area. Furthermore, the techniques described above enable the fabrication of devices suited for the relatively high voltage levels prevailing in many analog circuits and charge coupled devices.
Having described the preferred embodiments of the present invention, it is evident that other embodiments incorporating these concepts may be used. For example, a relatively thin silicon nitride layer, 300-500 A thick, may be formed between the metallisation layer 54 and the silicon dioxide layer 46. Also, the drift region 56 may be formed by ion implanting phosphorus or arsenic atoms into the silicon substrate 10 prior to the formation of the silicon dioxide layer 12 and the silicon nitride layer 14. Still further, the source and drain electrodes S and D may be formed in a separate masking step other than that used to form the gate electrode G.
Also, the gate electrode G may be doped polycrystalline silicon, aluminum or a composite layer of titanium and aluminum. Furthermore, the gate electrode G need not extend to the overlap of the drain region 38, but can terminate at one end over the silicon dioxide layer 12. In addition, while an n-channel device has been described, a p-channel device may be formed in analogous fashion by using dopants of opposite polarity. Also, the terms source and drain regions may be used interchangeably.

Claims (11)

1. A method of forming a semiconductor structure, wherein a first masking layer is formed to cover a portion of a surface of a semiconductor having a first type conductivity, a first doped region is formed in a portion of the semiconductor exposed by the first masking layer, a chemical etchant is brought into contact with the first masking layer, reducing the areas of the masking layer covering the semiconductor and exposing a second, different portion of the semiconductor contiguous to the first exposed portion of the semiconductor, and particles are introduced into the second exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to-the first doped region, the chemically etched masking layer inhibiting the particles from becoming introduced into the portion of the semiconductor disposed beneath the etched masking layer.
2. A method according to claim 1, wherein the first doped region is of opposite type conductivity to the semiconductor having a a first type conductivity, and the second doped region is of enhanced first type conductivity.
3. A method according to claim 1 or 2, wherein the first masking layer is an insulating layer.
4. A method according to claim 3 insofar as dependant on claim 2, wherein two spaced regions of opposite type conductivity are formed to provide the source and drain regions of a field effect device, the portion of semiconductor disposed beneath the etched masking layer forming a drift region of the field effect device, and the region of enchanced first type conductivity forming a gate region of the field effect device.
5. A method according to any of claims 1 to 4, wherein a second masking layer is formed over the first masking layer before bringing the chemical etchant into contact with an edge of the first masking layer to etch into that edge and thereby effect the reduction of area of the first masking layer, the second masking layer inhibiting exposure of the surface of the.first masking layer to the chemical etchant.
6. A method according to claim 5, wherein the second masking layer is an insulating layer.
7. A method according to any of claims 1 to 6, wherein the or each first doped region is formed by ion implantation.
8. A method according to any of claims 1 to 7, wherein the second doped region is formed by ion implantation.
9. A method according to any of claims 1 to 8, wherein an insulating layer is formed over the first masking layer, the insulating layer being formed with a thickness substantially less than the thickness of the masking layer.
10. A semiconductor device comprising a semiconductor body having a source region; and a drift region contiguous to the gate region and a drain region which is electrically connected to the source region through the gate region and the drift region, a first insulating layer disposed over the gate region, a second thicker insulating layer disposed over the entire drift region, source and drain electrodes in contact with the source and drain regions, and a gate electrode disposed over the first insulating layer and at least a portion of the second, thicker insulating layer.
11. A semiconductor device according to claim 10, wherein implanted particles forming the drift region are disposed near to the surface of the semiconductor body in the drift region and more deeply in the body beneath the other regions.
GB7941941A 1978-12-15 1979-12-05 Semiconductor structures Expired GB2038088B (en)

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CA (1) CA1138571A (en)
DE (1) DE2950413A1 (en)
FR (2) FR2445618A1 (en)
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IT (1) IT1120149B (en)

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GB2124427A (en) * 1982-07-08 1984-02-15 Gen Electric Insulated gate semiconductor devices
US4442589A (en) * 1981-03-05 1984-04-17 International Business Machines Corporation Method for manufacturing field effect transistors
US5151374A (en) * 1991-07-24 1992-09-29 Industrial Technology Research Institute Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode
US5604139A (en) * 1994-02-10 1997-02-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device

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JPH0427799Y2 (en) * 1986-08-28 1992-07-03
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DE2703877C2 (en) * 1977-01-31 1982-06-03 Siemens Ag, 1000 Berlin Und 8000 Muenchen Short channel MIS transistor and process for its manufacture
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US4173818A (en) * 1978-05-30 1979-11-13 International Business Machines Corporation Method for fabricating transistor structures having very short effective channels

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442589A (en) * 1981-03-05 1984-04-17 International Business Machines Corporation Method for manufacturing field effect transistors
GB2124427A (en) * 1982-07-08 1984-02-15 Gen Electric Insulated gate semiconductor devices
US5151374A (en) * 1991-07-24 1992-09-29 Industrial Technology Research Institute Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode
US5604139A (en) * 1994-02-10 1997-02-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5741718A (en) * 1994-02-10 1998-04-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device

Also Published As

Publication number Publication date
FR2445618B1 (en) 1985-03-01
GB2038088B (en) 1983-05-25
DE2950413C2 (en) 1989-12-28
FR2445618A1 (en) 1980-07-25
FR2453501B1 (en) 1984-09-07
JPS6326553B2 (en) 1988-05-30
CA1138571A (en) 1982-12-28
FR2453501A1 (en) 1980-10-31
DE2950413A1 (en) 1980-06-26
JPS5583270A (en) 1980-06-23
IT1120149B (en) 1986-03-19
IT7951008A0 (en) 1979-12-06

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