CA1138571A - Semiconductor structures and manufacturing methods - Google Patents
Semiconductor structures and manufacturing methodsInfo
- Publication number
- CA1138571A CA1138571A CA000339782A CA339782A CA1138571A CA 1138571 A CA1138571 A CA 1138571A CA 000339782 A CA000339782 A CA 000339782A CA 339782 A CA339782 A CA 339782A CA 1138571 A CA1138571 A CA 1138571A
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- CA
- Canada
- Prior art keywords
- semiconductor
- insulating layer
- forming
- region
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title description 7
- 230000000873 masking effect Effects 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000126 substance Substances 0.000 claims abstract description 21
- 239000002245 particle Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 230000002401 inhibitory effect Effects 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 84
- 235000012239 silicon dioxide Nutrition 0.000 description 42
- 239000000377 silicon dioxide Substances 0.000 description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 27
- 239000010703 silicon Substances 0.000 description 27
- 239000000758 substrate Substances 0.000 description 26
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 239000007943 implant Substances 0.000 description 8
- 125000004429 atom Chemical group 0.000 description 7
- 238000003486 chemical etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 125000004437 phosphorous atom Chemical group 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 101150068246 V-MOS gene Proteins 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 layer 12 Chemical compound 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Abstract of the Disclosure A semiconductor structure wherein a masking layer is formed to coves a portion of a surface of a semiconductor.
A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the making layer covering the semiconductor exposing a second different portion of the semiconductor contiguous to the first exposed portion of the semiconductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semi-conductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.
A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the making layer covering the semiconductor exposing a second different portion of the semiconductor contiguous to the first exposed portion of the semiconductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semi-conductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.
Description
1~385~1 .
Back round of the Invention This invention relates generally to semiconductor struc-tures and manufacturing methods and more particularly to short channel metal-oxide-semiconductor (MOS) field-effect transistor structures and manufacturing methods.
As is known in the art, high performance MOS field-effect transistors generally require channel lengths below 3~m and even as short as 0.5 to 1.0~m. It is very difficult to obtain these small dimensions with present photolithographic techniques. This difficulty has led to the development of several types o~ transistors having channel lengths defined by means other than photolithography. One such device is generally referred to as a D-MOS transistor where two ~iffusions of dopants of opposite type conductivity are driven to different depths in a silicon substrate through ~/7~
one, noncritical mask opening, resulting in a channel length equal to the difference in the depth of the electrical junctions formed. Here, however, since the doping concentration varies along the channel, the "turn-on" voltage, which is a function of doping, is critically dependent on the location in the channel and the concentration at which the two diffusion profiles intersect. In practice, therefore, the "turn-on", or threshold voltage, will exhibit relatively large fluctuations because of the difficulty to control ~he two diffusions.
Other types of transistors wherein channel width is controlled by means other than photolithography are so-called "V-MOS" transistors and "D-V-MOS" transistors. With a V-MOS
transistor the channel length is generally defined by the up-diffusion of boron from an n-type substrate into a p-type epitaxial layer formed on such substrate, in combination with a ~38571 V-shaped groove etched through the epitaxial layer, down into the substrate. In the D-V-MOS transistor the channel is generally defined by an implant of boron from the top surface, through the n+ layer forming the source and drain, and again the intersection of the implanted zone with the walls of a V-shaped groove.
113~571 Summary of the Invention In accordance with the present invention a masking layer is formed to cover a portion of a surface of a semiconductor; a first doped region is formed in a portion of the semiconductor exposed by the ~asking layer; a chemical etchant is brought into contact with the masking layer, reducing the area of the masking layer covering the semiconductor, exposing a second, different portion of the semiconductor contiguous to the first exposed por-tion of the semiconductor; and particles capable of establishing a doped region in the semiconductor are introduced into the second exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, such chemically etchet masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer.
Thus, this invention provides a method of forming a semiconductor structure comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking such portion of the semiconductor;
(b) forming a region of opposite type conductivity in a portion of the semiconductor layer unmasked by the insulating layer;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer;
(d) ion implanting particles capable of establishing a first type conductivity in the semiconductor into a portion of the semiconductor exposed by the chemically etched insulating layer forming a region of first type conductivity contiguous to both the first formed region of opposite type conductivity and a region of the semiconductor masked by remaining portions of the chemically etched insulating layer; and, (e) forming an electrode over remaining portions of the chemically ~0 etched insulating làyer and over the portion of the semiconductor exposed 1131~1571 by the chemically etched insulating layer and having formed therein the ion implanted region.
In a second aspect, this invention provides a method for forming a semiconductor structure comprising the steps of:
(a) forming an insulator over a portion of a surface of a semi-conductor structure;
(b) forming a first doped region in a portion of the semiconductor structure exposed by the insulator;
(c) bringing a chemical etchant into contact with the insulator removing edge portions thereof ~xposing a second, different portion of the semiconductor structure contiguous to the first doped region;
(d) introducing particles into the second, different portion of the semiconductor structure, the remaining unetched portions of the chemically etched insulator inhibiting such particles from becoming introduced into the portion of the semiconductor structure disposed beneath remaining portions of the insulator; and (e) forming an electrode over remaining portions of the insulator and over the second, different portion of the semiconductor structure exposed by the insulator.
In a preferred embodiment of this invention a second masking layer is formed over the first-mentioned masking layer, such second masking layer ~emaining over the first-mentioned masking layer while a portion of the first-mentioned layer is chemically removed. The second masking layer re-stricts the chemical attack of the etchant to the side of the first-mentioned masking layer.
Further, the structure is formed in a mesa-shape with side walls of such structure being oxidized for device isolation. The first-mentioned masking layer is silicon dioxide and the second masking layer is silicon nitride. During the oxidation process the second masking layer remains over the first-mentioned masking layer, enabling the selective oxidation of the walls of the silicon semiconductor, but preventing oxidation of the first-mentioned masking layer.
- 3a -1~38571 Still further, in a preferred embodiment of this invention the masking layer is used to form source and drain regions of a field effect device. The particles are ion implanted to form a gate region contiguous to one of the source and drain regions.
The channel length of this gate region is accurately controlled by the chemical etching process. The masking layer used to form the source and drain regions is, after being chemically etched, used as an ion implantation mask for forming the qate region. In this way the process is self-aligning since the mask used to form the source and drain regions is, after being etched, used to form the gate region. The masking layer includes a layer of silicon dioxide. A drift channel is formed in the silicon layer disposed beneath the silicon dioxide masking layer to electrically connect the ion implanted gate region to the source and drain regions.
With such techniques the field effect device has a uniformly doped short channel formed by ion implantation.
Furthermore, ~he channel length depends on an accurately controlled chemical etching process. Still further, a relatively thick oxide or insulator layer is formed over the drift region so that when a gate electrode is formed over this oxide layer, any parasitic capacitance between such electrode and the drift region is reduced by this thick oxide layer.
Brief Description of the Drawings The foregoing features of this invention, as well as the invention itself, may be more fully understood from the fol-lowing description read together with the accompanying drawings, in which:
FIGS. 1-9 are cross-section elevation, diagrammatical views of a portion of a field effect device according to the invention at various steps in the manufacture thereof; and FIG. 10 is a cross-sectional eleva~ion, diagrammatical view of a portion of the field effect device according to an alternative embodiment of the invention at an intermediate stage in the manufacture thereof.
Description of the Preferred Embodiments Referring now to FIGS. 1-9, the fabrication of a field effect device will be described. As shown in FIG. 1, a p-type silicon substrate 10, preferably having a surface parallel to the ~100> crystallographic plane and having a doping concen-tration in the range of 5X1014 to 1015 atoms per cm3 is coated with a 1500 to 3000 A thick silicon dioxide layer 12 by conven-tional thermal oxidation or chemical vapor deposition, or a combination of both. Next the silicon dioxide layer 12 is coated with a silicon nitride layer 14, here in the order of 1500 A thick, using conventional chemical vapor deposition. A
photoresist layer 16 is formed over the silicon nitride layer 14 and selectively removed using conventional photo-lithography to form a mask 18, as shown. The photoresis~ mask 18 is used to remove exposed portions of the silicon nitride layer 14 and the then exposed silicon dioxide layer 12 adjacent such mask 18 using any conventional technique. For example, the exposed portions of the silicon nitride layer 14 may be removed using conventional plasma etching and the then exposed portions of the silicon dioxide layer 12 are removed with a suitable chemical etchant, here a hydrofluoric acid solution or also by plasma etching. That is, as will become apparent hereinafter, the composite silicon dioxide layer 12 and silicon nitride layer 14 are etched away from the field or isolation region while they are retained over the mesa shaped Z/~ ~ ~ own in FIG. 2. The remaining portions of the composite silicon dioxide layer 12-silicon nitride layer 14 form an etch resistant mask 20, as shown. The portions of the silicon sub-strate 1~ exposed by such mask 20 are brought into contact by a suitable etchant, either an isotropic or anisotropic etchant, 113857~
to etch such exposed portions of the silicon substrate 10 to a depth in the order of 3000 to 4000 A, as shown. The sur-face of the structure thus formed is exposed to ion implanted particles 22, here boron atoms, with a dosage of 5X1013 atoms per cm2 to 5~1014 atoms/cm2 at an implant energy here in the order of 40 Kev. The structure is then heated in a conventional manner to anneal any implant damage and to activate the im-planted boron atoms forming p-type conductivity regions 24, as shown.
Referring now also to FIG. 3, the structure is then oxidized to form a 6000-8000A thick silicon dioxide layer 26 on the side walls of the mesa-shaped silicon substrate 10 and thereby form a surface in the isolation regions which is substan-tially co-planar with the device surface. (It should be noted that during the oxidation the boron dopant is driven further into the silicon substrate 10.) The boron implant, i.e. p-type conductivity regions 24 (FIG. 2), prevents the formation of an inversion layer on the surface of the high resistivity silicon substrate 10 which would destroy device isolation.
A photoresist layer 28 is deposited over the surface of the structure and then suitably masked and etched, using conventional photolithographic~chemical etching techniques to form a mask 30, as shown in FIG. 3. The portions of the silicon nitride layer 14 and silicon dioxide layer 12 exposed by the photoreslst mask 30 are removed in any conventional manner, similar to that described in connection with FIGS. 1 and 2, to expose portions of the underlying surface of the silicon substrate 10, wherein the source and drain regions 36, 38 of the device will be formed, 1~3~S71 as shown in FIG. 4. The remaining portions of the composite silicon nitride layer 14 and silicon dioxide layer 12 form an ion implantation mask 32 as shown in FIG. 4. Particles, here arsenic atoms, are ion implanted into the portions of the silicon substrate 10 exposed by the ion implantation mask 32.
Here a dosage of 5X1014 atoms/cm2 and an implant energy level of 140 Kev is used. The structure is heated to anneal any implant damage and to activate the implanted arsenic atoms to form n-type conductivity source and drain regions 36, 38 respectively, as shown, in the regions of the silicon sub-strate 10 which are adjacent the region of such substrate 10 covered by the ion implantation mask 32. The depth of the source and drain regions 36, 38 is here in the order of 1000 A.
Referring now also to FIG. 5, a photoresist layer 40 is formed over the surface of the structure, using conventional photolithographic techniques to form an etch resistant mask 42 as shown. It is noted that a window 44 is formed in the photo-resist layer 40 to expose: A portion of the silicon substrate 10 having the source region 36 formed therein; the side portions of the silicon nitride layer 12; the side portions of the silicon dioxide layer 14 adjacent the source region 36; and a portion of the upper surface of the silicon nitride layer 14.
The purpose of the mask 42 is to expose only the edge of the source region 36 while covering the drain region 38. This masking step is then relatively noncritical. A chemical etchant, here a hydrofluoric acid solution, which selectively etches silicon dioxide without attacking either silicon, silicon nitride or photoresist, is brought into contact with the surface of the structure. The chemical etchant passes through the window 44 tG attack the exposed side portions of the silicon dioxide layer 113857~
12 and thereby selectively etch away and remove such exposed portion of the silicon dioxide layer 12. The chemical etchant therefore reduces the area of the silicon substrate 10 dis-posed beneath the chemically etched silicon dioxide layer 12, exposing a gate region 47 (FIG. 6) which is contiguous to the source region 36. As will be described, the remaining portion of the silicon dioxide layer 12 will provide an ion implantation mask for forming gate region 47 of the field effect device. The silicon dioxide layer 14 is therefore etched bac~ a length L, here in the order of 0.5 to 2.5~ m, such length, L, being the channel length of the field effect device. It is noted that the length L of the gate region is determined by the amount of chemical etching provided to the silicon dioxide layer 12. This chemical etching process is readily controllable by the etching time duration and chemical etchant stren~th which is itse~f controllable by proper dilution. Further, the etching processes may be monitored using a high powered measuring microscope. The resulting structure, after photoresist layer 40 is removed, is shown in FIG. 6.
Referring now also to FIG. 7, the silicon nitride layer 14 is removed in any conventional manner and a thin silicon dioxide layer 46 is thermally grown over the surface of the structure.
The thin silicon dioxide layer 46 is here in the order of 300 to 1000 A thick and, as will be shown, provides the gate oxide for the device. (It is noted that the silicon dioxide layer 46 is thicker over the surface of the silicon substrate 10 than over the silicon dioxide layer 14.) Following this thermal oxidation, particles, here boron atoms, are ion implanted into the surface of the structure. It is noted that the thicker silicon dioxide layer 12 serves as an ion implantation mask 113857~
so that the boron atoms become implanted only into the portion of the silicon substrate 10 which is disposed beneath the thinner oxide layer 46, the silicon dioxide layer 12 inhibiting boron atoms from becoming implanted in the portions of the silicon substrate 10 disposed beneath the silicon dioxide layer 12. The concentration of boron atoms in the silicon substrate 10 is here in the order of 3 x 1012 atoms/cm2 and hence, after annealing, a p-type conductivity region is formed in the gate region 47 as shown in Figure 7. It is noted that the concentration of n-type dopant in the source and drain regions 36, 38 is in the order of 3 x 1019 atoms/cm3 or higher and hence is not substantially affected by the boron implant which results in a concentration several orders of magnitude less than 3 x 1019 atoms/cm3.
Referring now also to Figure 8, a photoresist layer 50 is deposited over the surface of the structure and patterned into a source/drain contact mask 52, as shown, using con-ventional photolithographic-chemical etching techniques. A
suitable chemical etchant is then brought into contact with the mask 52 and the portions of the silicon dioxide layer 46 exposed by the windows 51, 53 formed in the mask 52 to selec-tively remove such exposed portions of the silicon dioxide layer 46 which are disposed over portions of the source and drain regions 36J 38, respectively, as shown in Figure 9. After the photoresist layer 50 has been removed in any conventional manner a suitable metalization layer 54 is deposited over the surface of the structure, i.e. over the remaining portions of the silicon dioxide layer 46 and, through the windows 51, 53 formed therein, onto the exposed surfaces of the silicon substrate 10 which are disposed over portions of the source and drain regions 36, 38 ~F`
~`~
l~3ssn to form ohmic contact with such regions 36, 38. The metaliza-tion layer 54 is then patterned, in any conventional manner, as by photolithographic-chemical etching processing, into source, drain and gate electrodes S, D and G, respectively, as shown in FIG. 9. It should be noted that although the gate electrode G
overlaps the source region 36 and the drain region 38 as well as the gate region 47 and a drift region 56, the gate electrode G
- is separated from the drift region 56 by a thick insulating layer of silicon dioxide, i.e. layer 12, which is in the order of 1500 A to 3000 A thick.
In the MOS field effect device thus formed, and shown in FIG. 9, the drift region 56 which is disposed beneath the thick silicon dioxide layer 12 connects the gate region 47 to the drain region 38. The drift region 56 is an n-type conductive region formed at the surface of the silicon substrate 10 adjacent the silicon dioxide layer 12 because of fixed positive charge, generally referred to as QSS~ present in the silicon dioxide layer 12, and also as a result of the positive gate voltage which turns the drift region 56 "on" to a greater degree when the short channel is biased "onn. Also, as is Xnown, when the silicon dioxide layer 12 is initially thermally grown over the surface of the silicon substrate 10, as discussed in connection with FIG. 1, and then cooled in an oxygen environ-ment, positive charges are created in the silicon dioxide layer - 1~ to create a strong inversion in the contiguous high resis-tivity p-type conductivity silicon substrate 10 surface to form an n-type conductivity drift region 56.
Alternatively, the drift region 56 may be formed by ion implanting a suitable n-type dopant, as phosphorous atoms, //~/7~ 30 into the surface of the structure either prior to or subsequent to the ion implantation of the boron atoms discussed in connection with FIG. 7. That is, referring to FIG. 10, after the thin silicon dioxide layer 46 is deposited over the surface of the structure phosphorous atoms are ion implanted into the silicon substrate 10 disposed beneath the silicon dioxide layer 12, as shown, to form, after annealing, the drift region 56'. The boron atoms are then ion implanted to form the gate region 47;
however, the depth of such implanted boron atoms is less than the depth of the implanted phosphorous atoms and such implanted boron atoms do not enter the drift region 56'. Further, it should be noted that the implanted phosphorous atoms are dis-posed beneath the source, drain and gate regions 36, 38, 47 because the silicon dioxide layer 46 is thinner over such regions than the thick silicon dloxide layer 12 disposed over the drift region 56'. The phosphorous implant serves to reduce the impedance of the drift region 56' and may also serve to form a buried channel in the drift region 56' to reduce gate electrode capacitance. The structure is then processed as described in connection with FIGS. 8 and 9 to complete the MOS field effect device.
The length of the drift region 56 (or 56') may be adjusted to the desired circuit conditions and may range from about one micrometer to five micrometers. The drift region ~6 (or 56') eliminates the short channel effects (i.e. punch through from drain to source and dependance of the gate threshold voltage on the ~rain voltage) which affect many short channel devices without much additional expenditure in wafer area. ~urther, _ the techniques described above enable the fabrication of ~ hc devices suited for~relatively high voltage levels prevailing in many analog circuits and charge-coupled devices.
~13E}571 Having described preferred embodiments of this invention, it is evident that other embodiments incorporating these /~ concepts may be used. For example, a relatively thin silicon ~;tr;~
layer, 300-500 A thick, may be formed between the metalization layer 54 and the silicon dioxide layer 46. Also, the drift region 56 may be formed by ion implanting phosphorous or arsenic atoms into the silicon substrate 10 prior to the formation of silicon dioxide layer 12 and silicon nitride layer 14. Still further, the source and drain electrodes S, D may be formed in a separate masking step than that used to form the gate electrode G. Also, the gate electrode G may be doped polycrystalline silicon, aluminum or a composite layer of titanium and aluminum. Further, the gate electrode G need not extend to the overlap of the drain region 38, but can terminate at one end over the silicon dioxide layer 12. Still further, while~ n-channel device has been described, a p-channel device may be formed in analogous fashion by using dopants of opposite polarity. Also, the termS source and drain regions may be used interchangeably. It is felt, there-fore, that this invention should not be restricted to thedisclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.
Back round of the Invention This invention relates generally to semiconductor struc-tures and manufacturing methods and more particularly to short channel metal-oxide-semiconductor (MOS) field-effect transistor structures and manufacturing methods.
As is known in the art, high performance MOS field-effect transistors generally require channel lengths below 3~m and even as short as 0.5 to 1.0~m. It is very difficult to obtain these small dimensions with present photolithographic techniques. This difficulty has led to the development of several types o~ transistors having channel lengths defined by means other than photolithography. One such device is generally referred to as a D-MOS transistor where two ~iffusions of dopants of opposite type conductivity are driven to different depths in a silicon substrate through ~/7~
one, noncritical mask opening, resulting in a channel length equal to the difference in the depth of the electrical junctions formed. Here, however, since the doping concentration varies along the channel, the "turn-on" voltage, which is a function of doping, is critically dependent on the location in the channel and the concentration at which the two diffusion profiles intersect. In practice, therefore, the "turn-on", or threshold voltage, will exhibit relatively large fluctuations because of the difficulty to control ~he two diffusions.
Other types of transistors wherein channel width is controlled by means other than photolithography are so-called "V-MOS" transistors and "D-V-MOS" transistors. With a V-MOS
transistor the channel length is generally defined by the up-diffusion of boron from an n-type substrate into a p-type epitaxial layer formed on such substrate, in combination with a ~38571 V-shaped groove etched through the epitaxial layer, down into the substrate. In the D-V-MOS transistor the channel is generally defined by an implant of boron from the top surface, through the n+ layer forming the source and drain, and again the intersection of the implanted zone with the walls of a V-shaped groove.
113~571 Summary of the Invention In accordance with the present invention a masking layer is formed to cover a portion of a surface of a semiconductor; a first doped region is formed in a portion of the semiconductor exposed by the ~asking layer; a chemical etchant is brought into contact with the masking layer, reducing the area of the masking layer covering the semiconductor, exposing a second, different portion of the semiconductor contiguous to the first exposed por-tion of the semiconductor; and particles capable of establishing a doped region in the semiconductor are introduced into the second exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, such chemically etchet masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer.
Thus, this invention provides a method of forming a semiconductor structure comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking such portion of the semiconductor;
(b) forming a region of opposite type conductivity in a portion of the semiconductor layer unmasked by the insulating layer;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer;
(d) ion implanting particles capable of establishing a first type conductivity in the semiconductor into a portion of the semiconductor exposed by the chemically etched insulating layer forming a region of first type conductivity contiguous to both the first formed region of opposite type conductivity and a region of the semiconductor masked by remaining portions of the chemically etched insulating layer; and, (e) forming an electrode over remaining portions of the chemically ~0 etched insulating làyer and over the portion of the semiconductor exposed 1131~1571 by the chemically etched insulating layer and having formed therein the ion implanted region.
In a second aspect, this invention provides a method for forming a semiconductor structure comprising the steps of:
(a) forming an insulator over a portion of a surface of a semi-conductor structure;
(b) forming a first doped region in a portion of the semiconductor structure exposed by the insulator;
(c) bringing a chemical etchant into contact with the insulator removing edge portions thereof ~xposing a second, different portion of the semiconductor structure contiguous to the first doped region;
(d) introducing particles into the second, different portion of the semiconductor structure, the remaining unetched portions of the chemically etched insulator inhibiting such particles from becoming introduced into the portion of the semiconductor structure disposed beneath remaining portions of the insulator; and (e) forming an electrode over remaining portions of the insulator and over the second, different portion of the semiconductor structure exposed by the insulator.
In a preferred embodiment of this invention a second masking layer is formed over the first-mentioned masking layer, such second masking layer ~emaining over the first-mentioned masking layer while a portion of the first-mentioned layer is chemically removed. The second masking layer re-stricts the chemical attack of the etchant to the side of the first-mentioned masking layer.
Further, the structure is formed in a mesa-shape with side walls of such structure being oxidized for device isolation. The first-mentioned masking layer is silicon dioxide and the second masking layer is silicon nitride. During the oxidation process the second masking layer remains over the first-mentioned masking layer, enabling the selective oxidation of the walls of the silicon semiconductor, but preventing oxidation of the first-mentioned masking layer.
- 3a -1~38571 Still further, in a preferred embodiment of this invention the masking layer is used to form source and drain regions of a field effect device. The particles are ion implanted to form a gate region contiguous to one of the source and drain regions.
The channel length of this gate region is accurately controlled by the chemical etching process. The masking layer used to form the source and drain regions is, after being chemically etched, used as an ion implantation mask for forming the qate region. In this way the process is self-aligning since the mask used to form the source and drain regions is, after being etched, used to form the gate region. The masking layer includes a layer of silicon dioxide. A drift channel is formed in the silicon layer disposed beneath the silicon dioxide masking layer to electrically connect the ion implanted gate region to the source and drain regions.
With such techniques the field effect device has a uniformly doped short channel formed by ion implantation.
Furthermore, ~he channel length depends on an accurately controlled chemical etching process. Still further, a relatively thick oxide or insulator layer is formed over the drift region so that when a gate electrode is formed over this oxide layer, any parasitic capacitance between such electrode and the drift region is reduced by this thick oxide layer.
Brief Description of the Drawings The foregoing features of this invention, as well as the invention itself, may be more fully understood from the fol-lowing description read together with the accompanying drawings, in which:
FIGS. 1-9 are cross-section elevation, diagrammatical views of a portion of a field effect device according to the invention at various steps in the manufacture thereof; and FIG. 10 is a cross-sectional eleva~ion, diagrammatical view of a portion of the field effect device according to an alternative embodiment of the invention at an intermediate stage in the manufacture thereof.
Description of the Preferred Embodiments Referring now to FIGS. 1-9, the fabrication of a field effect device will be described. As shown in FIG. 1, a p-type silicon substrate 10, preferably having a surface parallel to the ~100> crystallographic plane and having a doping concen-tration in the range of 5X1014 to 1015 atoms per cm3 is coated with a 1500 to 3000 A thick silicon dioxide layer 12 by conven-tional thermal oxidation or chemical vapor deposition, or a combination of both. Next the silicon dioxide layer 12 is coated with a silicon nitride layer 14, here in the order of 1500 A thick, using conventional chemical vapor deposition. A
photoresist layer 16 is formed over the silicon nitride layer 14 and selectively removed using conventional photo-lithography to form a mask 18, as shown. The photoresis~ mask 18 is used to remove exposed portions of the silicon nitride layer 14 and the then exposed silicon dioxide layer 12 adjacent such mask 18 using any conventional technique. For example, the exposed portions of the silicon nitride layer 14 may be removed using conventional plasma etching and the then exposed portions of the silicon dioxide layer 12 are removed with a suitable chemical etchant, here a hydrofluoric acid solution or also by plasma etching. That is, as will become apparent hereinafter, the composite silicon dioxide layer 12 and silicon nitride layer 14 are etched away from the field or isolation region while they are retained over the mesa shaped Z/~ ~ ~ own in FIG. 2. The remaining portions of the composite silicon dioxide layer 12-silicon nitride layer 14 form an etch resistant mask 20, as shown. The portions of the silicon sub-strate 1~ exposed by such mask 20 are brought into contact by a suitable etchant, either an isotropic or anisotropic etchant, 113857~
to etch such exposed portions of the silicon substrate 10 to a depth in the order of 3000 to 4000 A, as shown. The sur-face of the structure thus formed is exposed to ion implanted particles 22, here boron atoms, with a dosage of 5X1013 atoms per cm2 to 5~1014 atoms/cm2 at an implant energy here in the order of 40 Kev. The structure is then heated in a conventional manner to anneal any implant damage and to activate the im-planted boron atoms forming p-type conductivity regions 24, as shown.
Referring now also to FIG. 3, the structure is then oxidized to form a 6000-8000A thick silicon dioxide layer 26 on the side walls of the mesa-shaped silicon substrate 10 and thereby form a surface in the isolation regions which is substan-tially co-planar with the device surface. (It should be noted that during the oxidation the boron dopant is driven further into the silicon substrate 10.) The boron implant, i.e. p-type conductivity regions 24 (FIG. 2), prevents the formation of an inversion layer on the surface of the high resistivity silicon substrate 10 which would destroy device isolation.
A photoresist layer 28 is deposited over the surface of the structure and then suitably masked and etched, using conventional photolithographic~chemical etching techniques to form a mask 30, as shown in FIG. 3. The portions of the silicon nitride layer 14 and silicon dioxide layer 12 exposed by the photoreslst mask 30 are removed in any conventional manner, similar to that described in connection with FIGS. 1 and 2, to expose portions of the underlying surface of the silicon substrate 10, wherein the source and drain regions 36, 38 of the device will be formed, 1~3~S71 as shown in FIG. 4. The remaining portions of the composite silicon nitride layer 14 and silicon dioxide layer 12 form an ion implantation mask 32 as shown in FIG. 4. Particles, here arsenic atoms, are ion implanted into the portions of the silicon substrate 10 exposed by the ion implantation mask 32.
Here a dosage of 5X1014 atoms/cm2 and an implant energy level of 140 Kev is used. The structure is heated to anneal any implant damage and to activate the implanted arsenic atoms to form n-type conductivity source and drain regions 36, 38 respectively, as shown, in the regions of the silicon sub-strate 10 which are adjacent the region of such substrate 10 covered by the ion implantation mask 32. The depth of the source and drain regions 36, 38 is here in the order of 1000 A.
Referring now also to FIG. 5, a photoresist layer 40 is formed over the surface of the structure, using conventional photolithographic techniques to form an etch resistant mask 42 as shown. It is noted that a window 44 is formed in the photo-resist layer 40 to expose: A portion of the silicon substrate 10 having the source region 36 formed therein; the side portions of the silicon nitride layer 12; the side portions of the silicon dioxide layer 14 adjacent the source region 36; and a portion of the upper surface of the silicon nitride layer 14.
The purpose of the mask 42 is to expose only the edge of the source region 36 while covering the drain region 38. This masking step is then relatively noncritical. A chemical etchant, here a hydrofluoric acid solution, which selectively etches silicon dioxide without attacking either silicon, silicon nitride or photoresist, is brought into contact with the surface of the structure. The chemical etchant passes through the window 44 tG attack the exposed side portions of the silicon dioxide layer 113857~
12 and thereby selectively etch away and remove such exposed portion of the silicon dioxide layer 12. The chemical etchant therefore reduces the area of the silicon substrate 10 dis-posed beneath the chemically etched silicon dioxide layer 12, exposing a gate region 47 (FIG. 6) which is contiguous to the source region 36. As will be described, the remaining portion of the silicon dioxide layer 12 will provide an ion implantation mask for forming gate region 47 of the field effect device. The silicon dioxide layer 14 is therefore etched bac~ a length L, here in the order of 0.5 to 2.5~ m, such length, L, being the channel length of the field effect device. It is noted that the length L of the gate region is determined by the amount of chemical etching provided to the silicon dioxide layer 12. This chemical etching process is readily controllable by the etching time duration and chemical etchant stren~th which is itse~f controllable by proper dilution. Further, the etching processes may be monitored using a high powered measuring microscope. The resulting structure, after photoresist layer 40 is removed, is shown in FIG. 6.
Referring now also to FIG. 7, the silicon nitride layer 14 is removed in any conventional manner and a thin silicon dioxide layer 46 is thermally grown over the surface of the structure.
The thin silicon dioxide layer 46 is here in the order of 300 to 1000 A thick and, as will be shown, provides the gate oxide for the device. (It is noted that the silicon dioxide layer 46 is thicker over the surface of the silicon substrate 10 than over the silicon dioxide layer 14.) Following this thermal oxidation, particles, here boron atoms, are ion implanted into the surface of the structure. It is noted that the thicker silicon dioxide layer 12 serves as an ion implantation mask 113857~
so that the boron atoms become implanted only into the portion of the silicon substrate 10 which is disposed beneath the thinner oxide layer 46, the silicon dioxide layer 12 inhibiting boron atoms from becoming implanted in the portions of the silicon substrate 10 disposed beneath the silicon dioxide layer 12. The concentration of boron atoms in the silicon substrate 10 is here in the order of 3 x 1012 atoms/cm2 and hence, after annealing, a p-type conductivity region is formed in the gate region 47 as shown in Figure 7. It is noted that the concentration of n-type dopant in the source and drain regions 36, 38 is in the order of 3 x 1019 atoms/cm3 or higher and hence is not substantially affected by the boron implant which results in a concentration several orders of magnitude less than 3 x 1019 atoms/cm3.
Referring now also to Figure 8, a photoresist layer 50 is deposited over the surface of the structure and patterned into a source/drain contact mask 52, as shown, using con-ventional photolithographic-chemical etching techniques. A
suitable chemical etchant is then brought into contact with the mask 52 and the portions of the silicon dioxide layer 46 exposed by the windows 51, 53 formed in the mask 52 to selec-tively remove such exposed portions of the silicon dioxide layer 46 which are disposed over portions of the source and drain regions 36J 38, respectively, as shown in Figure 9. After the photoresist layer 50 has been removed in any conventional manner a suitable metalization layer 54 is deposited over the surface of the structure, i.e. over the remaining portions of the silicon dioxide layer 46 and, through the windows 51, 53 formed therein, onto the exposed surfaces of the silicon substrate 10 which are disposed over portions of the source and drain regions 36, 38 ~F`
~`~
l~3ssn to form ohmic contact with such regions 36, 38. The metaliza-tion layer 54 is then patterned, in any conventional manner, as by photolithographic-chemical etching processing, into source, drain and gate electrodes S, D and G, respectively, as shown in FIG. 9. It should be noted that although the gate electrode G
overlaps the source region 36 and the drain region 38 as well as the gate region 47 and a drift region 56, the gate electrode G
- is separated from the drift region 56 by a thick insulating layer of silicon dioxide, i.e. layer 12, which is in the order of 1500 A to 3000 A thick.
In the MOS field effect device thus formed, and shown in FIG. 9, the drift region 56 which is disposed beneath the thick silicon dioxide layer 12 connects the gate region 47 to the drain region 38. The drift region 56 is an n-type conductive region formed at the surface of the silicon substrate 10 adjacent the silicon dioxide layer 12 because of fixed positive charge, generally referred to as QSS~ present in the silicon dioxide layer 12, and also as a result of the positive gate voltage which turns the drift region 56 "on" to a greater degree when the short channel is biased "onn. Also, as is Xnown, when the silicon dioxide layer 12 is initially thermally grown over the surface of the silicon substrate 10, as discussed in connection with FIG. 1, and then cooled in an oxygen environ-ment, positive charges are created in the silicon dioxide layer - 1~ to create a strong inversion in the contiguous high resis-tivity p-type conductivity silicon substrate 10 surface to form an n-type conductivity drift region 56.
Alternatively, the drift region 56 may be formed by ion implanting a suitable n-type dopant, as phosphorous atoms, //~/7~ 30 into the surface of the structure either prior to or subsequent to the ion implantation of the boron atoms discussed in connection with FIG. 7. That is, referring to FIG. 10, after the thin silicon dioxide layer 46 is deposited over the surface of the structure phosphorous atoms are ion implanted into the silicon substrate 10 disposed beneath the silicon dioxide layer 12, as shown, to form, after annealing, the drift region 56'. The boron atoms are then ion implanted to form the gate region 47;
however, the depth of such implanted boron atoms is less than the depth of the implanted phosphorous atoms and such implanted boron atoms do not enter the drift region 56'. Further, it should be noted that the implanted phosphorous atoms are dis-posed beneath the source, drain and gate regions 36, 38, 47 because the silicon dioxide layer 46 is thinner over such regions than the thick silicon dloxide layer 12 disposed over the drift region 56'. The phosphorous implant serves to reduce the impedance of the drift region 56' and may also serve to form a buried channel in the drift region 56' to reduce gate electrode capacitance. The structure is then processed as described in connection with FIGS. 8 and 9 to complete the MOS field effect device.
The length of the drift region 56 (or 56') may be adjusted to the desired circuit conditions and may range from about one micrometer to five micrometers. The drift region ~6 (or 56') eliminates the short channel effects (i.e. punch through from drain to source and dependance of the gate threshold voltage on the ~rain voltage) which affect many short channel devices without much additional expenditure in wafer area. ~urther, _ the techniques described above enable the fabrication of ~ hc devices suited for~relatively high voltage levels prevailing in many analog circuits and charge-coupled devices.
~13E}571 Having described preferred embodiments of this invention, it is evident that other embodiments incorporating these /~ concepts may be used. For example, a relatively thin silicon ~;tr;~
layer, 300-500 A thick, may be formed between the metalization layer 54 and the silicon dioxide layer 46. Also, the drift region 56 may be formed by ion implanting phosphorous or arsenic atoms into the silicon substrate 10 prior to the formation of silicon dioxide layer 12 and silicon nitride layer 14. Still further, the source and drain electrodes S, D may be formed in a separate masking step than that used to form the gate electrode G. Also, the gate electrode G may be doped polycrystalline silicon, aluminum or a composite layer of titanium and aluminum. Further, the gate electrode G need not extend to the overlap of the drain region 38, but can terminate at one end over the silicon dioxide layer 12. Still further, while~ n-channel device has been described, a p-channel device may be formed in analogous fashion by using dopants of opposite polarity. Also, the termS source and drain regions may be used interchangeably. It is felt, there-fore, that this invention should not be restricted to thedisclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of forming a semiconductor structure comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking such portion of the semiconductor;
(b) forming a region of opposite type conductivity in a portion or the semiconductor layer unmasked by the insulating layer;
(c) bringing a chemical enchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer;
(d) ion implanting particles capable of establishing a first type conductivity in the semiconductor into a portion of the semiconductor exposed by the chemically etched insulating layer forming a region of first type conductivity contiguous to both the first formed region of opposite type conductivity and a region of the semi-conductor masked by remaining portions of the chemically etched insulating layer; and, (e) forming an electrode over remaining portions of the chemically etched insulating layer and over the portion of the semiconductor exposed by the chemically etched insulating layer and having formed therein the ion implanted region.
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking such portion of the semiconductor;
(b) forming a region of opposite type conductivity in a portion or the semiconductor layer unmasked by the insulating layer;
(c) bringing a chemical enchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer;
(d) ion implanting particles capable of establishing a first type conductivity in the semiconductor into a portion of the semiconductor exposed by the chemically etched insulating layer forming a region of first type conductivity contiguous to both the first formed region of opposite type conductivity and a region of the semi-conductor masked by remaining portions of the chemically etched insulating layer; and, (e) forming an electrode over remaining portions of the chemically etched insulating layer and over the portion of the semiconductor exposed by the chemically etched insulating layer and having formed therein the ion implanted region.
2. The method recited in claim 1 including the steps of:
forming a masking layer over the insulating layer prior to bringing the chemical etchant into contact with the insulating layer; and selectively etching side portions of the insulating layer, such masking layer inhibiting exposure of the surface of the insulating layer to the chemical etchant.
forming a masking layer over the insulating layer prior to bringing the chemical etchant into contact with the insulating layer; and selectively etching side portions of the insulating layer, such masking layer inhibiting exposure of the surface of the insulating layer to the chemical etchant.
3. The method recited in claim 1 wherein the region of opposite type conductivity is formed by ion implantation.
4. A method of forming a field effect device comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking the underlying portion of such semiconductor and unmasking portions of the semiconductor adjacent to the insulating layer;
(b) introducing particles capable of forming an opposite type conductivity in the semiconductor into the unmasked portions of the semiconductor to form source and drain regions of the device;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area masked by the insulating layer, unmasking a gate region contiguous to the source region, and forming a drift region beneath the remaining portion of the insulating layer;
(d) introducing particles capable of establishing a region of first type conductivity in the semiconductor into the gate region exposed by the chemically etched insulating layer; and (e) forming a gate electrode over the gate region and remaining portions of the insulating layer.
(a) forming an insulating layer over a portion of a surface of a semiconductor having a first type conductivity masking the underlying portion of such semiconductor and unmasking portions of the semiconductor adjacent to the insulating layer;
(b) introducing particles capable of forming an opposite type conductivity in the semiconductor into the unmasked portions of the semiconductor to form source and drain regions of the device;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area masked by the insulating layer, unmasking a gate region contiguous to the source region, and forming a drift region beneath the remaining portion of the insulating layer;
(d) introducing particles capable of establishing a region of first type conductivity in the semiconductor into the gate region exposed by the chemically etched insulating layer; and (e) forming a gate electrode over the gate region and remaining portions of the insulating layer.
5. The method recited in claim 4 including the steps of forming a masking layer over the insulating layer prior to bringing the chemical etchant into contact with the insulating layer; and selectively etching only side portions of the insulating layer, such masking layer inhibiting exposure of the surface of the insulating layer to the chemical etchant.
6. A method of forming a semiconductor structure comprising the steps of:
(a) forming an insulating layer and a masking layer over a portion of a surface of a semiconductor having a first type conductivity, such insulating layer being formed between the surface of the semiconductor and the masking layer, only such insulating layer being capable of being etched by a predetermined chemical etchant;
(b) forming a region of opposite type conductivity in a portion of the semiconductor exposed by the insulating layer and the masking layer;
(c) bringing the predetermined chemical etchant into contact with the insulating layer and the masking layer to reduce the area of the insulating layer masking the semiconductor, unmasking a second different portion of the semiconductor contiguous to the first masked portion of the semi-conductor;
(d) ion implanting particles capable of establishing a region of first type of conductivity in the semiconductor selec-tively into the second different unmasked portion of the semiconductor to form a second region in the semiconductor contiguous to the first formed region, such chemically etched insulating layer inhibiting such particles from becoming implanted into the portion of the semiconductor disposed beneath the chemically etched insulating layer;
and (e) forming an electrode over the second, different unmasked portion of the semiconductor and over the unetched portion of the insulating layer.
(a) forming an insulating layer and a masking layer over a portion of a surface of a semiconductor having a first type conductivity, such insulating layer being formed between the surface of the semiconductor and the masking layer, only such insulating layer being capable of being etched by a predetermined chemical etchant;
(b) forming a region of opposite type conductivity in a portion of the semiconductor exposed by the insulating layer and the masking layer;
(c) bringing the predetermined chemical etchant into contact with the insulating layer and the masking layer to reduce the area of the insulating layer masking the semiconductor, unmasking a second different portion of the semiconductor contiguous to the first masked portion of the semi-conductor;
(d) ion implanting particles capable of establishing a region of first type of conductivity in the semiconductor selec-tively into the second different unmasked portion of the semiconductor to form a second region in the semiconductor contiguous to the first formed region, such chemically etched insulating layer inhibiting such particles from becoming implanted into the portion of the semiconductor disposed beneath the chemically etched insulating layer;
and (e) forming an electrode over the second, different unmasked portion of the semiconductor and over the unetched portion of the insulating layer.
7. The method recited in claim 6 including the step of forming a second, thinner insulating layer over the second formed region and wherein the electrode forming step includes the step of forming the electrode over the second, thinner insulating layer.
8. A method of forming a semiconductor structure comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a semiconductor, masking such portion of the semi-conductor;
(b) forming a first doped region in a portion of the semi-conductor unmasked by the insulating layer;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer and unmasking a second, different portion of the semiconductor contiguous to the unmasked exposed portion of the semiconductor;
(d) introducing particles into the second, different unmasked portion of the semiconductor forming a second doped region in the semiconductor contiguous to the first doped region, the chemically etched insulating layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath such insulating masking layer; and (e) forming an electrode over remaining portions of the etched insulating layer and the unmasked second portion of the semiconductor having the second doped region.
(a) forming an insulating layer over a portion of a surface of a semiconductor, masking such portion of the semi-conductor;
(b) forming a first doped region in a portion of the semi-conductor unmasked by the insulating layer;
(c) bringing a chemical etchant into contact with the insulating layer, reducing the area of the semiconductor masked by the insulating layer and unmasking a second, different portion of the semiconductor contiguous to the unmasked exposed portion of the semiconductor;
(d) introducing particles into the second, different unmasked portion of the semiconductor forming a second doped region in the semiconductor contiguous to the first doped region, the chemically etched insulating layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath such insulating masking layer; and (e) forming an electrode over remaining portions of the etched insulating layer and the unmasked second portion of the semiconductor having the second doped region.
9. A method for forming a semiconductor structure comprising the steps of:
(a) forming an insulator over a portion of a surface of a semiconductor structure;
(b) forming a first doped region in a portion of the semi-conductor structure exposed by the insulator;
(c) bringing a chemical etchant into contact with the insulator removing edge portions thereof exposing a second, different portion of the semiconductor structure contiguous to the first doped region;
(d) introducing particles into the second, different portion of the semiconductor structure, the remaining unetched portions of the chemically etched insulator inhibiting such particles from becoming introduced into the portion of the semiconductor structure disposed beneath remaining portions of the insulator; and (e) forming an electrode over remaining portions of the insulator and over the second, different portion of the semiconductor structure exposed by the insulator.
(a) forming an insulator over a portion of a surface of a semiconductor structure;
(b) forming a first doped region in a portion of the semi-conductor structure exposed by the insulator;
(c) bringing a chemical etchant into contact with the insulator removing edge portions thereof exposing a second, different portion of the semiconductor structure contiguous to the first doped region;
(d) introducing particles into the second, different portion of the semiconductor structure, the remaining unetched portions of the chemically etched insulator inhibiting such particles from becoming introduced into the portion of the semiconductor structure disposed beneath remaining portions of the insulator; and (e) forming an electrode over remaining portions of the insulator and over the second, different portion of the semiconductor structure exposed by the insulator.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US96990678A | 1978-12-15 | 1978-12-15 | |
| US969,906 | 1978-12-15 |
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|---|---|
| CA1138571A true CA1138571A (en) | 1982-12-28 |
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| CA000339782A Expired CA1138571A (en) | 1978-12-15 | 1979-11-14 | Semiconductor structures and manufacturing methods |
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| CA (1) | CA1138571A (en) |
| DE (1) | DE2950413A1 (en) |
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| IT (1) | IT1120149B (en) |
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| DE3040775C2 (en) * | 1980-10-29 | 1987-01-15 | Siemens AG, 1000 Berlin und 8000 München | Controllable MIS semiconductor device |
| US4442589A (en) * | 1981-03-05 | 1984-04-17 | International Business Machines Corporation | Method for manufacturing field effect transistors |
| DE3322669C2 (en) * | 1982-07-08 | 1986-04-24 | General Electric Co., Schenectady, N.Y. | A method of manufacturing a semiconductor device having insulated gate electrodes |
| JPH0427799Y2 (en) * | 1986-08-28 | 1992-07-03 | ||
| US5151374A (en) * | 1991-07-24 | 1992-09-29 | Industrial Technology Research Institute | Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode |
| US5604139A (en) * | 1994-02-10 | 1997-02-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| JP2007085210A (en) * | 2005-09-21 | 2007-04-05 | Hitachi Ltd | Water turbine or pump turbine |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636585B2 (en) * | 1973-07-02 | 1981-08-25 | ||
| US4001048A (en) * | 1974-06-26 | 1977-01-04 | Signetics Corporation | Method of making metal oxide semiconductor structures using ion implantation |
| US4058822A (en) * | 1975-05-30 | 1977-11-15 | Sharp Kabushiki Kaisha | High voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device and manufacture thereof |
| JPS5284981A (en) * | 1976-01-06 | 1977-07-14 | Mitsubishi Electric Corp | Production of insulated gate type semiconductor device |
| US4062699A (en) * | 1976-02-20 | 1977-12-13 | Western Digital Corporation | Method for fabricating diffusion self-aligned short channel MOS device |
| JPS605075B2 (en) * | 1976-12-29 | 1985-02-08 | 松下電器産業株式会社 | MOS type semiconductor device and its manufacturing method |
| DE2703877C2 (en) * | 1977-01-31 | 1982-06-03 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Short channel MIS transistor and process for its manufacture |
| JPS53135581A (en) * | 1977-05-02 | 1978-11-27 | Hitachi Ltd | Manufacture for mos semiconductor device |
| US4173818A (en) * | 1978-05-30 | 1979-11-13 | International Business Machines Corporation | Method for fabricating transistor structures having very short effective channels |
-
1979
- 1979-11-14 CA CA000339782A patent/CA1138571A/en not_active Expired
- 1979-12-05 GB GB7941941A patent/GB2038088B/en not_active Expired
- 1979-12-06 IT IT51008/79A patent/IT1120149B/en active
- 1979-12-14 JP JP16263079A patent/JPS5583270A/en active Granted
- 1979-12-14 DE DE19792950413 patent/DE2950413A1/en active Granted
- 1979-12-17 FR FR7930817A patent/FR2445618A1/en active Granted
-
1980
- 1980-04-21 FR FR8008887A patent/FR2453501A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| GB2038088B (en) | 1983-05-25 |
| FR2453501A1 (en) | 1980-10-31 |
| GB2038088A (en) | 1980-07-16 |
| DE2950413C2 (en) | 1989-12-28 |
| FR2445618A1 (en) | 1980-07-25 |
| FR2453501B1 (en) | 1984-09-07 |
| JPS5583270A (en) | 1980-06-23 |
| IT1120149B (en) | 1986-03-19 |
| IT7951008A0 (en) | 1979-12-06 |
| FR2445618B1 (en) | 1985-03-01 |
| DE2950413A1 (en) | 1980-06-26 |
| JPS6326553B2 (en) | 1988-05-30 |
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