JPS6326553B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to semiconductor devices and manufacturing methods, and more particularly to short channel MOSFET devices and manufacturing methods.

As is well known, high performance MOSFETs are generally 3μm.
Shorter channel lengths are required, in some cases as short as 0.5 to 1.0 μm. It is very difficult to obtain such small dimensions with current photolithography techniques. This difficulty has prompted the development of several types of transistors with channel lengths determined by methods other than photolithography. One such device is commonly referred to as a D-MOS transistor, in which two diffusions with dopants of opposite conductivity type are made through one imprecise mask opening to different depths in the silicon substrate, thereby A channel length equal to the electrical junction depth difference is created. However, since the doping concentration varies along the channel, the turn-on voltage, which is a function of the doping, is strictly determined by the location within the channel and the concentration at the intersection of the two diffusion regions. In practice, therefore, this turn-on voltage or threshold voltage will vary relatively widely due to the difficulty in controlling these two diffusions.

Other types of transistors whose channel widths have become controlled by means other than photolithography are the so-called V-MOS transistors and D-V-MOS transistors.
It is a MOS transistor. In a V-MOS transistor, the channel length is generally determined by the upward diffusion of boron from an n-type substrate into a p-type epitaxial layer formed thereon and the diffusion of boron into a v-type etched downwardly into this substrate through said epitaxial layer. Limited by combination with groove. D-V-MOS
In transistors, the channel is generally defined by boron implantation from the top through the n ⁺ layer forming the source and drain and the intersection of the implanted region with the walls of the V-groove.

According to the invention, a mask layer is formed to cover a portion of the surface of the semiconductor, and a first doped region is formed in the portion of the semiconductor that is not covered by the mask. A chemical etchant is applied to the mask layer to reduce its area and communicate with the exposed first portion of the semiconductor to expose a second portion.
Particles capable of creating a doped region within the semiconductor are introduced into this second exposed portion to communicate with the first doped region and form a second doped region. This chemically etched mask layer prevents such particles from entering the underlying semiconductor portion.

In one embodiment of the invention, a second masking layer is formed over the first masking layer. A second like this
The mask layer remains on the first mask layer while a portion of the first mask layer is chemically removed. The second mask layer limits the chemical action of the etchant on the side of the first mask layer.

Additionally, the structure is formed as a mesa with sidewalls that are oxidized for device isolation. 1st
The mask layer is silicon dioxide and the second mask layer is silicon nitride. During oxidation, the second mask layer remains on the first mask layer to allow selective oxidation of the walls of the silicon semiconductor and to prevent oxidation of the first mask layer.

Additionally, one embodiment of the present invention uses a mask layer to form source and drain regions of a field effect device. Particles are implanted to communicate with one of the source and drain regions to form a gate region. The mask layer used to form the source and drain regions is used as an ion implant mask for the formation of the gate region after chemical etching. The process is thus self-aligned since the masks used to create the source and drain regions are used after etching to create the gate regions. This mask layer has a layer of silicon dioxide. A drift channel is formed in the silicon layer below the silicon dioxide mask layer to electrically connect the implanted gate region to the source and drain regions.

By using such techniques, field effect devices have short, uniformly doped channels formed by ion implantation. Furthermore, the length of the channel is determined by a precisely defined chemical etching process. Additionally, a relatively thick oxide or insulator layer is formed over the drift region. The thick oxide layer is designed to reduce the parasitic capacitance between the gate electrode and the drift region when the gate electrode is formed on the oxide layer.

Next, a method for manufacturing a field effect device will be described with reference to FIGS. 1 to 9. As shown in FIG. 1, a P-type silicon substrate 10 having a surface preferably parallel to the <100> plane and having a doping concentration in the range of 5×10 ¹⁴ to 10 ¹⁵ atoms/cm ³ is conventionally used. 1500 by thermal oxidation or chemical vapor deposition or a combination of these
It is coated with a silicon dioxide layer 12 with a thickness of Å to 3000 Å. Next, silicon dioxide layer 12
is coated with a silicon nitride layer 14, here approximately 1500 Å thick, by conventional chemical vapor deposition.
A photoresist layer 16 is formed on silicon nitride layer 14 and selectively removed as shown to form mask 18 using conventional photolithography techniques. Photoresist mask 18 is silicon nitride layer 1
4 and then adjacent the mask 18 is used to remove the exposed silicon dioxide layer 12 using conventional techniques. For example, the exposed portions of layer 14 may be removed using a conventional plasma etch, and then the exposed portions of layer 12 may be removed using a suitable chemical etchant, here a hydrofluoric acid solution, or using a plasma etch. That is, the composite silicon dioxide layer 12 and silicon nitride layer 14 are etched away from the electric field or isolation region while overlying the mesa region shown in FIG. The remaining portions of layers 12-14 form etch-resistant mask 20 as shown. The portion of silicon substrate 10 exposed by mask 20 is exposed to a suitable anisotropic or isotropic etchant and etched to a depth of approximately 3000-4000 Å as shown. The surface of the structure formed in this way is now exposed to a dose of 5 with an implant energy of around 40 KeV.
Particles 22, which are boron atoms in this case, are ion-implanted at a concentration of approximately ×10 ¹³ to 5 × 10 ¹⁴ atoms/cm ³ . It is then conventionally heated to eliminate implant damage and to activate the implanted boron atoms forming P-type region 24 as shown.

As shown in Figure 3, this structure is then oxidized to form a 6000-8000 Å thick silicon dioxide layer 26 on the sidewalls of the mesa silicon substrate 10, so that it is substantially coplanar with the surface of the device. (during this oxidation, the boron dopant also enters the silicon substrate 10). The boron implant or P-type region 24 (FIG. 2) prevents the formation of an inversion layer on the surface of the high resistance silicon substrate 10 that would destroy device isolation.

A layer of photoresist 28 is provided over the surface of the structure and then suitably masked and etched using conventional photolithography-chemical etching techniques to form mask 30 as shown in FIG. Layers 14 and 12 exposed from mask 30
1 and 2 is conventionally removed to expose the surface portion of silicon substrate 10. In this portion, source and drain regions 36 and 38 of the device are formed as shown in FIG. The remainder of the combination of layers 12 and 14 forms an ion implant mask 32 as shown in FIG. Here, the particles that are arsenic atoms are mask 3.
Ions are implanted into the portion of the substrate 10 that is exposed from 2. Here a dose of 5×10 ¹⁴ atoms/cm ² and
An implant energy level of 140 KeV is used.
The structure is heated to eliminate implant damage and activate the implanted arsenic atoms to form n-type source and drain regions, respectively, as shown in regions of substrate 10 covered by mask 32. become The source and drain region injections are here
It is about 1000 Å.

In FIG. 5, a layer of photoresist 40 is formed over the surface of this fabrication by conventional photolithography techniques to form an etch-resistant mask 42 as shown. A window 44 is formed in the photoresist layer 40 to include a portion of the silicon substrate 10 having the source region 36 , a side portion of the silicon nitride layer 12 , a side portion of the silicon dioxide layer 12 adjacent the source region 36 , and a portion of the top surface of the silicon nitride layer 14 . and expose. The purpose of mask 42 is to cover drain region 38 but expose only the edges of source region 36. We want this mask step to be relatively accurate in this case. A chemical etchant, here hydrofluoric acid, which selectively etches silicon dioxide without acting on silicon, silicon nitride, or photoresist, is then applied to the surface of this structure.
The etchant passes through window 44 and acts on the exposed side portions of silicon dioxide layer 12 to selectively remove that portion. This etchant therefore reduces the area of silicon substrate 10 beneath chemically etched silicon dioxide layer 12 to expose gate region 47 (FIG. 6) which is connected to source region 36. Silicon dioxide layer 12 as described below
The remaining portion forms an ion implantation mask for forming gate region 47 of the field effect device. Therefore, the silicon dioxide layer 14 is here 0.5
Only a length L, which is on the order of ~2.5 μm, is left. This length L is the channel length of the field effect device. The length L of the gate region is the silicon dioxide layer 12
Depends on the amount of etchant given. This etching process is easily controlled by the etching time and the strength of the etchant, which itself can be controlled by proper dilution. Furthermore, these etching processes can also be monitored using a high-magnification measuring microscope. After removing photoresist layer 40, the resulting structure is shown in FIG.

Referring to FIG. 7, silicon nitride layer 14 is removed by any method and thin silicon dioxide layer 46 is removed.
is thermally grown on the surface of this structure. This thin silicon dioxide layer 46 is here between 300 and 1000 Å.
The gate oxide for this device is made as shown (the silicon dioxide layer 46 is thick at the surface of the silicon substrate 10, and the silicon dioxide layer 1
4). Following this thermal oxidation, particles, here boron atoms, are implanted into the surface of the structure. In this case, the thick silicon dioxide layer 12 acts as an ion implant mask so that the boron atoms are implanted only into the portions of the silicon substrate 10 below the thin oxide layer 46, and the silicon dioxide layer 12 Prevent boron from being injected into the part. The concentration of boron atoms in the silicon substrate 10 is here of the order of 3×10 ¹² atoms/cm ² , so that after annealing P
A shaped region is formed in gate region 47 as shown in FIG. The concentration of n-type dopants in the source and drain regions is on the order of 3×10 ¹⁹ atoms/cm ³ or more, and therefore the effect of boron implantation is such that it results in a concentration several orders of magnitude lower than 3×10 ¹⁹ atoms/cm ^{3 .} practically not received.

In FIG. 8, a photoresist layer 50 is applied over the surface of the structure and patterned using conventional photolithography-chemical etching techniques in the form of a source/drain contact mask 52 as shown. Appropriate chemical etchants are mask 52 and mask 5.
9. Exposure of the silicon dioxide layer 46 overlying portions of the source and drain regions 36, 38, respectively, as shown in FIG. Selectively remove parts. After removing the photoresist layer 50 in a conventional manner, a suitable metal layer 54 is deposited over the surface of the structure, ie over the remaining portions of the silicon dioxide layer 46 and over portions of the source and drain regions 36, 38 through the windows 51, 53. Such a region 3 is provided on the exposed surface of the silicon substrate 10 of
Make ohmic contact with 6 and 38. metal layer 5
4, as in the conventional manner, patterns are then formed to form source, drain and gate electrodes SDG as shown in FIG. Gate electrode G is source region 3
6, drain region and gate region 47, but gate electrode G is separated from drift region 56 by a thick insulating layer or layer 12 of silicon dioxide on the order of 1500 Å to 3000 Å.

In the MOS field effect device of FIG. 9 thus formed, the drift region 56 under the thick silicon dioxide layer 12 connects the gate region 47 to the drain region 38. Drift region 56 is formed in silicon dioxide layer 12 as a result of a fixed positive charge, commonly referred to as Q _SS , in silicon dioxide layer 12 and a positive voltage that turns drift region 56 on to a significant extent when the short channel is biased on. An n-type region formed on the surface of silicon substrate 10 adjacent layer 12. It is also well known that when silicon dioxide layer 12 is first thermally grown on the surface of silicon substrate 10 as described in FIG. This generates a strong inversion on the surface of the continuous high-resistance P-type silicon substrate 10, creating an n-type drift region 56.

Drift region 56 may also be formed by implanting a suitable n-type dopant, such as phosphorous atoms, into the surface of the structure before or after implanting boron atoms as described in FIG. That is, the first
In Figure 0, after a thin silicon dioxide layer 46 is provided on the surface of the structure, phosphorus atoms are implanted into the surface of the silicon substrate 10 below layer 12 as shown to create a drift region 56' after annealing. Boron atoms will then be implanted to create gate region 47. However, the depth of such implanted boron atoms is less than that of the implanted phosphorus atoms, so such boron atoms do not enter the drift region 56'.
Furthermore, the implanted phosphorous atoms are more likely to cause the silicon dioxide layer 46 to be exposed to the source, drain and gate regions 36, 3 than to the layer 12 above the drift region 56'.
8, 47, so those areas 3
6, 38, and 47. The phosphorous implant acts to reduce the impedance of the drift region 56' and to form a buried channel within the drift region 56' to reduce the capacitance of the gate electrode. This structure is then extended to the eighth
9 to complete the MOS field effect device.

The length of drift region 56 (or 56') can be adjusted to desired circuit conditions and ranges from approximately 1 μm to 5 μm. Drift area 56
(or 56') eliminates short-channel effects (i.e., drain-to-source punchthrough and dependence of gate threshold voltage on drain voltage) that affect many short-channel devices without significantly increasing wafer area. Furthermore, the techniques described above enable the fabrication of devices suitable for the relatively high voltage levels common to many analog circuits and charge-coupled devices.

Although preferred embodiments of the invention have been described, it will be obvious that other embodiments incorporating these concepts may be used. For example, a relatively thin layer of silicon nitride, on the order of 300-500 Å, can be formed between metal layer 54 and silicon dioxide layer 46. Also,
Drift region 56 may be formed by ion-implanting phosphorus or arsenic atoms into silicon substrate 10 before forming silicon dioxide layer 12 and silicon nitride layer 14 . Furthermore, the source and drain regions SD may be formed using a mask other than the mask used to form the gate electrode G. The gate region G may also be a layer of doped polycrystalline silicon, aluminum, or a composition of titanium and aluminum.
Further, the gate electrode G does not need to extend to overlap the drain region 38, but may extend to one end on the silicon dioxide layer 12. Furthermore, although n-channel devices have been described, p-channel devices can be similarly made using dopants of opposite polarity.
Also, the source and drain regions may be reversed.

Next, some embodiments of the present invention will be listed.

(1) A method for manufacturing a field effect device consisting of the following steps.

(a) forming an insulating layer covering a portion of the surface of a semiconductor of a first conductivity type to mask the underlying portion of the semiconductor and exposing a portion of the semiconductor adjacent to the insulating layer;

(b) implanting particles capable of creating opposite conductivity types in the semiconductor into exposed portions of the semiconductor to form source and drain regions of the device;

(c) applying a chemical etchant to the insulating layer to reduce the area of the insulating layer covering the semiconductor and separating the source region and the drift region under the chemically etched insulating layer; The gate region is connected to the source region and the drift region to expose the gate region.

(d) implanting particles capable of creating a region of a first conductivity type in the semiconductor into the gate region exposed by the chemically etched insulating layer;

(2) forming a second insulating layer on the first insulating layer before applying the etchant to the first insulating layer; and selectively etching only the sides of the first insulating layer; The method for manufacturing a field effect device according to aspect (1), further comprising: the second insulating layer preventing the surface of the first insulating layer from being exposed to the etchant.

(3) A method for manufacturing a semiconductor structure comprising the following steps:

(b) An insulating layer and a mask layer covering a portion of the surface of the semiconductor of the first conductivity type are formed such that the insulating layer is between the surface and the mask layer, and only the insulating layer is Etchable by chemical etchant.

(b) forming a region of opposite conductivity type in a portion of the semiconductor exposed by the insulating layer and the mask layer;

(c) applying the etchant to the insulating layer and the mask layer to reduce the area of the insulating layer covering the semiconductor to expose a second portion of the semiconductor that is continuous with the exposed upper portion of the semiconductor; .

(d) particles capable of selectively creating regions of the first conductivity type in the semiconductor;
By implanting ions into the exposed portion of the first
A second region is formed in the semiconductor, continuous with the region, and the chemically etched insulating layer prevents implantation of the particles into portions of the semiconductor below.

8. The method of claim 7, further comprising the step of: (4) forming a second thin insulating layer on the first and second regions.

(5) A method for manufacturing a semiconductor structure if it includes the following steps:

(a) Form a mask layer that covers part of the surface of the semiconductor.

(b) forming a first doping region in a portion of the semiconductor not covered by the mask layer;

(c) applying a chemical etchant to the mask layer to reduce the area of the mask layer covering the semiconductor and exposing a second portion of the semiconductor that is continuous with the first exposed portion of the semiconductor;

(d) introducing particles into the second exposed portion of the semiconductor to form a second doped region of the semiconductor continuous with the first doped region; The layer prevents the introduction of the particles into the parts of the semiconductor underneath.

(6)(a) A semiconductor having a source region, a gate region continuous to the source region, a drift region continuous to the gate region, and a drain region electrically connected to the source region through the gate and the drift region. (b) a first insulating layer disposed over the gate region; (c) a second thick insulating layer disposed over the entire drift region; and (d) a source connected to the source and drain regions. and a drain electrode, and a gate electrode disposed on at least a portion of the first insulating layer and the second insulating layer.

(7) The semiconductor device according to claim 6, wherein the particles forming the drift region are present in the drift region portion closer to the surface of the semiconductor than in other portions of the semiconductor.

[Brief explanation of the drawing]

1, 2, 3, 4, 5, 6, 7, 8 and 9 illustrate various fabrications of parts of field effect devices according to the invention. FIG. 10 is a sectional view showing an intermediate stage in another embodiment of the present invention. 10... Silicon substrate, 12, 26, 46...
Silicon dioxide layer, 14...Silicon nitride layer, 1
6, 28, 40, 50...photoresist layer, 1
8, 30...Mask, 20...Photoresist mask, 22...Ion particles, 24...P-type region, 3
6... Source region, 38... Drain region, 32...
...Ion implantation mask, 42...Etching resistant mask, 44, 51, 53...Window, 47...Gate region, 52...Source/drain contact mask, 54...
...metal layer, 56...drift region.

Claims (1)

[Claims] 1 (a) An insulating layer and a mask layer covering the surface of the insulating layer are formed, and the insulating layer and the mask layer cover a part of the surface of the semiconductor of the first conductivity type and mask that part. (b) forming a region of opposite conductivity type in a portion of the semiconductor layer not masked by the insulating layer and the masking layer; (c) contacting the insulating layer and the masking layer with a chemical etching agent; selectively etching only the side portions of the insulating layer, the mask layer prohibits the surface of the insulating layer from being exposed to the chemical etching agent, and reduces the semiconductor area masked by the insulating layer; (d) A first layer is formed within the semiconductor in a portion of the semiconductor exposed by the chemically etched insulating layer.
ion implantation of particles capable of creating a conductive type of conductivity into both the regions of the opposite conductivity type and the regions of the semiconductor masked by the remainder of the chemically etched insulating layer. (e) ion implantation of the remaining portion of the chemically etched insulating layer and the semiconductor portion exposed by the chemically etching insulating layer; A method of forming a semiconductor structure consisting of steps that form an electrode over a region. 2. The method of claim 1, wherein the regions of opposite conductivity type are formed by ion implantation.