JP2519541B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a MOS (M) formed on a semiconductor layer on an insulator substrate.
et al Oxide Semiconductor) field effect transistor (hereinafter abbreviated as “SOI-MOSFET”),
The present invention relates to improvement of breakdown voltage between source and drain.

[Conventional technology]

FIG. 8 is a sectional view showing a conventional SOI-MOSFET. An insulator layer (2) is formed on a silicon substrate (1), and a silicon layer (3) is formed on the insulator layer (2). In the silicon layer (3), a channel region (6) having a low p-type impurity concentration (for example, 10 ¹⁶ to 10 ¹⁷ atoms / cm ³ ) is formed, and a high n-type impurity concentration (for example, 10 ¹⁹ to 10 ^19). A source region (7) having ²¹ atoms / cm ³ ) and a drain region (8) are formed in contact with one side and the other side of the channel region (6), respectively.

A gate dielectric thin film (hereinafter referred to as a gate insulating film) (4) is formed on the channel region (6), and a gate electrode (5) is formed on the gate insulating film (4). The silicon layer (3) and the gate electrode (5) are covered with an interlayer insulating film (9). Contact holes (10a) and (10b) are formed in the interlayer insulating film (9), and conductors corresponding to the contact holes (10a) and (10b), in this case, the source electrode (11) and the drain electrode ( 12)
Are formed.

In the SOI-MOSFET configured as described above, when a positive voltage is applied to the gate electrode (5), an n-conductivity type carrier (electron) is formed in the upper layer portion of the p-type channel region (6).
Are induced and their upper layers are inverted to the same n conductivity type as the source region (7) and the drain region (8). Therefore, a current can flow between the source region (7) and the drain region (8). In addition, since the concentration of n-type carriers attracted to the upper layer portion of the channel region (6) changes depending on the gate voltage, the channel region (6)
The amount of current flowing through can be controlled by the gate voltage. This is the operating principle of the MOSFET.

[Problems to be Solved by the Invention]

The conventional SOI-MOSFET is configured as above,
If the silicon layer (3) is relatively thick (eg, about 500Å thick), it extends from the drain region (8) into the channel region (6) when the SOI-MOSFET is activated by applying a gate voltage. The depletion layer may reach the source region (7). If the depletion layer reaches the source region (7),
The electrical barrier between the source region (7) and the channel region (6) is lowered, and the potential of the relatively deep region that cannot be controlled by the gate electrode (5) is raised, which causes the channel current to increase rapidly. A phenomenon called "punch-through phenomenon" occurs. This punch-through phenomenon lowers the breakdown voltage between the source and drain.

Further, when the voltage applied between the source and the drain is high, the carrier is accelerated in the channel region (6) at high speed. The carriers accelerated in the channel region (6) generate bears of electrons and holes by impact ionization in the vicinity of the drain region (8). The generated electrons flow into the n ⁺ type drain region (8). However, the holes are accumulated in the channel region (6) to raise the potential, so that the channel current is increased and an undesired kink effect is caused in the electrical characteristics representing the relationship between the drain voltage and the drain current. This kink effect is, for example, IEEE Electr
on Device Letter. Vol. 9, No. 2, pp. 97-99, 1988.

On the other hand, a thin film SOI-MOSFET having a very thin (eg, 500 Å to 1500 Å thickness) silicon layer (3) has superior characteristics to a normal SOI-MOSFET having a thick silicon layer (3). ing. For example, the thin channel region (6) is entirely depleted by applying a voltage to the gate electrode (5), and the potential is also controlled by the gate electrode (5). And the kink effect disappears. Further, the short channel effect, which causes the gate threshold voltage to be abnormally low when the gate length is short, is also reduced.

However, when the entire channel region (6) is fully depleted, the potential in the channel region (6) will be higher than in a normal MOSFET. Therefore, the electrical barrier between the source region (7) and the channel region (6) is lowered, and holes generated by the impact ionization described above are temporarily accumulated in the channel region (6). Then, the potential in the channel region (6) further rises, and electrons are rapidly injected from the source region (7) into the channel region (6). That is, thin film SOI-MOSFET
Also, there is a problem that the breakdown voltage between the source and the drain tends to be low.

In view of the problems as described above, an object of the present invention is to provide an SOI-MOSFET having an improved withstand voltage between the source and drain.

[Means for solving the problem]

According to another aspect of the present invention, there is provided a semiconductor device including an insulating base, a semiconductor layer formed on the insulating base, and a gate electrode having both ends formed on the semiconductor base via a gate dielectric thin film. A lower layer source region and a lower layer drain region formed to a predetermined depth from the semiconductor layer surface at a position sandwiching the gate electrode from both end sides, and at least a lower layer source region and a lower layer drain region of the semiconductor layer surface. On the surface of the semiconductor layer of the lower source region and the lower drain region and the channel region formed in the sandwiched region, the gate electrode is formed via the insulating film, the upper layer made of the impurity-doped epitaxial layer A source region and an upper drain region.

A semiconductor device according to a second aspect of the present invention further comprises a source electrode in addition to the structure of the first aspect, and the channel region has a region below the gate electrode in the semiconductor layer and a lower layer source. The source electrode and the region below the lower drain region, and the source electrode is formed in the contact hole opened to the upper source region, the lower source region, and the channel region thereunder, so that the upper source is formed. Connected to the region, the underlying source region and the channel region.

[Operation] According to the configuration of the present invention described in claim 1, since the upper layer source region and the upper layer drain region are provided on the semiconductor layer, the thicknesses of the lower layer source region and the lower layer drain region in the semiconductor layer are relatively small. Even if it is formed thinly, the thickness of the source / drain region including the upper layer and the lower layer can be secured to such an extent that a sufficiently low electric resistance required for the characteristics of the MOS transistor can be obtained. Also, for example, when the sidewall insulating films are formed on both ends of the gate electrode by anisotropic etching, even if the semiconductor layer is over-etched and the lower source region and the lower drain region are thinned, the upper source region is thinned. Also, the presence of the upper drain region makes it possible to secure the thickness of the source / drain region including the upper layer and the lower layer to such an extent that a sufficiently low electric resistance required for the characteristics of the MOS transistor can be obtained.

According to the semiconductor device of the present invention as set forth in claim 2, further comprising a source electrode connected to the upper layer source region, the lower layer source region and the channel region, so that the source electrode is also connected to the channel region and the substrate electrode is formed. Since it also serves as a surplus, excess carriers generated by impact ionization in the semiconductor layer are easily extracted by the source electrode.

Further, as a result of having the upper layer source region and the upper layer drain region on the semiconductor layer, the thickness of the lower layer source region and the lower layer drain region in the semiconductor layer can be made relatively thin, and as a result, the thickness of the semiconductor layer is constant. In this case, since the thickness of the channel region below the lower source region and the lower drain region can be made relatively large, the cross-sectional area of the channel region becomes large, and as a result, the resistance to carrier flow in the channel region is reduced. can do.

Example of Invention

Hereinafter, a structure and a manufacturing method of a semiconductor device related to the present invention and an embodiment of the present invention will be described with reference to the drawings. In addition, the description overlapping with the description of the conventional technique will be appropriately omitted. FIG. 1 shows SOI-M related to the present invention.
It is sectional drawing which shows one structure of OSFET. In the figure,
(1), (2), (4), (5) and (9) are the same as the conventional ones. Reference numeral (20) denotes a first silicon layer on the insulator layer (2), which has a high n-type impurity concentration formed on both sides of the gate electrode (5) on the upper side of the first silicon layer (20). The first source region (23) and the first drain region (24) are provided, and the first source region (23) and the first drain region (24) are formed on the outer sides of the lower portions thereof, respectively. a second channel region (22) (22) having a p-type impurity concentration, and a first source region (23), a first drain region (24) and a second channel region (22) (22). A first channel region (21) formed in the inner central portion and having a low p-type impurity concentration
It is made up of (25) is a first contact hole opened over a part of the main surface of the insulator (2) so as to expose a part of the interlayer insulating film (9) on the source region (23) side,
(26) is the first drain region (2
4) A second hole opened to expose a part of the main surface
Contact hole. (27) is one conductor which is connected to the first source region (23) and the second channel region (22) through the first contact hole and is also connected to the insulator layer (2). The source electrode, in this case the first
It has the performance of both the source electrode (27) and the substrate electrode. Reference numeral (28) is a drain electrode which is the other conductor and is connected to the first drain region (24) through the second contact hole (26).

The SOI-MOSFET having such a structure is formed as follows. This will be described with reference to FIG.

First, the insulator layer (2) is formed on the main surface of the silicon substrate (1).
Is formed to a predetermined thickness, and then a layer (32) which will be the first silicon layer is formed thereon. After that, p-type impurities, in this case, boron are ion-implanted (31) into the layer (32) to be the first silicon layer. As a result, a region to be the first channel region is formed. This area is, for example, 10 ⁶
It is formed at an impurity concentration of ˜10 ¹⁷ atoms / cm ³ (FIG. 2 (a)).

Next, a silicon oxide film (33) is formed on the entire surface of the layer (32) which will be the first silicon layer, and then a resist (34) is formed thereon. The resist (34) is patterned by the photolithography technique, and then the silicon oxide film (33) is etched by using this as a mask to selectively remove it. After this, p is added to the layer (32) to be the first silicon layer.
Type impurities, in this case boron ion implantation (35) and p
A type impurity region (36) is formed (FIG. 2 (b)).

Next, after removing the resist (34) by an assembling method or the like, the silicon substrate (1) is heat-treated at a predetermined temperature. As a result, the impurities in the p-type impurity region (36) are activated, and the boundary surface enters inside the end surface of the silicon oxide film (33) to form a diffusion layer. This diffusion layer serves as the second channel region (22), and is formed with an impurity concentration of, for example, 10 ¹⁹ to 10 ²⁰ atoms / cm ³ (FIG. 2 (c)).

Next, using the silicon oxide film (33) as a mask, the layer (32) to be the first silicon layer is selectively removed by reactive ion etching (hereinafter referred to as RIE) having anisotropic characteristics ( FIG. 2 (d)).

Next, after the silicon oxide film (33) serving as a mask is removed by etching, a silicon oxide film is formed on the entire surface so as to cover the layer (32) to be the first silicon layer, and further on the entire surface, For example, a polycrystalline silicon film is formed. After that, the polycrystalline silicon film is patterned by the photolithography technique, and then the underlying silicon oxide film is selectively etched away by RIE or the like using this as a mask. As a result, the gate insulating film (4) and the gate electrode (5) are formed on the inner center of the layer (32) to be the first silicon layer (FIG. 2 (e)).

Next, an n-type impurity, in this case, arsenic (in this case) is ion-implanted (37) from above the silicon substrate (1) and then activated to form an n-type diffusion layer. This diffusion layer serves as the first source region (23) and the first drain region (24), and has an impurity concentration of, for example, 10 ¹⁹ to 10 ²¹ atoms / cm ³ . Here, by forming the first source region (23) and the first drain region (24), the first channel region (21) and the second channel region (22) are formed.
Each area of (22) is defined, and the first silicon layer (20) is formed (FIG. 2 (f)).

Next, an interlayer insulating film (9) having a predetermined thickness is formed on the entire surface of the silicon substrate (1) so as to cover the gate electrode (5) and the first silicon layer (20). Subsequently, this is patterned by a photolithography technique to form a first contact hole (25) and a second contact hole (26). Here, the first contact hole (25) is formed on the main surface of the insulator layer (2) so that the outer end surface of the first source region (23) and the side surface of the second channel region (22) are exposed. The second contact hole (26) is opened so as to partially expose the main surface of the first drain region (24) (FIG. 2 (g)).

Next, a film to be a conductor layer, in this case, a polycrystalline silicon film is formed on the entire surface of the interlayer insulating film (9) so as to fill the first contact hole (25) and the second contact hole (26). It is formed to a film thickness. Subsequently, this is patterned by photolithography technology. As a result, the source electrode (27) joined to the first source region (23), the second channel region (22) and the insulator layer (2) is formed through the first contact hole (25), Further, the drain electrode (28) joined to the drain electrode (24) is formed. The second channel region (22) on the left side of the drawing is provided to obtain an ohmic electrical connection between the source electrode (27) and the first channel region (21) (Fig. 2 (h)).

In this way, the SOI-MOSFET is completed. This SOI
-The operation of the MOSFET is basically the same as that shown in the prior art, and therefore its description is omitted. In the operation of this structure, holes generated by impact ionization in the first channel region (21) are quickly extracted from the second channel region (22) to the source electrode (27), and the first silicon layer ( When the thickness of 20) is thick, the kink effect is likely to occur, and when it is thin, the breakdown voltage between the source and drain, which is likely to occur, is prevented.

FIG. 3 is a sectional view showing another structure of the SOI-MOSFET related to the present invention. In this structure, the fourth channel regions (42) (42) corresponding to the second channel regions (22) (22) shown in FIG. 1 have the first source region (23) and the first channel region (23) respectively. The structure extends to the boundary on the inner center side of the drain region (24), and has the third channel region (41) between them. If the second silicon layer (40) of this is thin, for example, about 1000 Å, in the case of FIG. 1, the first source region (23) and the first drain region (24) are the first silicon layer (40). Although it may reach the lower end of 20), the third channel region (42) (42) having a high impurity concentration is connected to the second source region (43),
By forming the second drain region (44) on substantially the entire lower surface of the second drain region (44), a channel region having an opposite conductivity type to the second drain region (44) can be extended to the end of the second silicon layer (40).

FIG. 4 is a sectional view showing the structure of an SOI-MOSFET according to an embodiment of the present invention. This is the third silicon layer (5
0) on the third source region (53) and the third drain region (54), respectively.
5), having a fourth drain region (56) and having sidewalls (57) (57) on the drain side sidewalls of the gate electrode (5) and the third silicon layer (50). There is.

 This is formed as in the step shown in FIG.

First, the insulator layer (2) is formed on the main surface of the silicon substrate (1).
Is formed to a predetermined thickness, and then a layer (61) to be a third silicon layer is formed thereon. After that, a p-type impurity, in this case, boron is ion-implanted (not shown) into the layer (61) to be the third silicon layer. As a result, a region to be the fifth channel region (51) is formed. This region is formed at an impurity concentration of 10 ¹⁶ to 10 ¹⁷ atoms / cm ³ , for example. The layer that will become the third silicon layer (61) is then patterned by photolithographic techniques. Then, a silicon oxide film, a polycrystalline silicon film, and a silicon nitride film are formed to a predetermined film thickness on the layer (61) to be the third silicon layer, and a resist is further formed thereon. Photoresist patterned by photolithography technology (63)
Then, using the register pattern (63) as a mask, the underlying silicon nitride film, polycrystalline silicon film, and silicon oxide film are sequentially and selectively removed by etching, for example, by RIE. As a result, the gate electrode (5) and the gate insulating film (4) having the patterned silicon nitride film (63) thereon are formed (FIG. 5A).

Next, p-type impurities, in this case, boron, n-type impurities, in this case, arsenic are sequentially ion-implanted (not shown) from above the silicon substrate (1) under predetermined conditions. At this time, the n-type impurity region is formed shallow and the p-type impurity region is formed deep. After that, the resist (63) serving as a mask is removed by an ashing method or the like, and the silicon substrate (1) is heat-treated at a predetermined temperature to form p-type and n-type diffusion layers, respectively. This n-type diffusion layer is the third source region (5
3), which will become the third drain region (54),
It is formed at an impurity concentration of ¹⁸ to 10 ¹⁹ atoms / cm ³ . These lower parts have a high p-type impurity concentration, for example, 10 ¹⁹ to 10 ²⁰ atom
A sixth channel region (52) having s / cm ³ is formed. Further, a fifth channel region (51) is formed in a region sandwiched by the third source region (53), the third drain region (54) and the sixth channel regions (52) (52). Here, the third silicon layer (50) composed of these is formed (FIG. 5B).

Next, the gate electrode (5) part and the third silicon layer (50)
A silicon oxide film is formed to have a predetermined thickness by a CVD method or the like so as to cover the exposed portion of. After this, it has anisotropic properties
The entire surface of the silicon oxide film is etched by RIE.
When the silicon nitride film (62) and the third silicon oxide film (50) are removed by etching so as to expose the respective main surfaces, the gate electrode (5) and the gate insulating film (4 ) And side walls of the third silicon layer (50) are formed with side walls (57) and (57) (FIG. 5 (c)).

Next, the silicon substrate (1) is subjected to selective epitaxial treatment. As a result, epitaxial growth is selectively performed on the main surface portions of the third source region (53) and the third drain region (54) where silicon is exposed, and the fourth source region (55) and the fourth source region (55) are respectively formed. A drain region (56) is formed.
These regions (56) (56) have an impurity concentration of, for example, 10
It is formed at ¹⁹ to 10 ²¹ atoms / cm ³ . After that, the silicon nitride film (62) which has worked as an oxidation resistant film on the main surface portion of the gate electrode (5) during the selective epitaxial treatment is removed (fifth step).
Figure (d)).

Next, an interlayer insulating layer (9) having a predetermined thickness is formed so as to cover the gate electrode (5) and the third silicon film (50), and the interlayer insulating layer (9) is selectively removed by a photolithography technique.
The contact hole (58) and the fourth contact hole (59) are formed. The third contact hole (58) has an outer end portion of the fourth source region (55), a side surface portion of the third source region (53), a side surface portion of the sixth channel region (52), and insulation. A hole is formed so that a part of the main surface of the body layer (2) is exposed,
Further, the fourth contact hole (59) is opened so that a part of the main surface of the fourth drain region (56) is exposed.
After that, a film to be a conductor layer, for example, a polycrystalline silicon film is formed on the interlayer insulating film (9) to a predetermined film thickness so as to fill the third contact hole (58) and the fourth contact hole (59). Then, a conductor layer, in this case, a source electrode (27) and a drain electrode (28) is formed by patterning and selectively removing it. This source electrode (27) has a fourth
The source region (55), the third source region (53), and the sixth channel region (52), and the insulator layer (2), and the drain electrode (28) is Four
Is joined to the drain region (56) (FIG. 5 (e)).

According to the SOI-MOSFET having such a structure, the fourth source region (55) as an upper layer source region and the fourth drain region (as an upper layer drain region) on the third silicon layer (50) as a semiconductor layer ( By having 56), the third source region (53) and the third drain region (54)
Even if the thickness of the MOS transistor is relatively thin, the thickness of the source / drain region including the upper layer and the lower layer can be secured to such an extent that a sufficiently low electric resistance required for the characteristics of the MOS transistor can be obtained. . In addition, when the sidewall insulating films (57) are formed on both ends of the gate electrode (5) by anisotropic etching, the third silicon layer is over-etched, and the third source region (53) and the third source region (53) are formed. The fourth source region (55) and the fourth drain region (56) even if the drain region (54) of the
Due to the presence of the
Since the thickness of the drain region can be secured to the extent that a sufficiently low electric resistance required for the characteristics of the MOS transistor can be obtained, a sufficient margin for such overetching is secured and the etching end point control is performed. You can also reduce the severity of

Further, according to the structure of the present embodiment, the source electrode (27) is formed in the third contact hole (58) and is connected to the sixth channel region (52), so that the source electrode is a substrate. Since it also serves as an electrode, surplus carriers generated by impact ionization in the semiconductor layer can be easily extracted by this source electrode.
This prevents the kink effect and the deterioration of the breakdown voltage between the source and the drain from being caused.

FIG. 6 is a sectional view showing still another structure of the SOI-MOSFET related to the present invention. This has a structure in which the second channel region (22) in the first silicon layer (20) shown in FIG. 1 is formed below the first source region (23), but the first drain region is formed. It has a structure which becomes a fourth silicon layer (60) not formed under (24).

FIG. 7 is a sectional view showing still another structure of the SOI-MOSFET related to the present invention. In this structure, a fourth channel region (42) in the second silicon layer (40) shown in FIG. 3 is formed below the second source region (43), but a second drain region ( It has a structure which will become a fifth silicon layer (70) not formed under 44).

Also in the structures shown in FIGS. 6 and 7,
It has the same effect as the above.

In the description of the above embodiment, the silicon layer (2
N-channel MOSFET in which the channels formed in (0), (40), (50), (60) and (70) are n-channels
However, the present invention is not limited to this, and a p-channel MOSFET can be formed by changing the conductivity type, and the same effect as above can be obtained in this case as well.

[Effects of the Invention] As described above, according to the configuration of the present invention described in claim 1, since the upper layer source region and the upper layer drain region are provided on the semiconductor layer, the source / drain in which the upper layer and the lower layer are combined is formed. It becomes easy to secure the thickness of the region to the extent that a sufficiently low electric resistance required for the characteristics of the MOS transistor can be obtained. For example, when the sidewall insulating films are formed on both ends of the gate electrode by anisotropic etching. It is also possible to secure a sufficient margin for over-etching in (1) and reduce the strictness of the end point control of etching.

According to the semiconductor device of the present invention as set forth in claim 2, since the source electrode is also connected to the channel region and also serves as the substrate electrode, surplus carriers generated by impact ionization in the semiconductor layer can be easily generated by the source electrode. It is possible to pull it out, thereby avoiding the kink effect and the deterioration of the source-drain breakdown voltage.

In addition, the synergistic effect of being able to reduce the resistance to carrier flow in the channel region and the fact that the source electrode is connected to the channel region makes the above-mentioned action of extracting excess carriers more remarkable, and -It has a unique effect that the characteristics of the MOSFET can be further improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a structure of an SOI-MOSFET of a first embodiment of the present invention, and FIGS. 2 (a) to 2 (h) show a manufacturing process of the one shown in FIG. FIG. 3 is a sectional view showing the structure of the SOI-MOSFET of the second embodiment of the present invention, FIG. 4 is a sectional view showing the structure of the SOI-MOSFET of the third embodiment of the present invention, 5 (a) to 5 (e) are sectional views showing the manufacturing process of the one shown in FIG. 4, and FIG. 6 is a SOI-MOSFE of the fourth embodiment of the present invention.
FIG. 7 is a sectional view showing the structure of T, FIG. 7 is a sectional view showing the structure of the SOI-MOSFET of the fifth embodiment of the present invention, and FIG. 8 is a conventional SOI.
FIG. 3 is a cross-sectional view showing the structure of a MOSFET. In the figure, (2) is an insulator layer, (4) is a gate insulating film, (5) is a gate electrode, (20) is a first silicon layer,
(21) is the first channel region, (22) is the second channel region, (23) is the first source region, (24) is the first drain region, (27) is the source electrode, (28) Is a drain electrode, (40) is a second silicon layer, (41) is a third channel region, (42) is a fourth channel region, (43) is a second source region, and (44) is a second channel region. Drain region of (5
(0) is the third silicon layer, (51) is the fifth channel region, (52) is the sixth channel region, (53) is the third source region, (54) is the third drain region, ( 55) is the fourth
Is a source region, (56) is a fourth drain region, (60) is a fourth silicon layer, and (70) is a fifth silicon layer. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. An insulating base, a semiconductor layer formed on the insulating base, a gate electrode formed on the semiconductor layer with a gate dielectric thin film interposed therebetween, and a gate electrode having both ends, and the gate electrode on both sides. It is sandwiched between the lower layer source region and the lower layer drain region formed at a position sandwiched from the end side to a predetermined depth from the semiconductor layer surface, and at least the lower layer source region and the lower layer drain region on the semiconductor layer surface. A channel region formed in a closed region, the lower source region and the lower drain region, on the surface of the semiconductor layer, the gate electrode is formed via an insulating film, from the epitaxial layer doped with impurities A semiconductor device having an upper layer source region and an upper layer drain region. 2. A source electrode is further provided, wherein the channel region is formed between a region below the gate electrode and a region below the lower source region and the lower drain region in the semiconductor layer, A source electrode is formed in the upper layer source region, the lower layer source region, and a contact hole formed under the channel region below the lower layer source region, thereby forming the upper layer source region, the lower layer source region, and the source electrode. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the channel region.