JP3038740B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an integrated circuit (Bi-type) in which a complementary field effect transistor (CMOS transistor) and a bipolar transistor are formed on the same semiconductor substrate. CMOS IC).

[Conventional technology]

High-speed operation and high drive capability of bipolar transistors and
Many attempts have been made for Bi-CMOS ICs which have the performance of both CMOS transistors and are formed on the same semiconductor substrate due to recent demands for low power consumption and high speed.

3A to 3I are cross-sectional views in the order of steps of a conventional method for manufacturing a Bi-CMOS IC.

First, as shown in FIG. 3A, an N ⁺ -type buried region 2 and a P ⁺ -type buried region 3 are formed in a P-type semiconductor substrate 1 made of silicon.
Is formed, and then an N-type epitaxial region 4 is formed,
This surface is thermally oxidized to form a first silicon dioxide layer 5 having a thickness of 600 to 800.degree. And selectively ion-implanted to form a P-type for an N-channel MOSFET formation region and a bipolar transistor isolation region. A well region 6 is formed, and an N-type well region 7 for a P-channel MOSFET formation region is formed by selective ion implantation.

Next, as shown in FIG. 3B, a silicon nitride layer 9 is formed on the surface of the first silicon dioxide layer 5 by using a CVD technique. Further, the silicon nitride layer 9 in a region where an element isolation oxide film is to be formed is selectively removed by anisotropic etching, and an element isolation oxide film 10 is formed by thermal oxidation.

Next, as shown in FIG. 3C, the silicon nitride layer 9 is removed by an etching technique, ion implantation for adjusting the threshold of the N-channel MOSFET is performed using a mask, and further, for example, the photoresist 11 is removed. Using such a mask, ion implantation for adjusting the threshold of the P-channel MOSFET is performed.

Next, as shown in FIG. 3D, the first silicon dioxide layer 5 is removed by an etching technique, and a gate oxide film 12 having a thickness of 200 to 300 ° is formed by thermal oxidation. An opening is formed in a region where a collector is to be formed.
Subsequently, for example, an N ⁺ type polycrystalline silicon layer 13 containing phosphorus,
For example, a silicide layer 14 of tungsten silicide, molybdenum silicide, or the like is attached and formed by a CVD technique.
Further, a silicon / silicide structure is formed on the region where the collector is to be formed and the region where the gate electrode of the MOSFET is to be formed by a well-known anisotropic etching using a mask. Here, there is a method in which the gate electrode is formed only of the polycrystalline silicon layer. Next, by heat treatment, an N ⁺ -type collector region 8 is formed by thermal diffusion from the N ⁺ -type polycrystalline silicon layer 13 on the collector formation planned region.

Next, as shown in FIG.
The low-concentration P-type diffusion region 15 and the low-concentration N-type diffusion region 16 of the N-channel MOSFET are formed using a mask. Subsequently, a second silicon dioxide layer 18 having a thickness of 2000 to 3000 ° is deposited by CVD.

Next, as shown in FIG. 3 (f), the second silicon dioxide layer 18 is etched back using a known anisotropic etching technique to form a sidewall 18a.

At this time, a region for forming a high-concentration source / drain of a MOSFET (a region for forming a high-concentration P-type diffusion region of a P-channel MOSFET and a region for forming a high-concentration N-type diffusion region of an N-channel MOSFET are planned) The gate oxide film 12 on the region (the region in which the gate oxide film is formed) is also removed.

Next, as shown in FIG. 3 (g), the P-type base formation region of the bipolar transistor and the high concentration source / drain formation region of the MOSFET are 500 to 100
A third silicon dioxide layer 25 having a thickness of 0 ° is formed. Subsequently, a P-type base region 17 of a bipolar transistor, a high-concentration N-type diffusion region 19 of an N-channel MOSFET, and a high-concentration P-type diffusion region 20 of a P-channel MOSFET are formed by ion implantation using a mask.

Next, as shown in FIG.
A fourth silicon dioxide layer 26 having a thickness of 0 to 2000 ° is formed. Subsequently, the emitter diffusion window of the bipolar transistor is opened using a mask, a second N ⁺ -type polycrystalline silicon layer 22 containing, for example, phosphorus is deposited by a CVD technique, and a known anisotropic etching using a mask is performed. As a result, the second N ⁺ -type polycrystalline silicon layer 22 is formed to remain so as to cover the emitter diffusion window.

Finally, as shown in FIG. 3 (i), the base contact region 21 and the emitter region of the bipolar transistor
23 are formed, and a lead-out electrode 28 is formed by a wiring forming process using an existing method.

[Problems to be solved by the invention]

According to the above-described conventional method for manufacturing a Bi-CMOS IC, when the second silicon dioxide layer 18 is etched back by anisotropic etching to form the sidewalls 18a, the portions other than the sidewall forming portions are formed. The second silicon dioxide layer 18 must be completely removed from the surface.

Assuming that the time for etching and removing the second silicon dioxide layer 18 from the surface other than the side wall formation portion is x,
Normally 1.2x to 1.25x, that is, 20% in consideration of the variation in the thickness of the second silicon dioxide layer 18 and the variation in etching.
25% overetching is performed, but only the gate oxide film 12 with a thickness of 200 to 300 mm remains on the region where the P-type base of the bipolar transistor is to be formed and the region where the high concentration source / drain of the MOSFET is to be formed at the time of the overetching. In particular, the silicon surface of the region where the P-type base of the bipolar transistor is to be formed is directly exposed to the anisotropic etching.

If the silicon surface of the region where the P-type base of the bipolar transistor is to be formed is over-etched by about 10% or more, the leakage current at the silicon surface between the emitter and the base of the bipolar transistor increases, and the electrical characteristics are greatly deteriorated. .

Further, in the future, higher integration is progressing, and the gate oxide film tends to be thinner. At this time, the silicon surface in the region where the P-type base is to be formed is further damaged. It is difficult to make the gate oxide film thinner than this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a Bi-CMOS IC in consideration of high integration of a MOSFET without causing deterioration in electric characteristics of a bipolar transistor as described above. It is in.

[Means for solving the problem]

The first aspect of the method of manufacturing a semiconductor device according to the present invention is that an LDD type first conductivity type MOS is formed on the same semiconductor substrate made of silicon.
In a method of manufacturing a semiconductor device including a field effect transistor, an LDD-type second conductivity type MOS field effect transistor, and a bipolar transistor, a first silicon dioxide layer having a predetermined thickness is formed on a surface of a semiconductor substrate by thermal oxidation. Forming an element isolation oxide film in a required region on the surface of the semiconductor substrate by a selective oxidation method to form a first conductive type MOS field effect transistor forming region, a second conductive type MOS field effect transistor forming region, and a bipolar transistor; Defining a transistor formation region on the surface of the semiconductor substrate, and using the first photoresist covering the second conductivity type MOS field effect transistor formation region and the bipolar transistor formation region as a mask, Performing a first ion implantation for threshold adjustment in a region where the type MOS field effect transistor is to be formed, A step of selectively removing the first silicon dioxide layer in the region in which the one-conductivity-type MOS field-effect transistor is to be formed; and a step of removing the first photoresist to form the region in which the first-conductivity-type MOS field-effect transistor is to be formed. Using the second photoresist covering the region where the polar transistor is to be formed as a mask, a second ion implantation for adjusting the threshold is performed in the region where the second conductivity type MOS field effect transistor is to be formed, thereby forming the second conductivity type MOS field effect. A step of selectively removing the first silicon dioxide layer in the region where the transistor is to be formed; a step of removing the second photoresist; and a region where the first conductivity type MOS field effect transistor is to be formed and the second conductivity type MOS by thermal oxidation. A gate oxide is formed in an area where a field effect transistor is to be formed, and
Forming a gate oxide film also at the interface between the first silicon dioxide layer left in the bipolar transistor formation region and the semiconductor substrate; and forming the first silicon dioxide layer in the collector formation region in the bipolar transistor formation region And selectively removing the gate oxide film;
At least the bottom is formed on the entire surface with a conductor film composed of a high-concentration N-type polycrystalline silicon layer, and the first conductivity type is formed by anisotropic etching of the conductor using a third photoresist as a mask.
A gate electrode is formed in each of the regions where the MOS field effect transistor and the second conductivity type MOS field effect transistor are to be formed, and a conductor film is left in a portion covering the region where the collector is to be formed. Forming a first collector type diffusion region in a region where a first conductivity type MOS field effect transistor is to be formed, and forming a lower concentration first conductivity type diffusion region in a region where a second conductivity type MOS field effect transistor is to be formed. Forming a two-conductivity-type diffusion region, forming a second silicon dioxide layer on the entire surface by CVD technology, anisotropically etching the second silicon dioxide layer to form sidewalls on the side surfaces of the gate electrode. Forming a P-type base region in a region where a bipolar transistor is to be formed, and forming a high-concentration first conductive region in a region where a first conductivity type MOS field effect transistor is to be formed. The diffusion region is formed, the second
Forming a high-concentration second-conductivity-type diffusion region in a region where a conductive-type MOS field-effect transistor is to be formed, forming a base contact region in a region in which a bipolar transistor is to be formed, and further forming an emitter region. I have.

A second aspect of the method for manufacturing a semiconductor device according to the present invention is that an LDD type first conductivity type MOS is formed on the same semiconductor substrate made of silicon.
In a method of manufacturing a semiconductor device including a field effect transistor, an LDD-type second conductivity type MOS field effect transistor, and a bipolar transistor, a first silicon dioxide layer having a predetermined thickness is formed on a surface of a semiconductor substrate by thermal oxidation. Forming an element isolation oxide film in a required region on the surface of the semiconductor substrate by a selective oxidation method to form a first conductive type MOS field effect transistor forming region, a second conductive type MOS field effect transistor forming region, and a bipolar transistor; Defining a transistor formation region on the surface of the semiconductor substrate; and forming a first conductivity type MOS field effect transistor formation region, a second conductivity type MOS field effect transistor formation region, and a bipolar transistor formation region. Using a first photoresist having an opening in a region where a collector is to be formed as a mask, a first conductivity type MOS is formed. Selectively removing the first silicon dioxide layer in the field-effect transistor formation region, the second conductivity type MOS field-effect transistor formation region, and the collector formation region, and removing the first photoresist to remove heat. Oxidation is used to form gate oxidation in the region where the first conductivity type MOS field effect transistor is to be formed, the region where the second conductivity type MOS field effect transistor is to be formed, and the region where the collector is to be formed. A step of forming a gate oxide film also at the interface between the remaining first silicon dioxide layer and the semiconductor substrate; a step of selectively removing the gate oxide film in a region where a collector is to be formed; A conductor film made of a polycrystalline silicon layer is formed on the entire surface, and a third photoresist is used as a mask. Gate electrodes are respectively formed in regions where the first conductivity type MOS field effect transistor and the second conductivity type MOS field effect transistor are to be formed by anisotropic etching, and a conductor film is left in a portion covering the region where the collector is to be formed. Forming a high-concentration N-type collector region in a region where a collector is to be formed, and forming a low-concentration first-conductivity-type diffusion region in a region where a first-conductivity-type MOS field-effect transistor is to be formed; Forming a low-concentration second-conductivity-type diffusion region in a region to be formed;
A second silicon dioxide layer is formed on the entire surface by a technique, the second silicon dioxide layer is anisotropically etched to form sidewalls on side surfaces of the gate electrode, and a P-type is formed in a region where a bipolar transistor is to be formed. Forming a base region; forming a high-concentration first-conductivity-type diffusion region in a region where a first-conductivity-type MOS field-effect transistor is to be formed;
Forming a high-concentration second conductivity type diffusion region in a region where an S field effect transistor is to be formed, forming a base contact region in a region where a bipolar transistor is to be formed, and further forming an emitter region.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIGS. 1 (a) to 1 (e) show Bi- of the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing main steps of a method for manufacturing a CMOS IC.

First, as shown in FIG. 1A, an N ⁺ -type buried region 2 and a P ⁺ -type buried region 3 are formed on a P-type semiconductor substrate 1 made of silicon by using a conventional manufacturing method. Type epitaxial region 4 is formed and the surface is thermally oxidized to 600
A first silicon dioxide layer 5 having a thickness of about 800 ° is formed. Further, a P-type well region 6 and an N-type well region 7 are formed, a silicon nitride layer (not shown) is formed, and the silicon nitride layer in a region where an element isolation oxide film is to be formed is selectively formed by anisotropic etching. Then, an element isolation oxide film 10 is formed by a selective oxidation method, and the silicon nitride layer is removed to define respective regions where N-channel MOS transistors, P-channel MOS transistors, and bipolar transistors are to be formed.

Next, as shown in FIG.
Is used as a mask to perform ion implantation for adjusting the threshold of the N-channel MOSFET, and then the first silicon dioxide layer 5 in the mask opening is removed.

Next, as shown in FIG.
Using a as a mask, ion implantation for threshold adjustment of the P-channel MOSFET is performed, and then the first silicon dioxide layer 5 in the mask opening is removed.

Next, as shown in FIG.
A gate oxide film 12 having a thickness of about 300 ° is formed. At this time, in the region where the bipolar transistor is to be formed,
Since thermal oxidation proceeds also at the interface between the remaining first silicon dioxide layer 5 and the N-type epitaxial region 4, a gate oxide film 12 is also formed at this interface. Subsequently, the first silicon dioxide layer 5 and the gate oxide film 12 on the region where the collector of the bipolar transistor is to be formed are sequentially removed by etching to open the region where the collector is to be formed.

Subsequently, for example, an N ⁺ type polysilicon layer 13 containing phosphorus
Then, a silicide layer 14 of, for example, tungsten silicide or molybdenum silicide is formed by CVD. Further, a silicon / silicide structure is formed on the region where the collector is to be formed and the region where the gate electrode of the MOSFET is to be formed by a well-known anisotropic etching using a mask. Here, there is a method in which the gate electrode is formed only of the polycrystalline silicon layer.

Next, by heat treatment, an N ⁺ -type collector region 8 is formed by thermal diffusion from the N ⁺ -type polycrystalline silicon layer 13 on the collector formation planned region.

Next, as shown in FIG. 1 (e), by using the conventional manufacturing method, the low-concentration P-type diffusion region 15 of the P-channel MOSFET and the low-concentration N-type diffusion region 16 of the N-channel MOSFET are formed.
Is formed, and a second silicon dioxide layer 18 having a thickness of 2000 to 3000 DEG is deposited by CVD.

Next, sidewalls are formed by anisotropic etching. The gate oxide films 12 and 60 of 200 to 300 ° are formed on the regions where the P-type base of the bipolar transistor is to be formed.
Since the first silicon dioxide layer 5 of 0 to 800 ° remains, even when overetching, the P
The silicon surface in the region where the mold base is to be formed is not directly exposed to anisotropic etching.

The subsequent steps up to the step of forming the extraction electrode are the same as in the conventional manufacturing method.

In this embodiment, the element isolation oxide film 10 is formed by using the silicon nitride layer as a mask, the silicon nitride layer is then etched away, and the first and second regions on the P-type base formation region of the bipolar transistor are to be formed by using the masks of the photoresists 24 and 24a. Although the first silicon dioxide layer 5 is left protected from the etching, the silicon nitride layer and the first silicon dioxide layer 5 are all removed by etching, a new thermal oxide film is formed, and this thermal oxide film is bipolar. There is also a method in which a transistor is left over a region where a P-type base is to be formed.

FIGS. 2 (a) to 2 (c) show Bi- of the second embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main step in a method for manufacturing a CMOS IC.

First, as shown in FIG. 2A, an N ⁺ -type buried region 2, a P ⁺ -type buried region 3, and an N-type buried region 3 are formed on a P-type substrate 1 by using the same manufacturing method as in the first embodiment. Epitaxial region 4,600 ~
800Å thick first silicon dioxide layer 5, P-type well region
6, an N-type well region 7 and an element isolation oxide film 10 are formed. Subsequently, the first silicon dioxide layer 5 on the region where the P-type base of the bipolar transistor is to be formed is protected by a mask such as a photoresist 24b, and the first silicon dioxide layer 5 in other portions is removed by etching. I do.

Next, as shown in FIG.
A gate oxide film 12 having a thickness of about 300 ° is formed. At this time, in the region where the P-type base of the bipolar transistor is to be formed, 600 to 800 °
The gate oxide film 12 is formed in such a manner that the first silicon dioxide layer 5 is stacked.

Next, as shown in FIG. 2C, the gate oxide film 12 on the region where the collector of the bipolar transistor is to be formed is removed by etching to open the region where the collector is to be formed. Subsequently, an N ⁺ -type polycrystalline silicon layer 13 containing, for example, phosphorus and a silicide layer 14 made of, for example, tungsten silicide or molybdenum silicide are deposited by CVD.
Further, a silicon / silicide structure is formed on the region where the collector is to be formed and the region where the gate electrode of the MOSFET is to be formed by a well-known anisotropic etching using a mask. Then, the low concentration P-type diffusion region of the P-channel MOSFET
15 and a lightly doped N-type diffusion region 16 of an N-channel MOSFET are formed, and a second silicon dioxide layer 18 having a thickness of 2000 to 3000.degree.

The subsequent steps up to the step of forming the extraction electrode are the same as in the conventional manufacturing method.

〔The invention's effect〕

As described above, the present invention provides a method of manufacturing an LD on the same semiconductor substrate.
In a method of manufacturing a semiconductor device including a D-type MOS field-effect transistor and a bipolar transistor, a silicon dioxide layer formed by thermal oxidation formed before gate oxidation is left on a region where a base of a bipolar transistor is to be formed. In this case, a silicon dioxide layer having a thickness obtained by adding the thickness of the gate oxide film is formed by performing the gate oxidation oxidation.

Therefore, when the sidewall is formed by anisotropic etching, the silicon surface in the region where the base of the bipolar transistor is to be formed can be prevented from being directly exposed to the etching.

From this, the emitter of the bipolar transistor
It is possible to prevent deterioration of electrical characteristics due to an increase in leakage current on the silicon surface between the bases.

Further, the method for manufacturing a semiconductor device according to the present invention can sufficiently cope with a case where the degree of integration of the semiconductor device is further advanced and the gate oxide film is further thinned.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (e) are sectional views in the order of steps of a first embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are second embodiments of the present invention. FIGS. 3 (a) to 3 (i) are cross-sectional views in the order of steps in a conventional example. 1 ... P-type semiconductor substrate, 2 ... N ⁺ type buried region, 3 ...
P ⁺ type buried region, 4 ... N-type epitaxial region, 5 ...
... First silicon dioxide layer, 6... P-type well region, 7
... N-type well region, 8 ... N ⁺ type collector region, 9 ...
Silicon nitride layer, 10 ... Device isolation oxide film, 11, 24, 24a, 24
b ... Photoresist, 12 ... Gate oxide film, 13 ... N ⁺
Type polycrystalline silicon layer, 14 silicide layer, 15 low concentration P type diffusion region, 16 low concentration N type diffusion region, 17 P
Mold base region, 18 ... second silicon dioxide layer, 18a ...
... side wall, 19 ... high concentration N-type diffusion region, 20 ...
High-concentration P-type diffusion region, 21 Base contact region, 22
... A second N ⁺ -type polycrystalline silicon layer, 23 an emitter region, 25 a third silicon dioxide layer, 26 a fourth silicon dioxide layer, 27 a fifth silicon dioxide Layer, 28 ……
Leader electrode.

Claims (2)

(57) [Claims] An LDD is formed on the same semiconductor substrate made of silicon.
Type first conductivity type MOS field effect transistor and LDD type second field effect transistor
In a method of manufacturing a semiconductor device including a conductive type MOS field effect transistor and a bipolar transistor, a first silicon dioxide layer having a predetermined thickness is formed by thermal oxidation on a surface of the semiconductor substrate, and the first silicon dioxide layer is formed by a selective oxidation method. Forming an element isolation oxide film in a required area on the surface of the semiconductor substrate,
Defining a region for forming a first conductivity type MOS field effect transistor, a region for forming a second conductivity type MOS field effect transistor, and a region for forming a bipolar transistor on the surface of the semiconductor substrate; Using the first photoresist covering the transistor formation region and the bipolar transistor formation region as a mask, a first ion implantation for threshold adjustment is performed in the first conductivity type MOS field effect transistor formation region. Selectively removing the first silicon dioxide layer in a region where a first conductivity type MOS field effect transistor is to be formed; removing the first photoresist;
Second ion implantation for threshold adjustment is performed in the second conductive type MOS field effect transistor formation region using the second photoresist covering the region where the field effect transistor is to be formed and the region where the bipolar transistor is to be formed as a mask. Selectively removing the first silicon dioxide layer in the region where the second conductivity type MOS field effect transistor is to be formed; removing the second photoresist, and thermally oxidizing the first conductive layer. Forming a gate oxide in a region where a type MOS field effect transistor is to be formed and a region where a second conductivity type MOS field effect transistor is to be formed, and forming the first silicon dioxide layer and the semiconductor substrate remaining in the region where the bipolar transistor is to be formed; Forming the gate oxide film also at the interface of the bipolar transistor; Selectively removing the first silicon dioxide layer and the gate oxide film in a region where a collector is to be formed in the collector formation region, and forming a conductive film at least a bottom portion of a high-concentration N-type polycrystalline silicon layer on the entire surface. The first is performed by anisotropic etching of the conductor using the photoresist of No. 3 as a mask.
A gate electrode is formed in each of the regions where the conductive type MOS field effect transistor and the second conductive type MOS field effect transistor are to be formed, and the conductor film is left in a portion covering the region where the collector is to be formed. Forming a high-concentration N-type collector region in a region; forming a low-concentration first-conductivity-type diffusion region in a region where the first-conductivity-type MOS field-effect transistor is to be formed; Forming a low-concentration second-conductivity-type diffusion region in the region to be formed; forming a second silicon dioxide layer on the entire surface by CVD; and anisotropically etching the second silicon dioxide layer Forming a sidewall on a side surface of the gate electrode and forming a P-type base region in a region where the bipolar transistor is to be formed; Forming a high-concentration first-conductivity-type diffusion region in the region where the transistor is to be formed, forming a high-concentration second-conductivity-type diffusion region in the region where the second-conductivity-type MOS field-effect transistor is to be formed, and forming the bipolar transistor; Forming a base contact region in the region and further forming an emitter region. 2. An LDD is formed on the same semiconductor substrate made of silicon.
Type first conductivity type MOS field effect transistor and LDD type second field effect transistor
In a method of manufacturing a semiconductor device including a conductive type MOS field effect transistor and a bipolar transistor, a first silicon dioxide layer having a predetermined thickness is formed by thermal oxidation on a surface of the semiconductor substrate, and the first silicon dioxide layer is formed by a selective oxidation method. Forming an element isolation oxide film in a required area on the surface of the semiconductor substrate,
Defining a first conductivity type MOS field effect transistor formation region, a second conductivity type MOS field effect transistor formation region, and a bipolar transistor formation region on the surface of the semiconductor substrate; A first photoresist having an opening in a collector formation scheduled region of a transistor formation scheduled region, a second conductivity type MOS field-effect transistor formation scheduled region and a bipolar transistor formation scheduled region is used as a first conductivity type. Selectively removing the first silicon dioxide layer in the region where the MOS field effect transistor is to be formed, the region where the second conductivity type MOS field effect transistor is to be formed, and the region where the collector is to be formed; Is removed, and the first conductive type MOS field effect transistor formation region and the second conductive type MOS field effect transistor are formed by thermal oxidation. Forming a gate oxide in the region where the type MOS field-effect transistor is to be formed and the region where the collector is to be formed, and forming the first silicon dioxide layer remaining in the region where the base is to be formed in the region where the bipolar transistor is to be formed and the semiconductor substrate; A step of forming the gate oxide film also at the interface; a step of selectively removing the gate oxide film in the region where the collector is to be formed; The first conductor is formed by anisotropic etching of the conductor using a third photoresist as a mask.
A gate electrode is formed in each of the regions where the conductive type MOS field effect transistor and the second conductive type MOS field effect transistor are to be formed, and the conductor film is left in a portion covering the region where the collector is to be formed. Forming a high-concentration N-type collector region in a region; forming a low-concentration first-conductivity-type diffusion region in a region where the first-conductivity-type MOS field-effect transistor is to be formed; Forming a low-concentration second-conductivity-type diffusion region in a region to be formed; forming a second silicon dioxide layer on the entire surface by CVD; and anisotropically etching the second silicon dioxide layer Forming a sidewall on a side surface of the gate electrode and forming a P-type base region in a region where the bipolar transistor is to be formed; Forming a high-concentration first-conductivity-type diffusion region in the region where the transistor is to be formed, forming a high-concentration second-conductivity-type diffusion region in the region where the second-conductivity-type MOS field-effect transistor is to be formed, and forming the bipolar transistor; Forming a base contact region in the region and further forming an emitter region.